SONY CXA1992

CXA1992AR
RF Signal Processing Servo Amplifier
Description
The CXA1992AR is a bipolar IC developed for CD
player RF signal processing and servo control.
Features
• Automatic focus bias adjustment circuit
• Automatic tracking balance and gain adjustment
circuits
• RF level control circuit
• Interruption countermeasure circuit
• Sled overrun prevention circuit
• Anti-shock circuit
• Defect detection and prevention circuits
• RF 1-V amplifier, RF amplifier
• APC circuit
• Focus and tracking error amplifier
• Focus, tracking and sled servo control circuits
• Focus OK circuit
• Mirror detection circuit
• Single power supply and dual power supplies
52 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
12
V
• Supply voltage
VCC
• Operating temperature Topr
–20 to +75 °C
• Storage temperature
Tstg
–65 to +150 °C
• Allowable power dissipation
PD
600 mW
Recommended Operating Conditions
Operating supply voltage VCC – VEE 3.0 to 5.5
V
Applications
CD players
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96X16-PS
CXA1992AR
RF_O
RF_I
CP
CB
CC1
CC2
FOK
37
RF_M
PD
38
RFTC
PD1
39
LD
PD2
Block Diagram
36
35
34
33
32
31
30
29
28
27
VEE
RF SUMMING AMP
PD1 IV
AMP
PD2 IV
AMP
FE_BIAS 40
26 SENS2
VCC
APC
IIL
↓
VEE
LASER POWER CONTROL
F 41
VCC
FE AMP
VCC
E 42
25 SENS1
TTL
VCC
F IV AMP
24 C. OUT
E IV AMP
VEE
IFB5
IFB6
IFB4
IFB2
BAL2
BAL4
BAL3
BAL1
IFB3
IFB1
DFCT
EI 43
23
XRST
VEE
LEVEL S
22 DATA
FO. BIAS
WINDOW COMP.
MIRR
IIL
↓
VCC
FOH
FOL
TGH
TGL
BALH
BALL
ATSC
TZC
FZC
TEI 47
ATSC 48
MIRR
LPC
TGFL
LDON
LPCL
FOK
E-F BALANCE
WINDOW COMP.
LPFI 46
TTL
↓
IIL
TTL
TRK. GAIN
WINDOW COMP.
TEO 45
21 XLT
20 CLK
CC1
TOG4
TOG3
TOG2
TOG1
VEE
DFCT1
TGFL
VEE
VEE
VEE 44
IIL DATA REGISTER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
19 LOCK
VCC
ATSC
WINDOW
COMP.
DFCTO
TZC COMP.
TZC 49
IFB1-6
BAL1-4
TOG1-4
FS1-4
TG1-2
TM1-7
18
VCC
17
ISET
16
SL_O
15
SL_M
14
SL_P
PS1-4
ISET
DFCT
TM1
VCC
TRACKING
PHASE COMPENSATION
TDFCT 50
TG1
TM4
VCC
TM6
VCC
VC 51
VCC
TM7
VCC
VEE
FS1
FOCUS
PHASE COMPENSATION
TM3
FZC 52
TM5
VEE
FS2
Charge
up
DFCT
FZC COMP.
VEE
FSET
TG2
FS4
FGD
FLB
FE_O
9
10
11
12
13
TA_O
FDFCT
8
TA_M
FEI
7
FSET
6
TG2
5
TGU
4
SRCH
3
FE_M
2
FEO
VEE
1
–2–
TM2
CXA1992AR
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10µ
25p
1
FEO
147
O
1
174k
10µ
Focus error amplifier output.
Connected internally to the window
comparator input for bias
adjustment.
300µ
2
FEI
I
Focus error input.
147
2
100k
147
3
FDFCT
I
4
FGD
I
3
3µ
Ground this pin through a capacitor
for cutting the focus servo highfrequency gain.
68k
147
Capacitor connection pin for defect
time constant.
4
130k
4µ
40k
330k
External time constant setting pin
for boosting the focus servo lowfrequency.
5
5
FLB
I
6
FE_O
O
13
TA_O
O
470k
Focus drive output.
6
Tracking drive output.
13
16
16
SL_O
250µ
O
147
7
FE_M
I
Sled drive output.
90k
Focus amplifier inverted input.
7
50k
2µ
–3–
CXA1992AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
147
8
SRCH
I
External time constant setting pin for
generating focus search waveform.
20k
8
11µ
50k
110k
9
TGU
External time constant setting pin
for switching tracking highfrequency gain.
147 20k
I
9
82k
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
10
470k
Peak frequency setting pin for focus
and tracking phase compensation
amplifier.
147k
11
FSET
I
11
15k
15k
100k
12
147
TA_M
I
Tracking amplifier inverted input.
12
11µ
14
SL_P
147
I
Sled amplifier non-inverted input.
14
2µ
15
SL_M
I
147
Sled amplifier inverted input.
15
22µ
–4–
CXA1992AR
Pin
No.
17
Symbol
ISET
I/O
I
Equivalent circuit
Description
Connect an external capacitance to
set the current which determines
the Focus search, Track jump, and
Sled kick heights.
147
17
50µ
18
VCC
I
19
LOCK
I
20
CLK
I
Positive power supply.
VCC
18
20µ
19
147
1k
Serial data transfer clock input from
CPU. (no pull-up resistance)
20
22
22
DATA
I
21
XLT
I
The sled overrun prevention circuit
operates when this pin is Low.
(no pull-up resistance)
Serial data input from CPU.
(no pull-up resistance)
20µ
147
Latch input from CPU.
(no pull-up resistance)
2k
21
23
23
XRST
I
24
C. OUT
O
Track number count signal output.
20k
24
25
SENS1
O
Reset input; resets at Low.
(no pull-up resistance)
5p
Outputs FZC, DFCT1, TZC, BALH,
TGH, FOH, ATSC, and others
according to the command from CPU.
147
25
26
26
SENS2
100k
O
Outputs DFCT2, MIRR, BALL, TGL,
FOL, and others according to the
command from the CPU.
20k
147
27
FOK
O
40k
27
100k
–5–
Focus OK comparator output.
CXA1992AR
Pin
No.
28
Symbol
CC2
I/O
Equivalent circuit
Description
Input for the defect bottom hold
output with capacitance coupled.
I
147
147
29
30
29
CC1
Defect bottom hold output.
Connected internally to the
interruption comparator input.
O
147
28
120k
30
CB
11k
I
Connection pin for defect bottom
hold capacitor.
43k
31
Connection pin for MIRR hold
capacitor.
MIRR comparator non-inverted
input.
100k
31
CP
I
32
RF_I
I
33
RF_O
O
1.5k
Input for the RF summing amplifier
output with capacitance coupled.
147
RF sunning amplifier output. Eyepattern check point.
32
147
33
147
34
10k
34
RF_M
I
35
RFTC
I
147
50µ
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
External time constant setting pin
during RF level control.
35
50µ
10µ
–6–
10k
CXA1992AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10k
1k
36
LD
O
APC amplifier output.
36
20µ
8µ
37
PD
I
55k
147
37
APC amplifier input.
10k
10k
8k
2k
38
39
PD1
PD2
I
I
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
147
38
39
100µ
11.6k
4k
Bias adjustment of focus error
amplifier.
Leave this pin open for automatic
adjustment.
147
40
FE_BIAS
I
40
6µ
12p
260k
41
42
F
E
I
I
147
41
42
500
10µ
–7–
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E.
CXA1992AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
6.8k 110k 56k 27k 13k
43
44
EI
VEE
—
147
75k
44
—
147
45
TEO
O
I-V amplifier E gain adjustment.
(When not using automatic balance
adjustment)
260k
43
45
Negative power supply.
VEE
7.5k 16k 7.5k 3.3k 1.5k
150k
10k
Tracking error amplifier output.
E-F signal is output.
150k
Comparator input for balance
adjustment.
(Input from TEO through LPF)
147
46
LPFI
I
46
7µ
47
TEI
I
147
Tracking error input.
100k
47
147
50
TDFCT
I
50
3µ
–8–
Capacitor connection pin for defect
time constant.
CXA1992AR
Pin
No.
Symbol
I/O
Equivalent circuit
Description
1k
100k
147
48
ATSC
I
Window comparator input for ATSC
detection.
48
1k
100k
10µ
10µ
10µ
147
49
TZC
I
Tracking zero-cross comparator
input.
49
75k
51
VC
O
120
50
(VCC + VEE)/2 direct voltage output.
51
120
VC
10µ
51k
147
52
FZC
I
52
Focus zero-cross comparator input.
75k
9k
–9–
CXA1992AR
Electrical Characteristics
TEST
Item
T1
Current
consumption 1
T2
Current
consumption 2
(VCC = 1.5V, VEE = 1.5V, Topr = 25°C)
SD
Input
pin
Measurement pin
51
RST
18
51
RST
SW conditions
(ON switches)
Center amplifier
51, 51D
output offset
RST
T4
Offset
RST
T5
RF amplifier
T3
Voltage gain
33S, 38, 39
Measurement
conditions
Min.
Typ.
Max.
Unit
18
18.4
24.4
34.2
mA
44
44
–34.2 –24.4 –18.4
mA
—
51
–100
0
100
mV
33
–50
0
50
mV
RST
38
39
33
1kHz I/O ratio
25.1
28.1
31.1
dB
Max. output
33D, 38
amplitude - High
RST
38
33
V2 = 0.2VDC
1.2
1.3
—
V
T7
Max. output
amplitude - Low
33D, 39
RST
39
33
V2 = 0.2VDC
—
–0.6
–0.3
V
T8
Offset
1D
39F
38
39
1
1FB6: ON
–120
0
120
mV
T9
Voltage gain 1
1S, 38
(PHD1)
39F
38
1
1kHz I/O ratio
27
30
33
dB
T10
Voltage gain 2
1S, 39
(PHD2)
39F
39
1
1kHz I/O ratio
27
30
33
dB
T11
Voltage gain
difference
39F
–3
0
3
dB
T12
Max. output
1D, 39
voltage – High
39F
39
1
V2 = 100mVDC
1
1.3
—
V
T13
Max. output
voltage – Low
1D, 38
39F
38
1
V2 = 100mVDC
—
–1.3
–1
V
BIAS0
1D
3BF
1
IFB1, 2, 3, 4, 5, 6:
OFF
560
801
1042
mV
T15
BIAS1
1D
3BE
1
IFB1: ON, BIAS0:
reference
–31.3
–25
–18.8
mV
T16
BIAS2
1D
3BD
1
5
6
7
dB
T17
BIAS3
1D
3BB
1
5
6
7
dB
T18
BIAS4
1D
3B7
1
5
6
7
dB
T19
BIAS5
1D
3AF
1
5
6
7
dB
T20
BIAS6
1D
39F
1
5
6
7
dB
T14
FE amplifier
T6
1S
– 10 –
IFB2: ON, BIAS0: reference
Output gain difference with T15
IFB3: ON, BIAS0: reference
Output gain difference with V17
IFB4: ON, BIAS0: reference
Output gain difference with V18
IFB5: ON, BIAS0: reference
Output gain difference with V19
IFB6: ON, BIAS0: reference
Output gain difference with V20
CXA1992AR
TEST
SW conditions
(ON switches)
SD
Input
pin
Measurement pin
Measurement
conditions
FOH threshold 1D, 25D, 40
39F
40
1
Pin 1 voltage when SENS1
Item
Min.
Typ.
Max.
Unit
5
20
35
mV
–35
–20
–5
mV
T21
T22
FE amplifier
IFB6: ON
(Pin 25) goes from High to Low
IFB6: ON
FOL threshold 1D, 26D, 40
39F
40
1
Pin 1 voltage when SENS2
(Pin 26) goes from High to Low
Offset
45D
34F
308
41
42
45
TOG: OFF,
BAL1, 2, 3: ON
–25
0
25
mV
T24
GAIN UP (F)
41, 45S
36F
308
41
45
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
8.6
11.6
14.6
dB
T25
GAIN UP (E)
42, 45S
36F
308
42
45
V1 = 2 kHz, I/O ratio
TOG: OFF, BAL1, 2, 3: ON
8.6
11.6
14.6
dB
T26
Voltage gain
F0
41, 45S
34F
41
45
V1 = 2kHz, TOG: OFF
I/O ratio
2.5
5.5
8.5
dB
T27
Voltage gain
F1
41, 45S
34E
30F
41
45
V1 = 2kHz, TOG1: ON
Reference to F0
–2.6
–2.1
–1.6
dB
T28
Voltage gain
F2
41, 45S
34D
41
45
V1 = 2kHz, TOG2: ON
Reference to F0
–4.4
–3.9
–3.4
dB
T29
Voltage gain
F3
41, 45S
34B
41
45
V1 = 2kHz, TOG3: ON
Reference to F0
–7.7
–7.2
–6.7
dB
Voltage gain
F4
41, 45S
347
41
45
V1 = 2kHz, TOG4: ON
Reference to F0
–12.2 –11.7 –11.2
dB
T31
Voltage gain
E0
42, 45S
34F
30F
00
42
45
V1 = 2kHz, BAL: OFF
I/O ratio
–0.33 2.67
5.67
dB
T32
Voltage gain
E1
42, 45S
30E
42
45
V1 = 2kHz, BAL1: ON
Reference to E0
0.17
0.47
0.77
dB
T33
Voltage gain
E2
42, 45S
30D
42
45
V1 = 2kHz, BAL2: ON
Reference to E0
0.6
0.9
1.2
dB
T34
Voltage gain
E3
42, 45S
30B
42
45
V1 = 2kHz, BAL3: ON
Reference to E0
1.46
1.76
2.06
dB
T35
Voltage gain
E4
42, 45S
307
42
45
V1 = 2kHz, BAL4: ON
Reference to E0
3.03
3.33
3.63
dB
T36
Max. output
41, 45D
voltage – High
34F
308
41
45
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
0.5
0.7
—
V
T37
Max. output
voltage – Low
42, 45D
34F
308
42
45
V1 = 1VDC, TOG: OFF,
BAL1, 2, 3: ON
—
–0.8
–0.5
V
T38
Output voltage
36D, 37
1
3C4
37
36
I37 = 364µA
–900 –694 –500
mV
T39
Output voltage
36D, 37
2
3C4
37
36
I37 = 439µA
–900 –538 –100
mV
T40
Output voltage
36D, 37
3
3C4
37
36
I37 = 515µA
–100
367
800
mV
T41
Output voltage
36, 36D
4
3C4
37
36
0.8mA sink
–200
130
500
mV
T42
LD OFF
3C0
37
36
I37 = 515µA,
LD: OFF
1.1
1.3
—
V
APC
T30
TE amplifier
T23
36, 36D, 37
– 11 –
CXA1992AR
SW conditions
(ON switches)
SD
Input
pin
Measurement pin
50% limit
32, 36D, 37
3C7
37
32
36
17% limit
32, 36D, 37
3C5
37
32
36
–50% limit
36D, 37, 38,
39
3C7
T46
–17% limit
36D, 37, 38,
39
3C5
T47
Direct voltage
gain
2, 6D
T48
FCS total gain
T49
Feed through
1
TEST
Item
T44
T45
RF level controll
T43
37
38
39
37
38
39
36
36
Measurement
conditions
I37 = 273µA
Output difference with LPC ON/OFF
I37 = 394µA
Output difference with LPC ON/OFF
I37 = 742µA
Output difference with LPC ON/OFF
I37 = 621µA
Output difference with LPC ON/OFF
Min.
Typ.
Max.
Unit
300
1020 1510
mV
230
610
1050
mV
–1510 –970 –300
mV
–900 –580
–80
mV
17.8
20.8
23.8
dB
49
51
53
dB
—
—
–30
dB
181
221
261
mV
2
6
—
—
—
00
08
2
6
FZC threshold 26D, 52
00
52
52
Max. output
2, 6D, 6S
voltage – High
08
2
6
V1 = 200mVDC
1
1.3
—
V
T52
Max. output
voltage – Low
2, 6D, 6S
08
2
6
V1 = –200mVDC
—
–1.3
–1
V
T53
Search
voltage (–)
6D
02
—
6
–640 –500 –360
mV
T54
Search
voltage (+)
6D
03
—
6
360
500
640
mV
T55
Direct voltage
gain
13D, 47
25
47
13
12.2
14.6
17.6
dB
T56
TRK total gain
—
—
—
18.1
20.1
22.1
dB
T57
Feed through
1
13S, 47
20
25
47
13
—
—
–39
dB
T58
Max. output
13D, 47
voltage – High
20
25
47
13
V1 = –0.5VDC
1
1.3
—
V
Max. output
voltage – Low
13D, 47
20
25
47
13
V1 = 0.5VDC
—
–1.3
–1
V
Jump output
voltage (–)
13D
2C
13
–640 –500 –360
mV
T61
Jump output
voltage (+)
13D
28
13
360
500
640
mV
T62
ATSC
threshold (–)
10, 10D, 48
10
48
48
–25
–15
–7
mV
T63
ATSC
threshold (+)
10, 10D, 48
10
48
48
7
15
25
mV
T64
TZC threshold
25D, 49,
49B
20
49
49
–20
0
20
mV
T51
T59
T60
Tracking servo
T50
Focus servo
08
2, 6S
– 12 –
T9 + T47
Output gain difference between
SD = 00 and SD = 08.
Pin 52 voltage when SENS1
(Pin 25) goes from Low to High
T26 + T55
Output gain difference between
SD = 20 and SD = 25.
Input voltage when TG2
(Pin 10) goes from Vcc/2 to Vcc
Input voltage when TG2 (Pin 10)
goes from Vcc/2 to Vcc
Pin 49 voltage when
SENS1 (Pin 25) is 0V
CXA1992AR
SD
Input
pin
Measurement pin
BAL COMP
25D, 46,
threshold – High 46B
300
46
46
BAL COMP
26D, 46,
threshold – Low 46B
300
46
46
GAIN COMP
25D, 41,
threshold – High 45D
308
34F
41
45
T68
GAIN COMP
26D, 41,
threshold – Low 45D
308
34F
41
45
T69
FOK
threshold
27D, 32
—
32
32
Pin 32 voltage when
Pin 27 is 0V
T70
Voltage gain
14, 14B, 15,
16S
25
14
16
V1 = 100Hz, I/O ratio
T71
Feed through
14, 14B,
16S
20
25
14
16
T72
Max. output
14, 14B,
voltage – High 16D
25
14
16
Max. output
voltage – Low
14, 14B,
16D
25
14
T74
Kick voltage 1
16D
20
T75
Kick voltage 2
16D
T76
Max. operating
frequency 1
TEST
Item
T73
T77
FOK
Sled servo
T67
MIRROR
T66
Tracking servo
T65
Min. input
operating voltage 1
Max. input
T78
operating voltage 1
SW conditions
(ON switches)
Measurement
conditions
Pin 46 voltage when SENS1
(Pin 25) goes from High to Low
Pin 46 voltage when SENS2
(Pin 26) goes from High to Low
Pin 45 voltage when SENS1
(Pin 25) goes from High to Low
Pin 45 voltage when SENS2
(Pin 26) goes from Low to High
Min.
Typ.
Max.
Unit
5
20
35
mV
–35
–20
–5
mV
350
400
450
mV
260
300
340
mV
–400 –367 –330
mV
50
—
—
dB
—
—
–34
dB
V1 = 400mVDC
1
1.3
—
V
16
V1 = 400mVDC
—
–1.3
–1
V
—
16
REV × 1
–750 –600 –450
mV
20
—
16
FWD × 1
450
600
750
mV
26S, 32
20
32
26
Measures at SENS2
pin.
30
—
—
kHz
26S, 32
20
32
26
Measures at SENS2
pin.
—
—
0.3
Vp-p
26S, 32
20
32
26
Measures at SENS2
pin.
1.8
—
—
Vp-p
Output gain difference between
SD = 20 and SD = 25.
Min. operating
frequency 1
25S, 38, 39
10
38
39
25
Measures at SENS1
pin.
—
—
1
kHz
T80
Max. operating
frequency 1
25S, 38, 39
10
38
39
25
Measures at SENS1
pin.
2.5
—
—
kHz
25S, 38, 39
10
38
39
25
Measures at SENS1
pin.
—
—
0.5
Vp-p
25S, 38, 39
10
38
39
25
Measures at SENS1
pin.
1.8
—
—
Vp-p
T81
T82
DEFECT
T79
Min. input
operating voltage 1
Max. input
operating voltage 1
– 13 –
R3
10k
R1
10k
R2
100
GND
V1
DC
AC
S51D
I51
0mA
C1
1000P
A49
A46
A44
S51I
A50
S49B
S46B
S45D
S45S
S45
C2 33µ
R4
13k
R5
390k
R6
390k
I40
0mA
S52
S51
S50
S49
S48
S47
S46
S43
S42
S41
S40
DC
R7
10k
R8
10k
S1D
52 FZC
51 VC
S3
R10
100
2
1
A3
C3
1000P
3
S4
S5
4
R13
47k
R16
13k
C4
1000P
S7
R19
100
R22
10k
S6D
S6S
R23
200k
7
6
5
R20
100k
S8D
R28
510k
C8
0.01µ
S12
8
R25
10k
27
28
29
30
31
32
33
34
R17
22k
35
S2
S36D
S32
S28
C9
3300p
36
S1S
S36
C7
1000p
37
50 TDFCT
49 TZC
S37
C6
3300p
R35
10k
38
48 ATSC
47 TEI
46 LPFI
45 TEO
44 VEE
43 EI
42 E
41 F
S38
C5
0.1µ
R31
100k
39
40 FE_BIAS
S39
R15
1M
R24
10k
PD2
FEO
AC
R11
10k
S33D S33S
R21
100
PD1
R9
10k
R12 R14
330 10k
R18
10k
PD
FEI
V2
I36
0mA
LD
FLB
VEE
I37
0mA
GND
GND
RFTC
FE_O
– 14 –
FE_M
GND
STORAGE2
RF_M
FDFCT
RF_O
FGD
RF_I
SRCH
CP
S9
R26
10k
S10D
9
TGU
CB
R27
10k
S10
10
TG2
CC1
R29
10k
11
FSET
CC2
R32
100
S13D
S13S
R30
100k
12
TA_M
FOK
R33
200k
13
TA_O
VCC
Electrical Characteristics Measurement Circuit
R49
100
S24S
S25S
S26S
R50
10k
R51
100
R52
100
GND
DATA
XRST
R34
13k
SL_P 14
SL_M 15
SL_O 16
ISET 17
VCC 18
LOCK 19
S14
R36
60k
S16
R42
R41 13k
10k
A14
S15
R44
5.1k
S16D
S16S
R43 120k
S14B
R37
120k
S17
C11 47µ
D_GND
CLK
A18
R45
10k
R46
10k
R47
10k
GND
CLK 20
C10 33µ
S24D
S25D
S26D
R53
100
STORAGE1
GND
XLT
S19
R38
10k
R39
10k
R40
10k
R48
10k
R54
100
GND
XLT 21
DATA 22
XRST 23
C. OUT 24
SENS1 25
SENS2 26
S27D
S27S
GND
DC OUTPUT
CXA1992AR
CXA1992AR
Application Circuit 1 (±2.5V power supply)
Vcc
Vcc
1µ
3.3µ
A
100µ
LD 10µH
PD
C
VEE VEE
E
VEE
36
35
34
33
32
31
PD1
PD
LD
RFTC
RF_M
RF_O
RF_I
CP
FE_BIAS
30
29
28
CC2
37
27
FOK
38
CB
39
PD2
40
0.033µ
CC1
1M
22k 0.01µ
D
F
MICRO
COMPUTER
DSP
1µ
100
500
0.033µ
VEE
B
0.01µ
SENS2
SENS1 25
42 E
C. OUT 24
43 EI
XRST 23
44 VEE
DATA 22
XLT 21
45 TEO
100k
150k
0.01µ
0.01µ
CLK 20
46 LPFI
LOCK 19
47 TEI
0.047µ
47k
330k
470p
26
41 F
Vcc 18
48 ATSC
Vcc
60k
ISET 17
49 TZC
0.022µ
50 TDFCT
SL_O 16
51 VC
SL_M 15
TGU
TG2
FSET
TA_M
8
9
10
11
12
0.1µ
4.7µ
100k
0.1µ
DRIVER
0.015µ 8.2k
3.3µ
13
100k
0.033µ
510k
DRIVER
SL_P 14
82k
SRCH
7
TA_O
FE_O
5
4
3
680k
10k
10k
2200p
6
0.1µ
FLB
2
FGD
1
FE_M
0.022µ
FEI
FZC
FEO
52
FDFCT
0.1µ
VEE
100k
1k
22
22µ 15k
0.015µ
DRIVER
Vcc
Application Circuit 2 (Single +5V power supply)
Vcc
Vcc
1µ
1k
22
3.3µ
A
100µ
LD 10µH
PD
C
E
36
35
34
33
32
31
30
29
28
PD1
PD
LD
RFTC
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FE_BIAS
27
FOK
37
SENS2
SENS1 25
42 E
C. OUT 24
43 EI
XRST 23
44 VEE
DATA 22
45 TEO
XLT 21
46 LPFI
CLK 20
150k
0.01µ
LOCK 19
47 TEI
0.047µ
47k
330k
470p
Vcc 18
48 ATSC
Vcc
60k
ISET 17
49 TZC
0.1µ
10k
10k
TG2
FSET
TA_M
6
7
8
9
10
11
12
4.7µ
0.1µ 0.1µ 0.1µ 100k
DRIVER
TA_O
TGU
5
SRCH
4
3
680k
FE_O
2
DRIVER
0.015µ
8.2k
FE_M
1
FGD
FZC
FDFCT
52
FLB
0.022µ
SL_O 16
SL_M 15
2200p
10µ
50 TDFCT
51 VC
FEI
10µ
FEO
0.022µ
VCC
26
41 F
100k
0.01µ
38
SL_P 14
100k
0.033µ
510k
Vcc
3.3µ
13
82k
100k
39
PD2
D
F
0.033µ
0.033µ
22k 0.01µ
0.01µ
1M
500
40
MICRO
COMPUTER
DSP
1µ
100
B
22µ 15k
0.015µ
DRIVER
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXA1992AR
Description of Functions
RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58kΩ
equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the
photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check
can be performed at this pin.
1k
22k
3.3µ
RF_O
RF_M
34
A
33
58k
C
PD1
iPD1→
VA
38
10k
PD1 IV AMP
B
VC
RF SUMMING AMP
58k
VC
D
PD2
iPD2→
VB
39
10k
PD2 IV AMP
VC
The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2).
– 16 –
CXA1992AR
Focus Error Amplifier
R3
58k
R7
174k
R5
32k
VB
PD2 39
1
B+D
FEO
PD2 IV AMP
R10
10k
FE AMP
R2
58k
VC
2
R4
32k
VA
PD1 38
R9
10k
A+C
PD1 IV AMP
R6
174k
VC
VCC
×1 ×2
7
×8 ×16 ×32
EF_BIAS 40
FOCUS
PHASE
COMPENSATION
IFB5
GND
FE_M
R11
100k
R8
100k
6
FE_O
DRIVER
IFB6
IFB3
IFB4
IFB2
VC
IFB1
C1
2200p
GND
R1
4k
×4
FEI
VIN > VH L
VIN < VH H
25mV/STEP
VH
RESET : IFB1 to IFB6 ON
VC
FOH
25 SENS1
VEE
20mV
SENS
SELECTOR
VIN
VC
FOL
26 SENS2
VL
VIN > VL H
VIN < VL L
–20mV
VC
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C – B – D).
The FEO output voltage:
VFEO =
=
174kΩ
(VA – VB)
32kΩ
174kΩ
{(–58kΩ × iPD1) – (–58kΩ × iPD2)}
32kΩ
= 315.4kΩ (iPD2 – iPD1)
The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment.
The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and
OFF.
The 6-bit focus bias adjustment switches are controlled with commands.
IFB1 to IFB6 are all ON after a reset.
The voltage is varied by approximately 25mV per step.
– 17 –
CXA1992AR
• Focus error amplifier offset adjustment (when adjusting the IC offset)
The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference
level.
The FEO and reference level are compared by the window comparator, and the comparison results are output
from SENS1 and SENS2. (ADDRESS D11001110D6)
Adjust the offset so that SENS1 and SENS2 are both High.
Set the reference level to the center ±20mV.
25mV
<
40mV
<
50mV
Reference level width
Variable voltage per step Variable voltage per 2 steps
• Focus bias fine adjustment
Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while
monitoring a DSP jitter meter with the microcomputer.
The 6-bit focus bias adjustment switches are controlled with commands.
• When performing conventional focus bias adjustment
Fix the focus bias adjustment switches to the desired settings. (for example, IFB6 ON)
In this condition, adjust the focus bias by turning a volume connected to FE_BIAS (Pin 40).
[Example circuit]
VCC
40 FE_BIAS
Volume 47k
3.9k
VEE
– 18 –
CXA1992AR
Tracking Error Amplifier
R23
100k
R24
150k
C3
0.01µ
C4
0.01µ
GND
TEO
GND
R5
13k
R16
NORMAL 96k
R14
13k
TGFL
R9
R3
26k
R1
260k
R4
6.8k
TGFL
NORMAL
R12
96k
C1
12p
E 42
R13
13k
V
VL
–
+
R22
1.5k
VC
TOG4
R8
17k
TOG1
VC
F I-V AMP
SENS1
BALL
R18
7.5k
GAIN UP
GAIN UP
TOG3
VF
25
VIN
17k
VC
F 41
BALH
20mV
VC
TOG2
C2
12p
VIN > VH L
VIN < VH H
VH
TE AMP
R17
10k
R19
16k
R20
7.5k
R21
3.3k
R2
260k
LPFI
46
45
VIN > VL H
–20mV VIN < VL L SENS
VIN > VH L SELECTOR
VIN < VH H
VH
TGH
400mV
VC
VC
SENS2
26
VIN
CPU
TGL
VE
VC
R6
75k
R7
BAL1 110k
R10
BAL2 56k
R11
BAL3 27k
R15
BAL4 13k
VC
E I-V AMP
VL
300mV
RE
VIN > VL H
VIN < VL L
VC
23
COMAND
COMAND
CONTROL
CONTROL
VC
22
21
20
XRST
DATA
XLT
CLK
43
EI
The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO.
The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at the E I-V amplifier.
E I-V AMP feedback resistance = R1 + R4 + R1 × R4
RE
F I-V AMP feedback resistance = R2 + R5 + R2 × R5 = 403kΩ
R3
Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance
adjustment switches (BAL1 to BAL4).
The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches
(TOG1 to TOG4).
The balance and gain adjustment switches are controlled with commands.
Set the cut-off frequency of the external LPF between 10Hz to 100Hz.
– 19 –
CXA1992AR
• Balance adjustment
The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external
LPF, extracting the offset DC, and comparing it to the reference level.
However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete offset DC can not be extracted.
To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency
that can lower a sufficient gain appears on the LPF.
Use the C.OUT output to check this frequency.
The offset DC and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6)
Adjust the balance so that the SENS1 and SENS2 pins are both High.
VIN < VL < VH
VL < VIN < VH
VL < VH < VIN
H
H
L
L
H
H
SENS1 pin
BALH
SENS2 pin
BALL
VH: High level threshold value
VIN: Window comparator input signal
VL: Low level threshold value
• Gain adjustment
Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component
to the reference level.
The AC component is generated by taking the difference between TE and the offset DC input to Pin 46.
The AC component and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6)
The comparison signal is as follows.
(1)
(2)
(3)
VH
VL
VIN
SENS1 pin
TGH
SENS2 pin
TGL
H
H
L
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).
When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the
TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL
(SENS2 pin).
– 20 –
CXA1992AR
APC & Laser Power Control
VCC
C2
100µ
R1
22
LD
R6
1k
VCC
LDON
L1
10µH
R10
56k
130mV
PD
C1
1µ
36
R2
500
LD PD
R8
10k
37
R3
100
R4
10k
R5
55k
R12
56k
R11
10k
VREF
VEE
GND
VEE
RF_I
VL
VEE
32
C3
0.01µ
LPC ON/OFF
R14
12.5k
1.1Vpp
R7
1.47V 39.5k
RF_O
50%/17%
670mV
33
RF
R9
23.5k
VC
VC
RFTC
35
R13
1M
C4
1µ
VEE VEE
• APC
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics.
The APC circuit is used to maintain the optical power output at a constant level.
The laser diode current is controlled according to the monitor photo diode output.
• Laser power control
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR.
This signal is then compared with the reference level.
The laser power is controlled by attaching an offset to VL according to the results of comparison with the
reference level.
Set the reference level to 670mV. (center voltage reference)
LPC ON/OFF and LD ON/OFF control is performed with commands.
The laser power control limit can also be switched between ±50% and ±17% with commands.
LPC
LPCL
VL variable range
OFF
—
ON
±50%
Approximately 1.27V ± 625mV
ON
±17%
Approximately 1.27V ± 208mV
Approximately 1.27V
– 21 –
CXA1992AR
Center Voltage Generation Circuit
(The figure below shows a single voltage application; Connect to GND for dual power supplies.)
Maximum current is approximately ±3mA. Output impedance is approximately 50Ω.
VCC
VCC
30k
VC
50
VC
51
30k
VEE
GND
Connected internally to the VEE pin.
– 22 –
CXA1992AR
Focus Servo
9k
0.022µ
FZC
52
51k
FZC
FEO
SENS
SELECTOR
1
FE
10k
25 SENS1
75k
2
FEI
100k
10k
2200p
DFCT
FS4
68k
FDFCT
0.1µ
FOCUS COIL
FE_O
Focus
100k
phase
Compensation
FS3
3
6
FGD
4
50k
100k
FE_M
7
680k
40k
11µ
22µ
0.1µ
ISET
60k
17
50k
FS2
FLB
5
0.1µ
FSET
11
510k
8
SRCH
FS1
Charge
up
0.015µ
4.7µ
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 5 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 11.
The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of Vcc and VC (Pin 51); (Vcc – VC) × 15%.
∗ 510kΩ resistance is recommended for Pin 11.
– 23 –
CXA1992AR
Tracking and Sled Servo
+
45
TEO
100k
BUFFER AMP
150k
0.01µ
46
0.01µ
–
LPFI
TGH
GAIN
TGL
WINDOW
COMPARATOR
26 SENS2
SENS
SELECTOR
BALH
BALANCE
WINDOW
COMPARATOR BALL
25 SENS1
47k
SLED ON/OFF
CONTROL
19 LOCK
SLED MOTOR
SL_O
16
DFCT
TM1
47
680k
SL_M
15
100k
100k
TDFCT
50
TM6 22µA
0.1µ
8.2k
1k
ATSC
470p
66p
TM5
0.047µ 47k
330k
680k
1k
22µA
TM4 11µA
49
10
TA_M
12
TM3
TZC
0.033µ
14
ATSC
100k
TZC
9
SL_P
TM2
3.3µ
48
0.022µ
20k
TGU
TG2
M
TG1
120k
TEI
0.015µ
TE
TG2
Tracking Phase
Compensation
10k
82k
22µ
100k
15k
11µA
TRACKING
COIL
90k
TA_O
13
TM7
470k
FSET
11
510k
0.015µ
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance is connected to Pin 11. In the CXA1992AR, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 (or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and VEE.
When this resistance is 60kΩ :
TM3 (or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 50.
– 24 –
CXA1992AR
The ISET pin is used to connect external resistance. This external resistance sets the current which
determines the focus search, track jump, and sled kick heights.
• Focus search current
I1 =
I1
VBG
×
R
1
2
I2
(VBG: approximately 1.27V)
I2 = 2I1
FS1
• Track jump current (TM3 and TM4 current)
I=
VBG
×
R
1
2
• Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands)
I=
VBG
R
Use external resistance of between 30kΩ to 240kΩ.
Using external resistance outside this range may cause oscillation.
– 25 –
CXA1992AR
Focus OK Circuit
RF
VCC
RF_O
20k
33
C5
0.01µ
×1
RF_I
54k
27 FOK
VG
32
15k
92k
0.63V
FOCUS OK AMP
FOCUS OK
COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 32 from Pin 33 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output is inverted when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK
amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate
degradation brought about by RF envelope defects caused by scratched discs can be prevented.
Defect Circuit
After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant
bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the
pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and
comparing both signals, the mirror defect detection signal is generated.
0.033µ
CC1
29
CC2
28
DFCT2
FLIP
FLOP
RF_O 33
a
×2
b
c
26 SENS2
e SENS
SELECTOR
d DFCT1
DEFECT SW
DEFECT AMP
CB
DEFECT BOTTOM
HOLD
30
DEFECT COMPARATOR
0.01µ
a
RFO
b
DEFECT
AMP
c
BOTTOM
HOLD (1)
solid line
CC1
e
DFCT1
d
H
L
– 26 –
BOTTOM
HOLD (2)
dotted line
CC2
25 SENS1
CXA1992AR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
RF_O
33
MIRROR HOLD AMP
RF
0.033µ
32
RF_I
× 1.4
G
PEAK &
BOTTOM
HOLD
31
CP
H
×1
I
MIRROR AMP
J
K
MIRR
SENS
SELECTOR
26 SENS2
MIRROR
COMPARATOR
RF_O
0V
G
(RF_I)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
H
MIRR
L
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1992AR, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP with MIRR input pin, input the C.OUT output to the MIRR input of
the DSP.
– 27 –
CXA1992AR
SENS Selector
FZC
HIGH-Z
DFCT1
DFCT2
TZC
MIRR
BALH
BALL
25 SENS1
26 SENS2
TGH
TGL
FOH
FOL
ATSC
What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin.
DATA (Pin 22) 8-bit transfer
ADDRESS
DATA
SENS1
SENS2
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
X
X
X
X
FZC
H
(HIGH-Z)
0
0
0
1
X
X
X
X
DFCT1
DFCT2
0
0
1
0
X
X
X
X
TZC
MIRR
0
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
H
(HIGH-Z)
H
(HIGH-Z)
DATA (Pin 22) 12-bit transfer
ADDRESS
D11 D10
DATA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SENS1
SENS2
0
0
1
1
0
0
X
X
X
X
X
X
BALH
BALL
0
0
1
1
0
1
X
X
X
X
X
X
TGH
TGL
0
0
1
1
1
0
X
X
X
X
X
X
FOH
FOL
0
0
1
1
1
1
X
X
X
X
X
X
ATSC
H
(HIGH-Z)
Notes)
• 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and
SENS2 are switched according to the D3 and D2 data.
• SENS1 and SENS2 are switched without latching.
– 28 –
CXA1992AR
Commands
The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is
represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0
and F/$XXX for 12-bit.
Commands for the CXA1992AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X,
$3XX.
1. $0X (FZC at SENS1 pin (Pin 25), H (Hi-Z) at SENS2 pin (Pin 26))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
0
D6
0
D5
0
D4
0
D3
FS4
D2
—
D1
FS2
D0
FS1
Four focus related switches exist: FS1, FS2, FS4 and DFCT.
$00
$02
When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.
(22µA – 11µA) × 50kΩ ×
$03
resistance between Pins 6 and 7
.... Equation 1
50kΩ
The SRCH DOWN speed can be increased by the charge up circuit.
From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 8 when FS1 goes from 0 → 1
This time constant is obtained with the 50kΩ resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
– 29 –
CXA1992AR
1-1. FS4
This switch is provided between the focus error input and the focus phase compensation, and is in charge of
turning the focus servo ON and OFF.
$00
→ $08
Focus off
Focus on
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
A
t
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig.
3. To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 25) as the point A transit signal.
In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00)
$03
$08
Drive voltage
∗ The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
Focus error
SENS1
(FZC)
The instant when the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart
– 30 –
CXA1992AR
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
Transfer $08
NO
YES
F. OK ?
F. OK ?
NO
NO
YES
YES
Transfer $08
FZC ↓ ?
NO
YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
2. $1X (DFCT1 at SENS1 pin (Pin 25), DFCT2 at SENS2 pin (Pin 26))
These commands deal with switching TG1/TG2, brake circuit ON/OFF,
and the sled kick output.
The bit configuration is as follows:
0
D6
0
D5
0
D4
1
D3
D2
TG1, TG2 Break
circuit
ON/OFF ON/OFF
D1
D0
Sled kick
height
D1
(PS1)
D0
(PS0)
Relative
value
D7
Sled kick height
0
0
0
1
±1
±2
1
1
0
1
±3
±4
TG1, TG2, TM7
The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track
jump has been performed actually though a 100-track jump was intended to be done due to the extremely
degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump.
For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to
the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between
the RF envelope and the tracking error is 180° out-of-phase to cut the unneeded portion of the tracking error
and apply braking.
– 31 –
CXA1992AR
[∗B]
[∗A]
Envelope
Detection
RF_I 32
(MIRR)
[∗C]
[∗E]
[∗D]
Waveform
Shaping
TZC 49
D2
Waveform
Shaping
[∗F]
[∗G]
D Q
BRK
TM7
Low: open
High: make
CK
[∗H]
Edge Detection
(Latch)
CXA1992
Fig. 6. TM7 movement during braking operation
From inner to outer track
From outer to inner track
[∗A]
[∗B]
[∗C]
("MIRR")
[∗D]
("TZC")
[∗E]
[∗F]
[∗G]
[∗H]
Braking is applied
from here.
0V
Fig. 7. Internal waveform
3. $2X (TZC at SENS1 pin (Pin 25), MIRR at SENS2 pin (Pin 26))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
0
D6
D5
D4
0
1
0
D3
D2
Tracking
control
00
off
01
Servo ON
10
F-JUMP
11
R-JUMP
↓
TM1, TM3, TM4,
– 32 –
D1
D0
Sled
control
00
off
01
Servo ON
10
F-FAST FORWARD
11
R-FAST FORWARD
↓
TM2, TM5, TM6
CXA1992AR
4. $3XX
These commands mainly control the balance and gain control circuit switches used during automatic tracking
adjustment and the bias circuit switch used during automatic focus bias adjustment.
In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to 6
switches are ON.
• Balance adjustment
The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches
are set using D0 to D3.
At this time, SENS1 outputs BALH and SENS2 outputs BALL.
Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0.
Sending a latch pulse with D6, D7 ≈ 0 does not change the balance switch settings.
START
C.OUT
is the frequency high
enough ?
BAL1 to BAL4
Switch Control
NO
YES
SENS1/2
Balance OK ?
Adjustment Completed
Balance adjustment
• Gain adjustment
The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches
are set using D0 to D3.
At this time, SENS1 outputs TGH and SENS2 outputs TGL.
In a fashion similar to the method used with the balance adjustment, set the data by specifying switch
conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.
START
TOG1 to TOG4
Switch control
SENS1/2
GAIN OK ?
NO
YES
Adjustment Completed
Gain adjustment
– 33 –
CXA1992AR
• Focus bias adjustment
The focus bias adjustment switches IFB1 to 6 can be controlled by setting D6 = 0 and D7 = 1. The switches
are set using D0 to D5.
At this time, SENS1 outputs FOH and SENS2 outputs FOL.
Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.
START
IFB1 to 6
Switch Control
NO
SENS1/2
BIAS OK ?
YES
Adjustment Completed
Focus bias adjustment method
• TGFL
The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0.
The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0.
The TEO signal level can be made higher by approximately 6dB for GAIN UP.
When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the
gain should be raised with the TGFL command for adjustment.
• LPC
The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1.
The circuit is ON with D0 = 1 and OFF with D0 = 0.
• LPCL
The laser power control limit can be switched between ±17% and ±50% by setting D1 with D6 = 1 and D7 = 1.
The control limit is ±17% with D1 = 0 and ±50% with D1 = 1.
• LDON
The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1.
The laser diode is ON with D2 = 1 and OFF with D2 = 0.
– 34 –
CXA1992AR
• ATSC
The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1.
This function is disabled with D3 = 1 and enabled with D3 = 0.
At this time, SENS1 outputs ATSC.
Even if ATSC is disabled, ATSC is output to SENS1.
When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode.
(In the Block Diagram, TG1 is set to the
side and TG2 is OFF. Even if TG1 and TG2 are NORMAL mode,
they switch to GAIN UP mode in conjunction with ATSC.)
When the anti-shock function is not used, Pin 48 (ATSC) should be connected to VC.
• RDFCT2
DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1.
DFCT2 is reset with D4 = 1.
After a reset, High is held when DFCT1 rises.
During $1X commands, DFCT2 is output from SENS2.
DFCT2 operates even if DFCT is disabled.
Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed.
• INT
The interruption (scratched disc) countermeasure circuit can be set to operating status by setting D5 with D6
= 1 and D7 = 1.
This circuit is enabled when D5 = 1 and disabled when D5 = 0.
Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise.
When MIRR rises, the DFCT switch is routed through the low-pass filter.
The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking
gain is increased. (including when the gain is increased by ATSC or LOCK)
Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.
Parallel direct interface
• LOCK (Sled overrun prevention circuit)
This circuit operates when LOCK is low.
When LOCK is low, the sled is OFF, and TG1 and TG2 are UP (TRACKING GAIN UP).
LOCK
SLED
TM2 SW:
SLED ON
side
TM2 SW:
side
SLED OFF
UP
TG1 SW:
TG2 OFF
TRACKING GAIN
NORMAL
TG1 SW:
TG2 ON
side
side
When LOCK is not used, Pin 19 (LOCK) should be pulled up to VCC with the resistor of approximately 47kΩ.
– 35 –
CXA1992AR
CPU Serial Interface Timing Chart
DATA
D0
D1
tWCK
D2
D3
tWCK
tSU
D4
D5
D6
D7
D0
th
CLK
tCD
1/fck
tD
XLT
tWL
(VCC = 3.0V)
Item
Symbol
Min.
Typ.
Max.
Unit
1
MHz
Clock frequency
fck
Clock pulse width
fwck
500
ns
Setup time
500
ns
500
ns
500
ns
1000
ns
Data transfer interval
tsu
th
tD
tWL
tCD
1000
ns
Low level input voltage
VIL
0.0
(VCC – VEE) × 0.1
V
High level input voltage
VIH
(VCC – VEE) × 0.9
VCC
V
Hold time
Delay time
Latch pulse width
– 36 –
0
0
TRACKING
CONTROL
TRACKING
SLED MODE
– 37 –
ON
FWD MOVE
REV MOVE
1
0
1
0
1
1
ON
FWD JUMP
REV JUMP
1
1
0
0
OFF
0
1
0
1
0
D0
D1
SLED MODE ∗2
SLED
KICK + 2
FS2
SRCH ON
1 = ON
0 = OFF
DATA
1 = ENABLE
0 = DISABLE
0
∗2 SLED MODE
—
D2
BRAKE
TRACKING MODE ∗1
1 = GAIN UP
0 = NORMAL
TG1, TG2
FS4
Focus
1 = ON
0 = OFF
D3
OFF
0
1
0
D4
D1
1
0
0
D5
D2
0
0
0
D6
ADDRESS
DATA (Pin 22) 8-bit transfer
D3
∗1 TRACKING MODE
0
D7
FOCUS
CONTROL
Item
System Control
SLED
KICK + 1
FS2
SRCH UP
1 = UP
0 = DOWN
D0
TZC
DFCT1
FZC
SENS1
MIRR
DFCT2
H
(HIGH-Z)
SENS2
CXA1992AR
0
FOCUS
BIAS
– 38 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
D6
RDFCT2
INT
ATSC
1 = OFF
0 = ON
IFB4
1 = OFF
0 = ON
TOG4
1 = OFF
0 = ON
BAL4
D3
LDON
1 = OFF
0 = ON
IFB3
1 = OFF
0 = ON
TOG3
1 = OFF
0 = ON
BAL3
D2
1 = ENABLE 1 = RESET
1 = DISABLE 1 = ON
0 = DISABLE 0 = NORMAL 0 = ENABLE 0 = OFF
1 = OFF
0 = ON
IFB5
—
—
D4
1 = OFF
0 = ON
IFB6
1 = GAIN UP
0 = NORMAL
TGFL
1 = DISABLE
0 = ENABLE
DFCT
D5
DATA
1 = ON
0 = OFF
LPC
LPCL
1 = ±50%
0 = ±17%
1 = OFF
0 = ON
IFB1
IFB2
1 = OFF
0 = ON
1 = OFF
0 = ON
TOG1
TOG2
1 = OFF
0 = ON
1 = OFF
0 = ON
BAL1
D0
1 = OFF
0 = ON
BAL2
D1
ATSC
FOH
TGH
BALH
SENS1
Notes)
• When ATSC is enabled, even if TG1 and TG2 are NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC and LOCK.
• INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC or LOCK)
When reset
• SENS1 = FZC
• SENS2 = High (Hi-Z)
• RDFCT2 = 1 (Reset)
• IFB1 to IFB6 = 0 (switch ON)
• TOG1 to TOG4 = 0 (switch ON)
• BAL1 to BAL4 = 1 (switch ON)
• Other data is "0".
0
0
TRACKING
GAIN
Others
0
D8 D7
ADDRESS
D11 D10 D9
E-F
BALANCE
Item
DATA (Pin 22) 12-bit transfer
H
(HIGH-Z)
FOL
TGL
BALL
SENS2
CXA1992AR
CXA1992AR
Serial Data Truth Table
Serial Data
HEX
FOCUS CONTROL
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
Functions
FS2 FS1
FS4
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes) • FS1
1: OFF
0: ON
• FS2
1: ON
0: OFF
• FS4
In the Block Diagram:
1:SW
side
0:SW
side
BRAK SLD KICK
TG1 Fig. 6 KICK KICK
TG2 D2
+2
+1
TRACKING CONTROL
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
0001 1111
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Notes) • TG1
In the Block Diagram:
1:SW
side
0:SW
side
• TG2
1: OFF
0: ON
• BRAKE
When D2 in Fig. 6 is:
1: 1
0: 0
• Sled kick height
– 39 –
D1
D0
0
0
1
1
0
1
0
1
Relative value
±1
±2
±3
±4
CXA1992AR
Serial Data
HEX
TM6 TM5 TM4 TM3 TM2 TM1
TRACKING/SLED MODE
0010 0000
0010 0001
0010 0010
0010 0011
0010 0100
0010 0101
0010 0110
0010 0111
0010 1000
0010 1001
0010 1010
0010 1011
0010 1100
0010 1101
0010 1110
0010 1111
Function
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
– 40 –
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Notes) • TM1/TM2
In the Block Diagram:
1:SW
side
0:SW
side
• TM3/TM4/TM5/TM6
1: ON
0: OFF
CXA1992AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0000 0000
0011 0000 0001
0011 0000 0010
0011 0000 0011
0011 0000 0100
0011 0000 0101
0011 0000 0110
0011 0000 0111
0011 0000 1000
0011 0000 1001
0011 0000 1010
0011 0000 1011
0011 0000 1100
0011 0000 1101
0011 0000 1110
0011 0000 1111
$300
$301
$302
$303
$304
$305
$306
$307
$308
$309
$30A
$30B
$30C
$30D
$30E
$30F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
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————
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————
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—
—
—
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—
—
—
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—
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—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
0011 0001 0000
0011 0001 0001
0011 0001 0010
0011 0001 0011
0011 0001 0100
0011 0001 0101
0011 0001 0110
0011 0001 0111
0011 0001 1000
0011 0001 1001
0011 0001 1010
0011 0001 1011
0011 0001 1100
0011 0001 1101
0011 0001 1110
0011 0001 1111
$310
$311
$312
$313
$314
$315
$316
$317
$318
$319
$31A
$31B
$31C
$31D
$31E
$31F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
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—
—
—
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—
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—
—
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—
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
0011 0010 0000
0011 0010 0001
0011 0010 0010
0011 0010 0011
0011 0010 0100
0011 0010 0101
0011 0010 0110
0011 0010 0111
0011 0010 1000
0011 0010 1001
0011 0010 1010
0011 0010 1011
0011 0010 1100
0011 0010 1101
0011 0010 1110
0011 0010 1111
$320
$321
$322
$323
$324
$325
$326
$327
$328
$329
$32A
$32B
$32C
$32D
$32E
$32F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
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——————
——————
——————
——————
——————
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——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 41 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA1992AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0011 0000
0011 0011 0001
0011 0011 0010
0011 0011 0011
0011 0011 0100
0011 0011 0101
0011 0011 0110
0011 0011 0111
0011 0011 1000
0011 0011 1001
0011 0011 1010
0011 0011 1011
0011 0011 1100
0011 0011 1101
0011 0011 1110
0011 0011 1111
$330
$331
$332
$333
$334
$335
$336
$337
$338
$339
$33A
$33B
$33C
$33D
$33E
$33F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0011 0100 0000
0011 0100 0001
0011 0100 0010
0011 0100 0011
0011 0100 0100
0011 0100 0101
0011 0100 0110
0011 0100 0111
0011 0100 1000
0011 0100 1001
0011 0100 1010
0011 0100 1011
0011 0100 1100
0011 0100 1101
0011 0100 1110
0011 0100 1111
$340
$341
$342
$343
$344
$345
$346
$347
$348
$349
$34A
$34B
$34C
$34D
$34E
$34F
0011 0101 0000
0011 0101 0001
0011 0101 0010
0011 0101 0011
0011 0101 0100
0011 0101 0101
0011 0101 0110
0011 0101 0111
0011 0101 1000
0011 0101 1001
0011 0101 1010
0011 0101 1011
0011 0101 1100
0011 0101 1101
0011 0101 1110
0011 0101 1111
$350
$351
$352
$353
$354
$355
$356
$357
$358
$359
$35A
$35B
$35C
$35D
$35E
$35F
4 3 2 1 4 3 2 1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TGFL
IFB SW
6 5 4 3 2 1
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
——————
——————
——————
——————
——————
——————
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——————
——————
——————
——————
——————
——————
——————
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
– 42 –
CXA1992AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 0110 0000
0011 0110 0001
0011 0110 0010
0011 0110 0011
0011 0110 0100
0011 0110 0101
0011 0110 0110
0011 0110 0111
0011 0110 1000
0011 0110 1001
0011 0110 1010
0011 0110 1011
0011 0110 1100
0011 0110 1101
0011 0110 1110
0011 0110 1111
$360
$361
$362
$363
$364
$365
$366
$367
$368
$369
$36A
$36B
$36C
$36D
$36E
$36F
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 0111 0000
0011 0111 0001
0011 0111 0010
0011 0111 0011
0011 0111 0100
0011 0111 0101
0011 0111 0110
0011 0111 0111
0011 0111 1000
0011 0111 1001
0011 0111 1010
0011 0111 1011
0011 0111 1100
0011 0111 1101
0011 0111 1110
0011 0111 1111
$370
$371
$372
$373
$374
$375
$376
$377
$378
$379
$37A
$37B
$37C
$37D
$37E
$37F
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
————
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1000 0000
0011 1000 0001
0011 1000 0010
0011 1000 0011
0011 1000 0100
0011 1000 0101
0011 1000 0110
0011 1000 0111
0011 1000 1000
0011 1000 1001
0011 1000 1010
0011 1000 1011
0011 1000 1100
0011 1000 1101
0011 1000 1110
0011 1000 1111
$380
$381
$382
$383
$384
$385
$386
$387
$388
$389
$38A
$38B
$38C
$38D
$38E
$38F
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
– 43 –
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA1992AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 1001 0000
0011 1001 0001
0011 1001 0010
0011 1001 0011
0011 1001 0100
0011 1001 0101
0011 1001 0110
0011 1001 0111
0011 1001 1000
0011 1001 1001
0011 1001 1010
0011 1001 1011
0011 1001 1100
0011 1001 1101
0011 1001 1110
0011 1001 1111
$390
$391
$392
$393
$394
$395
$396
$397
$398
$399
$39A
$39B
$39C
$39D
$39E
$39F
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1010 0000
0011 1010 0001
0011 1010 0010
0011 1010 0011
0011 1010 0100
0011 1010 0101
0011 1010 0110
0011 1010 0111
0011 1010 1000
0011 1010 1001
0011 1010 1010
0011 1010 1011
0011 1010 1100
0011 1010 1101
0011 1010 1110
0011 1010 1111
$3A0
$3A1
$3A2
$3A3
$3A4
$3A5
$3A6
$3A7
$3A8
$3A9
$3AA
$3AB
$3AC
$3AD
$3AE
$3AF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1011 0000
0011 1011 0001
0011 1011 0010
0011 1011 0011
0011 1011 0100
0011 1011 0101
0011 1011 0110
0011 1011 0111
0011 1011 1000
0011 1011 1001
0011 1011 1010
0011 1011 1011
0011 1011 1100
0011 1011 1101
0011 1011 1110
0011 1011 1111
$3B0
$3B1
$3B2
$3B3
$3B4
$3B5
$3B6
$3B7
$3B8
$3B9
$3BA
$3BB
$3BC
$3BD
$3BE
$3BF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 44 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA1992AR
Serial Data
$3XX
HEX
BAL SW TOG SW
0011 1100 0000
0011 1100 0001
0011 1100 0010
0011 1100 0011
0011 1100 0100
0011 1100 0101
0011 1100 0110
0011 1100 0111
0011 1100 1000
0011 1100 1001
0011 1100 1010
0011 1100 1011
0011 1100 1100
0011 1100 1101
0011 1100 1110
0011 1100 1111
$3C0
$3C1
$3C2
$3C3
$3C4
$3C5
$3C6
$3C7
$3C8
$3C9
$3CA
$3CB
$3CC
$3CD
$3CE
$3CF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1101 0000
0011 1101 0001
0011 1101 0010
0011 1101 0011
0011 1101 0100
0011 1101 0101
0011 1101 0110
0011 1101 0111
0011 1101 1000
0011 1101 1001
0011 1101 1010
0011 1101 1011
0011 1101 1100
0011 1101 1101
0011 1101 1110
0011 1101 1111
$3D0
$3D1
$3D2
$3D3
$3D4
$3D5
$3D6
$3D7
$3D8
$3D9
$3DA
$3DB
$3DC
$3DD
$3DE
$3DF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0011 1110 0000
0011 1110 0001
0011 1110 0010
0011 1110 0011
0011 1110 0100
0011 1110 0101
0011 1110 0110
0011 1110 0111
0011 1110 1000
0011 1110 1001
0011 1110 1010
0011 1110 1011
0011 1110 1100
0011 1110 1101
0011 1110 1110
0011 1110 1111
$3E0
$3E1
$3E2
$3E3
$3E4
$3E5
$3E6
$3E7
$3E8
$3E9
$3EA
$3EB
$3EC
$3ED
$3EE
$3EF
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4 3 2 1 4 3 2 1
TGFL
IFB SW
6 5 4 3 2 1
– 45 –
INT
RDF
ATSC LDON LPCL LPC DFCT
CT2
CXA1992AR
Serial Data
$3XX
HEX
0011 1111 0000
0011 1111 0001
0011 1111 0010
0011 1111 0011
0011 1111 0100
0011 1111 0101
0011 1111 0110
0011 1111 0111
0011 1111 1000
0011 1111 1001
0011 1111 1010
0011 1111 1011
0011 1111 1100
0011 1111 1101
0011 1111 1110
0011 1111 1111
$3F0
$3F1
$3F2
$3F3
$3F4
$3F5
$3F6
$3F7
$3F8
$3F9
$3FA
$3FB
$3FC
$3FD
$3FE
$3FF
BAL SW TOG SW
4 3 2 1 4 3 2 1
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
— — — —— — — —
TGFL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IFB SW
6 5 4 3 2 1
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
——————
INT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RDF
ATSC LDON LPCL LPC DFCT
CT2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E
E
E
E
E
E
E
E
D
D
D
D
D
D
D
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Notes) • 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values
of each bit for serial data.
• "—" in the Truth Table indicates that the status does not change.
• TGFL
In the Block Diagram:
1:SW
side
0:SW
side
• ATSC E: enable/D: disable
• DFCT E: enable/D: disable
– 46 –
CXA1992AR
Initial State (resetting state)
ADDRESS
Item
DATA
D7 D6 D5 D4 D3 D2 D1 D0
HEX
FOCUS CONTROL
0
0
0
0
0
0
0
0
$00
TRACKING CONTROL
0
0
0
1
0
0
0
0
$10
TRACKING SLED MODE
0
0
1
0
0
0
0
0
$20
Item
ADDRESS
DATA
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HEX
E-F BALANCE
0
0
1
1
0
0
0
0
0
0
0
0
$300
TRACKING GAIN
0
0
1
1
0
1
0
0
0
0
0
0
$340
FOCUS BIAS
0
0
1
1
1
0
0
0
0
0
0
0
$380
Others
0
0
1
1
1
1
0
1
0
0
0
0
$3D0
The above data means the following operation modes.
FOCUS CONTROL
TRACKING CONTROL
TRACKING SLED MODE
E-F BALANCE
TRACKING GAIN
FOCUS BIAS
Others
: FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN
: TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative height value ±1
: TRACKING OFF, SLED OFF
: BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE
: TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL
: IFB1 to IFB6 = 0 (switch ON)
: INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL ±17%, LPC OFF
– 47 –
CXA1992AR
Notes on Operation
1. Focus OK circuit
1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.
VCC
20k
FOK
27
40k
The FOK and comparator output are as follows:
Output voltage High : VFOKH ≈ near Vcc
Output voltage Low : VFOKL ≈ Vsat (NPN) + VEE
RL
100k
VCC
VEE
VEE
2. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
3. Focus/Tracking internal phase compensation and reference design material
TRK
FCS
Item
SD
1.2kHz gain
08
1.2kHz phase
08
1.2kHz gain
25
1.2kHz phase
25
2.7kHz gain
25 → 13
2.7kHz phase
25 → 13
Measurement pin
6
13
Conditions
Typ.
Unit
CFLB = 0.1µF
CFGD = 0.1µF
21.5
dB
63
deg
13
dB
–125
deg
26.5
dB
–130
deg
CTGU = 0.1µF
4. Laser Poser Control
The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The laser life is shortened by increasing the laser power when the less light is reflected from the disc.
It is recommended that the typical laser power value is set lower to maintain the laser life.
Take care of the laser maximum ratings when using the laser power control circuit.
– 48 –
CXA1992AR
Package Outline
Unit: mm
52PIN LQFP(PLASTIC)
+ 0.1
1.5 0
12.0 ± 0.2
∗ 10.0 ± 0.1
0.1
39
27
26
40
B
A
52
14
13
1
0.65
+ 0.08
0.32 – 0.07
0.13 M
0° to 10°
(0.3)
(0.125)
+ 0.04
0.145 – 0.025
+ 0.08
0.32 – 0.07
(0.5)
(11.0)
0.1 ± 0.1
0.6 ± 0.15
0.25
DETAIL A
DETAIL B
NOTE: “∗” Dimensions do not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-52P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
LQFP052-P-1010
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.3g
JEDEC CODE
– 49 –