SONY CXA3512R

CXA3512R
LCD Driver
For the availability of this product, please contact the sales office.
Description
The CXA3512R is a driver IC for the analog inputs
of SVGA or higher Sony polycrystalline silicon TFT
LCD panels. It has a line invert amplifier and analog
demultiplexers, as well as the timing generator and
output buffers required for these. The CXA3512R
can directly drive an LCD panel. The VCOM setting
circuit and precharge pulse waveform generator are
also on-chip.
64 pin LQFP (Plastic)
Features
• High-speed signal processing supports XGA high refresh signal
• Overall wide band response
• Low output deviation by on-chip output offset cancel circuit
• Invert amplifier with small phase delay difference between inverted signal and non-inverted signal
• On-chip timing generator with ECL
• Dot clock phase adjustment function
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Absolute Maximum Ratings
• Supply voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation
Vcc
VDD
PD
16
5.5
–20 to +70
–65 to +150
2300
Recommended Operating Conditions
• Supply voltage
Vcc
15.0 to 15.5
VDD
4.75 to 5.25
• Ambient temperature
–20 to +70
V
V
°C
°C
mW (single layered board mounted)
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99803A9Z-PS
CXA3512R
NC
VIDEO_I
VIDEO_R
VIDEO_O
SH_IN
NC
VCC
GND
GND
SID_IN
SID_R
SID_O
FRP
SIGCNT
VCOMOFF
VCOMOUT
Block Diagram
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CAL_R 49
SID
INVERT
AMP
32 SHOUT1
CAL_O 50
CAL_I 51
31 NC
CALIBRATION
AMP
VCOM
VDD 52
S/H
S/H
DGND 53
S/H
29 NC
BUFFER
28 SHOUT3
OFFSET CANCEL
MCLK 54
S/H
S/H
MCLKX 55
GND 56
CLOCK
DELAY
GND 57
S/H
27 NC
BUFFER
26 PVCC
OFFSET CANCEL
D
S/H
S/H
S/H
25 GND
BUFFER
24 GND
OFFSET CANCEL
DLYCTR 58
S/H
S/H
S/H
pulses
CLKOUT 59
CLKOUTX 60
NC 61
S/H
S/H
S/H
offset
cancel
mode
timing
22 NC
S/H
21 SHOUT4
BUFFER
20 NC
S/H
S/H
19 SHOUT5
BUFFER
18 NC
OFFSET CANCEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PRG
NC
NC
POSCTR1
POSCTR2
NC
GND
GND
STATUS
ENB
NC
D1OR2
DIRCTR
NC
DCFBSW
17 SHOUT6
PRGPOL
F/H_CNT 64
23 PGND
BUFFER
OFFSET CANCEL
CLKIN 62
CLKINX 63
S/H
OFFSET CANCEL
TIMING
GENERATOR
30 SHOUT2
–2–
CXA3512R
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
VDD
1
PRGPOL
I
High: ≥ 2.5V
Low: ≤ 0.8V
OPEN High
Description
Equivalent circuit
VDD VDD
VDD
20k
100k
20k
1
40k
12µ
VDD
VDD
VDD
2
PRG
I
High: ≥ 2.5V
Low: ≤ 0.8V
150k
50k
2
145
50k
POSCTR1
POSCTR2
I
60k
See Table
A-1.
5
2k
6
VDD
10
STATUS
I
High: ≥ 2.5V
Low: ≤ 0.8V
OPEN High
VDD VDD
VDD
20k
100k
20k
10
40k
12µ
VDD
VDD
11
ENB
I
High: ≥ 2.5V
Low: ≤ 0.8V
13
D1OR2
I
High: ≥ 2.5V
Low: ≤ 0.8V
OPEN High
150k
50k
145
50k
ENB pulse input.
See the Timing Chart.
VDD VDD
VDD
100k
Used in XGA and UXGA modes
(when using 2 ICs for a gammacorrected IC).
During forward scan, high: 2nd
device, low: 1st device
During reverse scan, high: 1st
device, low: 2nd device
See Table B.
VDD
11
VDD
PRG pulse input.
See the Timing Chart.
Output phase adjustment.
Each pin has 4 setting values, for a
total of 16 settings.
(Adjustment in 1 dot clock units in
XGA mode, 1/2 dot clock units in
SVGA mode, and 1 dot clock units in
SXGA mode.)
See Tables A-1, A-2 and A-3.
VDD
VDD
5
6
Selects the latch polarity of the PRG
pulse used as the time reference.
High: PRG pulse is latched at the
falling edge of CLKIN.
Low: PRG pulse is latched at the
rising edge of CLKIN.
Select the polarity with sufficient
timing margin after adjusting the
analog video and CLKIN phases
with DLYCTR.
20k
13
40k
12µ
–3–
20k
CLKOUT pin frequency selection.
High: same frequency as MCLK
Low: double the MCLK frequency
CXA3512R
Pin
No.
Symbol
I/O
Standard
voltage level
VDD
14
DIRCTR
I
High: ≥ 2.5V
Low: ≤ 0.8V
OPEN High
Description
Equivalent circuit
VDD VDD
VDD
20k
100k
20k
14
40k
12µ
Scan direction setting.
Low: output as a time series in
descending order (reverse scan) of
output pin symbol (in order from
SHOUT6 to SHOUT1)
High: output in ascending order
(forward scan)
VDD
10µ
VDD VDD
16
DCFBSW
I
OPEN High
Offset cancel circuit on/off switch.
High: cancel circuit on
Use this pin at on (open).
100k
16
40k
40k
VCC
17
19
21
28
30
32
SHOUT6
SHOUT5
SHOUT4
SHOUT3
SHOUT2
SHOUT1
VCC VCC
300
17 28
O
1.5 to 13.5V
Demultiplexer outputs.
Can be connected directly to the
LCD input pins.
19 30
300
21 32
VCC
VCC
70µ
VCC
LCD common voltage of panel
output.
Can be set to VSIGCNT to
(VSIGCNT – 3V) by the Pin 34 input.
500
33
VCOMOUT
O
3 to 7V
33
145
60k
500
VCC
VCC
34
VCOMOFF
I
0 to 10V
60µ
2k
34
100k
VCOMOUT (Pin 33) voltage setting.
VCOMOUT is the same potential as
SIGCNT for input of 0V, and
approximately 3V lower than that for
input of 10V.
VCC
35
SIGCNT
I
7V
Signal center voltage (inversion
folded voltage) input.
Normally, set to 7V.
35
2k
20µ
–4–
CXA3512R
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
VDD VDD
36
FRP
I
High: ≥ 2.5V
Low: ≤ 0.8V
Description
VDD
Invert pulse input.
High: inverse
Low: non-inverse
See the Timing Chart.
100k
36
10k
50µ
VCC
VCC
78k
37
37
SID_O
O
0.2p
2 to 12V
145
78k
SID block output.
Provide an external buffer for
precharge.
0.2p
VCC
VCC
38
SID_R
I
3.3V
Precharge signal invert offset
adjustment.
When using the CXA2111R SID,
connect to the V33 output of the
CXA2111R.
10µ
38
30k
VCC
VCC
39
SID_IN
I
2.3 to 3.3V
Precharge waveform input.
Can be connected directly to the
CXA2111R SID output.
Connect to 5V when not using the
SID block.
40µ
39
145
VCC
200
44
SH_IN
I
2 to 10V
44
200
550µ
Analog demultiplexer input.
Connect to the VIDEO_O (Pin 45)
output.
Do not input 2V or less.
VCC
VCC VCC
VCC
45
VIDEO_O
O
2 to 10V
600µ
45
600µ
–5–
Invert amplifier output.
Connect directly to Pin 44.
When using two CXA3512R in
parallel in XGA or UXGA mode, use
the invert amplifier of only one IC,
and connect the output to Pin 44 of
both ICs.
CXA3512R
Pin
No.
Symbol
I/O
Standard
voltage level
VCC
46
VIDEO_R
I
Description
Equivalent circuit
3.3V
VCC
Input the 100% white level DC of the
signal input to VIDEO_I.
When using the CXA2111R,
connect to the V33 output of the
CXA2111R. When using bipolar
DAC output for VIDEO_I, connect to
the DAC supply voltage.
VCC
Video input.
Connect a gamma-corrected
1.5Vp-p analog video output.
Can be connected directly to the
CXA2111R video output. Connect
to 5V when not using the invert
amplifier.
10µ
46
30k
VCC
47
VIDEO_I
I
2 to 3.3V
420µ
47
145
VCC
VCC
49
CAL_R
I
2.7V
Calibration level input for offset
cancel.
Input the DC level during noninverse with the most highly visible
gradation. Normally, approximately
2.5 to 3V.
50µ
49
145
VCC
100µ
VCC
VCC
50
CAL_O
O
700
3 to 11V
50
145
Calibration amplifier output.
Connect directly to Pin 51.
When using two CXA3512R in
parallel in XGA or UXGA mode, use
the calibration amplifier of only one
IC, and connect the output to Pin 51
of both ICs.
VCC
51
CAL_I
I
Calibration level input for offset
cancel.
Connect to CAL_O.
30k
3 to 11V
51
30k
54
55
MCLK
MCLKX
I
PECL
differential
(amplitude
0.4V or more
between VDD
and 2V) or
TTL input
VDD
VDD
140k
54
55
1k
60k
100µ
–6–
Dot clock inputs.
PECL differential input or TTL input.
For TTL input, input to MCLK and
connect MCLKX to GND via a
capacitor.
Always input the dot clock or
equivalent signal to these pins even
when not using CLKOUT.
(Otherwise, noise may result.)
CXA3512R
Pin
No.
Symbol
I/O
Standard
voltage level
VDD
58
DLYCTR
I
Description
Equivalent circuit
Dot clock phase adjustment.
The CLKOUT phase relative to
MCLK can be changed by the
voltage of this pin.
Connection to the CXA2111R
DLY_CNT output allows digital
control using the I2C register of the
CXA2111R.
VDD
58
3 to 5V
10k
25µ
VDD
59
60
CLKOUT
CLKOUTX
O
VDD
59
VDD – 0.3V
to VDD
60
1m
2k
CLKIN
CLKINX
I
VDD – 0.3V
to VDD
1m
VDD VDD
VDD
62
63
Phase-adjusted dot clock outputs.
150
2k
62
63
145
100µ
VDD
VDD
64
F/H_CNT
I
High: ≥ 2.5V
Low: ≤ 0.8V
OPEN High
100k
Dot clock inputs for timing
generation.
Connect the CLKOUT (CLKOUTX)
pin.
When not using the CLK phase
adjustment function, the dot clock
can also be input directly to these
pins by PECL differential input.
VDD VDD
20k
64
40k
12µ
20k
SHOUT output timing selection.
High: SHOUT 1 to 3 and SHOUT 4
to 6 are output at different timing.
Low: SHOUT 1 to 6 are output at the
same timing.
23
PGND
GND
Power GND.
26
PVCC
15.5V
Power VCC.
Connect directly to VCC.
42
VCC
15.5V
15V power supply.
52
VDD
5V
5V power supply.
53
DGND
GND
Digital GND.
GND
Analog GND.
8, 9,
24, 25,
GND
40, 41,
56, 57
3, 4,
7, 12,
15, 18,
20, 22, NC
27, 29,
31, 43,
48, 61
No connection.
Not connected to anything.
–7–
CXA3512R
Electrical Characteristics (See Electrical Characteristics Measurement Circuit)
(VDD = 5V, VCC = 15.5V, VSIGCEN = 7V, Ta = 25 ± 3°C)
No.
Item
Symbol
Measurement
points
Measurement contents
Min.
Typ. Max.
Unit
1
VDD current
consumption
IDD
IVDD
IDD = IVDD
20
28
42
mA
2
VCC current
consumption
ICC
IVCC1
IVCC2
ICC = IVCC1 + IVCC2
30
45
65
mA
3
Input – output gain ASHOUT
VSHOUT
VIN
ASHOUT = VSHOUT (AC)/VIN
—
3
—
times
4
Invert amplifier
gain
VINV
VIN
AINV = VINV (AC)/VIN
—
2
—
times
VINV
Input a square wave from VIN
so that the VINV output
amplitude is 3.0Vp-p.
Measure the slew rate at 10 to
90% of output waveform rise
or fall. (for inverse or noninverse)
—
700
—
V/µs
—
90
—
MHz
5
Invert amplifier
slew rate
AINV
SRINV
6
Invert amplifier
BWINV
output band width
VINV
Input 2.5V DC, 100mVp-p AC
from Pin 47 (VIDEO_IN) and
measure VINV. The frequency
that is –3dB to 100kHz. (for
inverse or non-inverse)
7
Output delay
deviation for
inverse/noninverse
TDIFF
VINV
Invert amplifier delay time
difference for inverse and noninverse.
—
2
4
ns
8
SID output gain
ASID
VSID
VSID_IN
ASID = VSID (AC)/VSID_IN
—
4
4.4
times
30
50
—
V/µs
Vsig
V
9
SID block output
slew rate
SRSID
VSID
Input an invert pulse to Pin 44
(FRP), load capacitance C7 =
47pF, and apply DC input
voltage to VSID_IN so that VSID
is 2.5V/11.5V.
Measure the slew rate at 10 to
90% of output waveform rise
or fall.
10
VCOM adjustable
range
VCOM
VCOM
VCOM output voltage when
Pin 34 (VCOMOFF) is varied
from 0 to 10V.
11
First stage
SH_OUT
slew rate
SRSH1
12
SH_OUT
slew rate
SROUT
—
VOUT1 to
VOUT6
Vsig – 2 —
First stage sample-and-hold
slew rate on Block Diagram.
—
700
—
V/µs
Input a square wave from VIN
so that the VOUT1 to VOUT6
output amplitude is 3.5Vp-p.
Measure the slew rate at 10 to
90% of output waveform rise
or fall. (load 270pF, for inverse
or non-inverse)
—
150
—
V/µs
–8–
CXA3512R
No.
Item
Symbol
13
MCLK input
frequency range
fMCLK
14
TG operating
frequency range
fTG
15
VIDEO_I input
signal range
16
VIDEO_I input
signal amplitude
range
17
SHOUT minimum
output voltage
Measurement
points
Measurement contents
Min.
Typ. Max.
Unit
D1OR2 = High
(CLKOUT = MCLK)
14
—
65
MHz
—
Maximum frequency at which
the sample-and-hold timing
pulse is output properly.
—
—
120
MHz
VINR
—
VIDEO_I input voltage range
when VIDEO_R is set to 3.3V.
1.5
—
3.7
V
VIN
—
Maximum signal amplitude
range of VIDEO_I input signal
—
—
1.5
V
VMIN
VOUT1 to
VOUT6
Minimum voltage at which
sample-and-hold output
(SHOUT 1 to SHOUT 6) can
be output.
1.5
2
—
V
18
SHOUT maximum
VMAX
output voltage
VOUT1 to
VOUT6
Maximum voltage at which
sample-and-hold output
(SHOUT 1 to SHOUT 6) can
be output.
—
13
13.5
V
19
Output deviation
between
channels 1
VOUT1 to
VOUT6
Value obtained by subtracting
minimum VOUT1 to VOUT6 value
from maximum VOUT1 to VOUT6
value when CAL_R = 2.6V
and VIDEO_I = 2.6V.
—
4
10 mVp-p
20
Output deviation
between
channels 2
VOUT1 to
VOUT6
Value obtained by subtracting
minimum VOUT1 to VOUT6 value
from maximum VOUT1 to VOUT6
value when CAL_R = 2.6V
and VIDEO_I = 3.3V or 1.9V.
—
4
40 mVp-p
VOUT1 to
VOUT6
Value obtained by subtracting
minimum VOUT1 to VOUT6 value
from maximum VOUT1 to VOUT6
value when CAL_R = 2.6V
and VIDEO_I = 2.6V.
(when using two CXA3512R)
—
10
20 mVp-p
VOUT1 to
VOUT6
Value obtained by subtracting
minimum VOUT1 to VOUT6 value
from maximum VOUT1 to VOUT6
value when CAL_R = 2.6V
and VIDEO_I = 3.3V or 1.9V.
(when using two CXA3512R)
—
10
60 mVp-p
21
22
Output deviation
between ICs 1
Output deviation
between ICs 2
DOUT1
DOUT2
DIC1
DIC2
Unless otherwise specified, pin setting conditions are as follows.
(46) VIDEO_R = 3.3V, (47) VIDEO_I = 2.0V, (39) SID_IN = 2.3V, (38) SID_R = 3.3V, (35) SIGCNT = 7.0V,
(34) VCOMOFF = 0V, (1) PRGPOL = 0V, (5) POSCTR1 = 0V, (6) POSCTR2 = 0V, (10) STATUS = 0V,
(13) D1OR2 = 5V, (14) DIRCTR = 5V, (49) CAL_R = 2.6V, (58) DLYCTR = 4.0V, (64) F/H_CNT = 0V,
(36) FRP = 0V, fCLK32.5MHz
–9–
CXA3512R
Electrical Characteristics Measurement Circuit
2.3V VSID_IN
VINV
VSID
CLKINX
F/H_CNT
VCOMOFF
SIGCNT
FRP
SID_O
SID_R
SID_IN
GND
GND
VCC
NC
SH_IN
VCOMOUT
33
32
VCOM
52
S/H
53
S/H
S/H
29
BUFFER
28
OFFSET CANCEL
54
S/H
55
CLOCK
DELAY
57
S/H
27
BUFFER
26
OFFSET CANCEL
D
56
S/H
S/H
S/H
S/H
25
BUFFER
24
OFFSET CANCEL
58
S/H
S/H
pulses
59
60
S/H
S/H
S/H
offset
cancel
mode
timing
64
23
BUFFER
22
S/H
21
BUFFER
20
OFFSET CANCEL
62
63
S/H
OFFSET CANCEL
TIMING
GENERATOR
61
S/H
S/H
30
S/H
19
BUFFER
18
OFFSET CANCEL
17
SHOUT1
VOUT1
NC
C1 270pF
SHOUT2
VOUT2
NC
C2 270pF
SHOUT3
VOUT3
NC
PVCC
IVCC2 C3 270pF
A
VCC
GND
GND
PGND
NC
SHOUT4
VOUT4
NC
C4 270pF
SHOUT5
VOUT5
NC
C5 270pF
SHOUT6
VOUT6
C6 270pF
1
VDD
2
3
4
5
6
7
8
9
10
VDD
SW1
SW2
11
12
13
VDD
SW3
14
15
16
DCFBSW
CLKIN
34
NC
NC
35
DIRCTR
CLKOUTX
36
D1OR2
CLKOUT
37
NC
DLYCTR
38
ENB
GND
39
STATUS
GND
40
GND
MCLKX
41
GND
MCLK
51
NC
Frequency
fCLK
DGND
42
V VCOM
31
POSCTR2
DIFF
BUFFER2
A
43
SID
POSCTR1
VDD
VDD
44
CALIBRATION
AMP
NC
IVDD
45
50
NC
CAL_I
PRG
CAL_O
46
IVCC1 A
INVERT
AMP
49
PRGPOL
CAL_R
47
VIDEO_O
NC
48
VIDEO_I
VIN
2.0V
VIDEO_R
VCC
VDD
SW4
VCC
VDD
15.5V
– 10 –
5V
CXA3512R
Level Diagram
VIDEO_I to SHOUT
(SIGCNT = 7V, VIDEO_R = input 100% white level)
VCC
12.5V
10.667V
8V
7.667V
SIGCNT = 7V
6.333V
6V
V white
V black
VIDEO_I = 1.5Vp-p
3.333V
1.5V
GND
VIDEO_I
2.0 times
VIDEO_O
SH_IN
1.5 times
SHOUT
VIDEO_I to VIDEO_O
The formulas for calculating the VIDEO_I to SHOUT internal DC gain are as follows.
For non-inverse:
VIDEO_O = 2.0 × (VIDEO_I – VIDEO_R) + SIGCNT × (1 – 1/10.5)
SHOUT = 3.0 × (VIDEO_I – VIDEO_R) + SIGCNT × (1 – 1/7)
For inverse:
VIDEO_O = –2.0 × (VIDEO_I – VIDEO_R) + SIGCNT × (1 + 1/10.5)
SHOUT = –3.0 × (VIDEO_I – VIDEO_R) + SIGCNT × (1 + 1/7)
– 11 –
CXA3512R
Description of Operation
1. Invert Amplifier Block
FRP
VIDEO_R
input level
(100% white)
VIDEO_I
VIN
approx.
3×VIN
approx.
1V
VSIGCNT
VIDEO_O
Calibration level
The CXA3512R is designed so that the optimal signal for the LCD panel is output from the SHOUT pins when
a signal in the range from 1.8 to 3.3V is applied to the VIDEO_I input. As shown in the figure above, when a γ
corrected video signal is input to VIDEO_I, the signal is inverse/non-inverse amplified according to the FRP
input (TTL level) and output from VIDEO_O. The DC level is determined by the VIDEO_R input. Input a level
equivalent to 100% white of input. Also, when not using the invert amplifier, connect VIDEO_I to 5V.
2. Analog Demultiplexer Block
The SH_IN analog input signal is converted from a time series signal to a 6-channel (or 12-channel) cyclic
parallel signal by the sample-and-hold group which is appropriately controlled by the on-chip timing generator.
These signals pass through a fixed-gain (= 1.5 times) buffer amplifier and are output to SHOUT. These outputs
can directly drive the input load of the LCD panel.
When using a SVGA panel, connect the (6-channel output) VIDEO_O output directly to the adjacent SH_IN.
XGA panels use 12-channel output, so short the SH_IN of two CXA3512R and connect them to the VIDEO_O
output of one of the IC. The on-chip TG recognizes master/slave by the low/high STATUS (Pin 10) input. For
forward scan, the output alternates between the ICs in the order of master SHOUT1 → slave SHOUT1 →
master SHOUT2 → slave SHOUT2 → master SHOUT3 and so on. Connect the wiring to the LCD panel inputs
in this order.
The sample-and-hold pulse generation timing is shown on the following pages. These pulses are not output
and are used only inside the IC.
– 12 –
Slave
(STATUS = high)
Master
(STATUS = low)
– 13 –
SH3_4 to 6
SH3_1 to 3
SH2_4 to 6
SH2_1 to 3
SH1_6ch
SH1_5ch
SH1_4ch
SH1_3ch
SH1_2ch
SH1_1ch
SH3_4 to 6
SH3_1 to 3
SH2_4 to 6
SH2_1 to 3
SH1_6ch
SH1_5ch
SH1_4ch
SH1_3ch
SH1_2ch
SH1_1ch
Internal Sample-and-Hold Pulse Timing Chart 1
Forward scan (DIRCTR = high), F/H_CNT = high
When F/H_CNT = low:
same timing as SH3_1 to 3
When F/H_CNT = low:
same timing as SH3_1 to 3
CXA3512R
Slave
(STATUS = high)
Master
(STATUS = low)
– 14 –
SH3_4 to 6
SH3_1 to 3
SH2_4 to 6
SH2_1 to 3
SH1_6ch
SH1_5ch
SH1_4ch
SH1_3ch
SH1_2ch
SH1_1ch
SH3_4 to 6
SH3_1 to 3
SH2_4 to 6
SH2_1 to 3
SH1_6ch
SH1_5ch
SH1_4ch
SH1_3ch
SH1_2ch
SH1_1ch
Internal Sample-and-Hold Pulse Timing Chart 2
Reverse scan (DIRCTR = low), F/H_CNT = high
When F/H_CNT = low:
same timing as SH3_4 to 6
When F/H_CNT = low:
same timing as SH3_4 to 6
CXA3512R
CXA3512R
3. Timing Generator (TG) Block
The on-chip TG operates by one pair of differential clock inputs (CLK_IN, CLK_INX) and two horizontal sync
signal inputs (PRG, ENB), and generates the timing pulses needed by the demultiplexer block and the output
deviation cancel circuit. The various operation modes can be designated by the pin voltage settings.
• Input timing signal conditions
30 clk or more
ENB
60 clk or more
PRG
4 clk or more
FRP
0 to 5 clk
Maintain the ENB, PRG and FRP phase relationship shown in the timing chart above, with the CLK_IN input
sync as 1 clk. In particular, when FRP changes between high and low, be sure to input ENB and PRG as
shown above. Otherwise, the IC may suffer irrecoverable deterioration in the worst case.
• Operation mode setting
Table B.
SVGA (6-channel mode) XGA/UXGA (12-channel/24-channel mode)
SXGA (12-channel mode)
Master
Slave
STATUS
D1OR2
H/L∗1
L
H
L
H
H
∗1 The output phase can be shifted by 1/2-dot clock in SVGA/SXGA mode by changing STATUS.
• Scan direction setting
The output scan direction can be changed by the DIRCTR (Pin 14) input.
Pin 14
Direction
Scan order
H
Forward SHOUT1 → SHOUT2 → SHOUT3 → SHOUT4 → SHOUT5 → SHOUT6 → SHOUT1 →
L
Reverse SHOUT6 → SHOUT5 → SHOUT4 → SHOUT3 → SHOUT2 → SHOUT1 → SHOUT6 →
The scan direction can be changed by the Pin 14 setting without changing other connections even when using
two CXA3512R such as in XGA mode.
– 15 –
CXA3512R
• Output phase setting
The phase of each SHOUT output relative to the analog input can be adjusted in CLK_IN clock units by the
Pins 5 and 6 input levels.
Each input pin has 4 setting values, for a total of 16 settings.
POSCTR1 is the lower bits setting, POSCTR2 is the upper bits setting, and the setting values are as shown in
Table A-1.
Table A-2. CMOS Logic Connection Setting
Value and CMOS Output Pins
Table A-1. Setting Voltage Range
for Output Phase
Setting value
Threshold
Setting value
a
b
0
to 0.75V
0
L
L
1
1.15 to 1.50V
1
Hi-Z
L
2
1.70 to 2.55V
2
Hi-Z
H
3
H
H
3
2.95V to
There are two ways to use these pins.
A. Connect directly to the CXA2111R
Connect to the corresponding CXA2111R pins POS_CNT1 and POS_CNT2. This allows bit setting via the
CXA2111R I2C bus.
B. Connect to CMOS logic
Connect CMOS logic as shown in the figure. This allows digital control by tri-state control of Pin a. See
Table A-2.
R1 is a threshold setting resistor that provides the voltage for setting values 1 and 2. The appropriate
resistance value changes depending on the number of CXA3512R driven by one CMOS logic (1-channel or 3channel RGB drive, or one CXA3512R (6-outputs/ch) or two CXA3512R (12-outputs/ch)).
Recommended resistance values are given in Table A-3.
CMOS Logic Connection
CXA3512R Usage and Threshold Setting Resistor R1
Table A-3.
CMOS
a
CXA3512R
b
5
R1
POS_CNT1 or
POS_CNT2
(Pin 6)
R1 value
RGB 1-channel drive
RGB 3-channel drive
6 outputs
12 outputs
6 outputs
12 outputs
250kΩ
150kΩ
100kΩ
47kΩ
CMOS supply voltage = 3.3 to 5V
– 16 –
CXA3512R
4. Dot Clock Phase Adjustment Block
The CXA3512R has a function for adjusting the phase between the analog video input and the dot clock input
to achieve stable reproduction of high definition images. Images with no jitter and flicker can be reproduced by
optimizing the setting.
The 1/2-dot clock input to MCLK and MCLKX (PECL level) is input to the phase comparator of the on-chip PLL
clock generator. The output from CLKOUT and CLKOUTX becomes the internal VCO output. CLKOUT is the
same frequency as MCLK when the D10R2 (Pin 13) input is high, and twice the MCLK frequency when the
D10R2 input is low.
A large amplitude logic with a threshold value of 1.5V can also be connected directly to MCLK instead of
PECL. In this case, connect MCLKX to GND via a capacitor of approximately 100pF. (PECL level input is
recommended when the MCLK input is used around 50MHz.)
The CLKOUT phase can be adjusted up to ±180° according to the DC level (3 to 5V) of the DLYCTR (Pin 58)
input.
By connecting CLKOUT to the TG clock input, the analog video signal and first stage sample-and-hold phases
can be finely adjusted using the DLYCTR DC level.
When using two CXA3512R in XGA mode, input the CLKOUT of one CXA3512R to the CLKIN of both in order
to match the timing of both ICs. In this case, input the same clock to MLCK of both ICs.
5. Calibration Amplifier Block
The CXA3512R generates the deviation cancel circuit reference with a calibration amplifier in order to minimize
the deviation between channels at the highest visibility level.
Input DC level equivalent to approximately 50% gray at VIDEO_I to CAL_R (Pin 49). In addition, directly
connect the CAL_O (Pin 50) output to the adjacent CAL_I.
When using two CXA3512R in XGA mode, connect the CAL_O of one IC to the CAL_I of both ICs, and
connect the unused CAL_R to 5V.
6. SID Block
This block generates the precharge signal used by the LCD panel.
The signal input to SID_IN (Pin 39) is folded at the SIGCNT potential by FRP in the same manner as the invert
amplifier, and output to SID_O (Pin 37). The gain is designed at approximately 4 times. The DC level is
determined by SID_R, and is normally approximately 3.3V.
SID_O cannot directly drive the precharge signal input of the LCD panel. Therefore, connect SID_O via a
buffer having sufficient current supply capability.
SID_O DC calculation formula
Pin 36: low = non-inverse
SID_O = 4 × (SID_IN – SID_R) + 6/7 (SIGCNT)
Pin 36: high = inverse
SID_O = 4 × (SID_R – SID_IN) + 8/7 (SIGCNT)
7. VCOM Block
This block sets the DC potential of the VCOM level.
The VCOMOFF (Pin 34) potential sets the deviation relative to the SIGCNT potential as follows.
VCOMOFF = 0V: VCOMOUT = SIGCNT
VCOMOFF = 10V: VCOMOUT = SIGCNT – 3V
– 17 –
CXA3512R
Combination with the CXA2111R
Used together with the CXA2111R, the CXA3512R can achieve most of the analog signal processing (γ
correction, precharge waveform generation) required by LCD panels.
In addition, I2C serial control of the following functions is possible using the I2C-controlled registers built into
the CXA2111R.
• Output phase adjustment (POSCTR1, 2)
• Clock phase adjustment (DLYCTR)
• Scan direction (DIRCTR)
Connect the pins as shown in the table below to use the various functions.
For details, see the CXA2111R specifications.
CXA2111R
CXA3512R
Video signal
ROUT (18), GOUT (16) or
BOUT (14)
VIDE_IN (47)
Precharge waveform
SIDOUT (6)
SID_IN (39)
POS_CNT (1)
POSCTR1 (5)
POS_CNT (2)
POSCTR2 (6)
Clock phase
DLK_CNT (3)
DLYCTR (58)
Scan direction
DIR_CNT (4)
DIRCTR (14)
Reference level
V33 (8)
VIDEO_R (46)
SID_R (38)
Output phase
– 18 –
CXA3512R
Notes on Operation
1. Notes on Mounting
• The CXA3512R consumes power of approximately 1W. Be sure to take the following measures to prevent
the IC temperature from rising.
A. Pins 8, 9, 24, 25, 40, 41, 56 and 57 (total 8 pins) are connected directly to the "die pad". Electrically
and thermally connect these pins to the inner layer GND plane of a 4-layer substrate using multiple via.
B. Do not mount in high density on a small substrate. Mounting to a 4-layer substrate with an inner layer
copper foil thickness of 30µm or more is recommended.
C. Do not locate the CXA3512R downwind of high thermal loads (lamp, etc.) in sets with fans.
Do not locate the CXA3512R in portions with stagnant air flows in sets without fans.
• The wiring for the CXA3512R alone does not require special consideration, the skew with the PRG pulse
rise timing may cause problems when using a high-speed dot clock. Particularly when using multiple
CXA3512R, the timing of the PRG used as the time reference inside the IC must be matched at the IC
input pins. Care should be taken when designing the board for the effects of propagation time and
reflection, with the PRG line also considered an analog line like MCLK.
If skew with the PRG pulse poses a problem after adjusting the phase relationship between the analog
video input and CLK_IN, it may be possible to solve this problem by adjusting the PRGPOL (Pin 1) H/L
setting for each IC.
2. Input Signals
• Be sure to maintain the FRP, ENB and PRG timings noted in "Description of Operation 3. Timing
Generator (TG) Block".
Special care should be taken to avoid FRP transition without ENB and PRG.
• There is no particular problem when connecting the VIDEO_O output to SH_IN, but in this case do not
input voltages of 2V or less, or (VDD – 2V) or more.
– 19 –
CXA3512R
Application Circuit 1 (to SVGA Panel)
VCC
VCC
5.1k
20k
10k
5.1k
0.1µ
0.1µ
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VCOMOUT
SIGCNT
FRP
SID_O
SID_R
SID_IN
GND
VCC
GND
NC
SH_IN
VIDEO_O
VIDEO_R
VIDEO_I
NC
0.1µ
VCOMOFF
BUFFER
10µ
0.1µ
33
VDD
CLK H 32
CXA3106Q
CLK L 31
20k
CAL_R
49
0.1µ
CAL_O
50
CAL_I
VDD
CXA2111R
SID_OUT 6
V33 8
R_OUT 18
G_OUT 16
B_OUT 14
DLY_CNT 3
POS_CTR1 1
POS_CTR2 2
DIR_CNT 4
10µ
VDD
0.1µ
DGND
MCLK
MCLKX
GND
GND
DLYCTR
CLKOUT
CLKOUTX
NC
CLKIN
CLKINX
FRP
F/H_CNT
51
SID
INVERT
AMP
32
31
CALIBRATION
AMP
VCOM
52
S/H
53
S/H
S/H
29
BUFFER
28
OFFSET CANCEL
54
S/H
55
CLOCK
DELAY
57
S/H
27
BUFFER
26
OFFSET CANCEL
D
56
S/H
S/H
S/H
S/H
25
BUFFER
24
OFFSET CANCEL
58
S/H
S/H
pulses
59
60
S/H
S/H
S/H
offset
cancel
mode
timing
64
BUFFER
22
S/H
21
BUFFER
20
OFFSET CANCEL
62
63
S/H
23
OFFSET CANCEL
TIMING
GENERATOR
61
S/H
S/H
30
S/H
19
BUFFER
18
OFFSET CANCEL
17
SHOUT1
NC
SHOUT2
NC
SHOUT3
(LCX026)
NC
VCC
PVCC
GND
LCD panel
1 Psig
10µ
0.1µ
24 COM
GND
7 Sig1
PGND
5 Sig2
NC
3 Sig3
SHOUT4
2 Sig4
NC
4 Sig5
SHOUT5
6 Sig6
NC
SHOUT6
NRG
Open
15
NC
14
16
DCFBSW
13
DIRCTR
12
D1OR2
11
NC
10
ENB
GND
9
STATUS
8
GND
7
NC
6
POSCTR2
5
POSCTR1
4
NC
3
NC
2
PRG
1
PRGPOL
ENB
Open
VDD
5V
VCC
15.5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 20 –
CXA3512R
VCC
Application Circuit 2 (to XGA Panel)
VCC
5.1k
20k
10k
5.1k
0.1µ
0.1µ
BUFFER
48
VDD
DLYCTR
CLKOUT
POS_CTR1 1
CLKOUTX
POS_CTR2 2
NC
DIR_CNT 4
CLKIN
CLKINX
F/H_CNT
VCOMOUT
SIGCNT
FRP
SID_R
SID_IN
GND
VCC
GND
NC
SH_IN
VIDEO_O
VIDEO_R
SID_O
32
31
CALIBRATION
AMP
VCOM
52
S/H
53
S/H
S/H
55
S/H
BUFFER
28
S/H
27
BUFFER
26
OFFSET CANCEL
D
56
CLOCK
DELAY
57
S/H
S/H
S/H
25
BUFFER
24
OFFSET CANCEL
58
S/H
S/H
pulses
59
60
S/H
2
3
PRG
PRGPOL
1
S/H
S/H
offset
cancel
mode
timing
64
23
BUFFER
22
S/H
21
BUFFER
20
OFFSET CANCEL
62
63
S/H
OFFSET CANCEL
TIMING
GENERATOR
61
S/H
4
5
S/H
30
29
OFFSET CANCEL
54
CLK H 32
CXA3106Q
CLK L 31
S/H
S/H
19
BUFFER
18
OFFSET CANCEL
17
6
7
8
9
10
11
12
Open
13
14
15
0.1µ
33
50
51
31 COM
10µ
SHOUT1
3 Sig1
NC
SHOUT2
5 Sig3
NC
SHOUT3
7 Sig5
NC
VCC
PVCC
GND
10µ
0.1µ
GND
PGND
NC
SHOUT4
9 Sig7
NC
SHOUT5
11 Sig9
NC
SHOUT6
13 Sig11
16
DCFBSW
B_OUT 14
DLY_CNT 3
34
NC
GND
35
DIRCTR
G_OUT 16
36
D1OR2
GND
37
SID
INVERT
AMP
49
38
NC
MCLKX
R_OUT 18
39
ENB
V33 8
40
GND
MCLK
41
STATUS
DGND
42
GND
0.1µ
43
NC
10µ
VDD
44
POSCTR2
CAL_I
VDD
45
POSCTR1
CAL_R
CAL_O
46
NC
0.1µ
47
NC
20k
CXA2111R
SID_OUT 6
VIDEO_I
NC
0.1µ
VCOMOFF
1 Psig
VDD
Open
VDD
Open
LCD panel
(LCX023)
FRP
NRG
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DCFBSW
NC
DIRCTR
NC
ENB
GND
GND
NC
POSCTR2
POSCTR1
NC
NC
NRG
PRGPOL
1
STATUS
VDD
Open
D1OR2
ENB
16
F/H_CNT
64
CAL_O
VDD
CAL_R
CLOCK
DELAY
56
S/H
D
BUFFER
23
S/H
24
S/H
BUFFER
25
OFFSET CANCEL
55
S/H
54
S/H
26
S/H
BUFFER
27
OFFSET CANCEL
53
S/H
52
50
S/H
OFFSET CANCEL
57
51
S/H
S/H
28
S/H
BUFFER
CALIBRATION
AMP
VCOM
NC
48
47
30
31
INVERT
AMP
49
29
46
45
32
SID
44
43
42
41
40
39
38
37
0.1µ
VDD
VDD
36
35
34
SHOUT6
14 Sig12
NC
SHOUT5
12 Sig10
NC
SHOUT4
10 Sig8
NC
PGND
GND
GND
VCC
PVCC
NC
10µ
SHOUT3
0.1µ
8 Sig6
NC
SHOUT2
6 Sig4
NC
SHOUT1
4 Sig2
33
VCOMOUT
0.1µ CAL_I
21
22
VCOMOFF
10µ
BUFFER
SIGCNT
VDD
19
20
FRP
VDD
S/H
58
SID_O
DGND
BUFFER
S/H
SID_R
MCLK
S/H
GND
MCLKX
S/H
OFFSET CANCEL
SID_IN
GND
S/H
S/H
pulses
59
GND
GND
60
VCC
DLYCTR
61
S/H
18
OFFSET CANCEL
NC
CLKOUT
S/H
TIMING
GENERATOR
SH_IN
CLKOUTX
OFFSET CANCEL
62
VIDEO_O
NC
VIDEO_R
CLKIN
17
mode
timing
offset
cancel
63
VIDEO_I
CLKINX
VDD
VDD
5V
VCC
15.5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 21 –
CXA3512R
Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, SIGCNT = 7.0V, Ta = 25 ± 3°C)
CLKOUT phase to MCLK vs. DLYCTR voltage
180
MCLK = 20MHz
120
Phase [deg]
60
D1OR2 = HIgh
0
–60
–120
–180
3
3.5
4
4.5
5
DLYCTR (Pin 58) voltage [V]
SID_O voltage vs. SID_R voltage (1)
SID_O voltage vs. SID_R voltage (2)
16
16
SID_IN = 2.3V
SID_IN = 4.0V
14
SID_O (Pin 37) voltage [V]
SID_O (Pin 37) voltage [V]
14
12
FRP = High
10
8
6
4
12
FRP = High
10
8
6
4
FRP = Low
FRP = Low
2
0
2
0
1
2
3
4
0
5
0
1
SID_R (Pin 38) voltage [V]
2
3
4
5
SID_R (Pin 38) voltage [V]
SID_O voltage vs. SID_IN voltage (1)
SID_O voltage vs. SID_IN voltage (2)
16
16
SID_R = 3.3V
14
SID_O (Pin 37) voltage [V]
SID_O (Pin 37) voltage [V]
14
12
FRP = High
10
8
6
4
FRP = High
12
10
SID_R = 5.0V
8
6
4
FRP = Low
2
0
FRP = Low
2
0
1
2
3
4
0
5
SID_IN (Pin 39) voltage [V]
0
1
2
3
SID_IN (Pin 39) voltage [V]
– 22 –
4
5
CXA3512R
VIDEO_O voltage vs. VIDEO_R voltage (1)
VIDEO_O voltage vs. VIDEO_R voltage (2)
12
12
VIDEO_IN = 3.5V
10
VIDEO_O (Pin 45) voltage [V]
VIDEO_O (Pin 45) voltage [V]
VIDEO_IN = 1.8V
FRP = High
8
6
FRP = Low
4
2
0
1
2
3
4
10
FRP = High
8
6
FRP = Low
4
2
5
0
VIDEO_R (Pin 46) voltage [V]
VIDEO_O voltage vs. VIDEO_IN voltage (1)
5
VIDEO_R = 5.0V
12
VIDEO_O (Pin 45) voltage [V]
VIDEO_O (Pin 45) voltage [V]
4
VIDEO_O voltage vs. VIDEO_IN voltage (2)
VIDEO_R = 3.3V
FRP = High
10
8
6
4
FRP = Low
2
10
FRP = High
8
6
FRP = Low
4
2
0
1
2
3
4
0
5
VIDEO_IN (Pin 47) voltage [V]
VCOMOUT voltage vs. VCOMOFF voltage
6.5
6.0
5.5
5.0
4.5
4.0
0
2
4
6
8
0
1
2
3
4
VIDEO_IN (Pin 47) voltage [V]
7.0
VCOMOUT (Pin 33) voltage [V]
3
14
12
3.5
2
VIDEO_R (Pin 46) voltage [V]
14
0
1
10
VCOMOFF (Pin 34) voltage [V]
– 23 –
5
CXA3512R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
1.7MAX
14.0 ± 0.1
0.1
33
48
32
(15.0)
49
B
A
17
64
16
+ 0.08
0.37 – 0.07
(0.5)
1
0.8
0.13 M
0.25
(0.5)
0° to 10°
0.6 ± 0.2
(0.35)
DETAIL A
(0.125)
+ 0.08
0.37 – 0.07
0.145 ± 0.04
0.1 ± 0.1
DETAIL B
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L02
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
LQFP064-P-1414
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 24 –