System-on-a-Chip (SoC) Device Supports 48× Speed CD-ROM Drives Digital Signal-processing IC for CD-ROM Systems CXD3030R A CD-ROM playback speed of 48× has finally been achieved. We can say that the CD-ROM has reached the transfer rates of hard disks only a few years ago. ■ Implements all the digital signal processing required for playback in a single chip. ■ Integrates digital servo control, digital signal processing, a CDROM decoder, ATAPI interface, and DRAM on a single chip. ■ Playback speeds: Up to 48× ■ Provides even higher mounting densities by including on-chip RAM. The CD-ROM is now indispensable in personal computers for installing application software. The CXD3030R system-on-a-Chip (SoC) product represents an optimal selection for compact basic design, energy-saving design, and increased speed. The CXD3030R is a system-on-a-Chip (SoC) product that integrates digital servo control, digital signal processing, a CD-ROM decoder, ATAPI interface, and DRAM on a single chip. It supports playback speeds up to 48×. V O I C When I joined Sony, 2× speed drives had just been released. It’s impressive how far we’ve come since then. Although the economy has its ups and downs, technology is always progressing. While I know that my fantasies of my salary increasing as fast as technology are unreasonable, I am aware that technology has advanced this far through the efforts of many people in many areas. I recommend that you experience this speed directly. E Digital Servo Control While the CD-ROM optical system includes several adjustment points, the CXD3030R can automatically set all of these to optimal values. It includes a 6-stage cascaded digital filter as the tracking filter, and can flexibly support different pickups and playback speeds. The inclusion of an on-chip wide capture PLL circuit allows the CXD3030R to be freely set up to get the maximum performance from the drive mechanism, providing support for both CAV techniques using an FG signal, and partial CAV techniques that take into account the limitations on the speeds the motor can provide. A drive with a short access time can be designed by using the mode in which the VCO is controlled by a microcomputer and the pull-in time after access is minimized. Digital Signal Processing The CXD3030R supports playback speeds up to 48×. Since this speed is 48 times the speed at which audio CDs are played back, the CD-ROM certainly has progressed to surprising speeds. The built-in buffered audio play function allows this device to play back CD-DA audio while actually reading the disc in high-speed CAV mode. An extensive set of power saving functions are also provided since an increasingly high percentage of notebook personal computers include a CD-ROM drive. In addition to providing functions that lower power consumption in the standby state, this device also achieves reduced power consumption during playback. ATAPI Sony has led the industry by integrating on a single chip an interface and a decoder that support ATAPI ULTRA DMA (33). It goes without saying that the CXD3030R implements all related operations even while reaching a speed of 48×. CXD3030R RF amp. Disc CXA2581 Digital signal transaction block ROM decoder block Digital servo block Control block 1-bit D/A converter DRAM Audio out Spindle motor pickup Driver ATAPI interface block ATAPI bus Sub CPU System control microcomputer (SPC970) ■ Figure 1 System Block Diagram for 48× Speed CD-ROM System-on-a-Chip LSI System XTLO XTLI 138 139 Data block VDD DRVDD 32K RAM VSS 1-Mbit DRAM Digital PLL Data processor EFM Sync. protector CPU Interface (Serial I/F) Auto sequencer Descrambler Host I/F ■ Figure 2 CXD3030R Block Diagram 77 to 83 84 to 91 D0 to 7 69 70 74 75 76 A0 to 6 131 XRD 130 XCS 142 143 135 134 Sub CPU I/F XWAT 63 10 DOUT 58 14 57 56 FOK 2 SENS 3 MIRR 4 DFCT 5 Clock gen. XTL1 OP amp. DAC I/F XTL2 8 Fs 1-bit DAC DAC COUT Servo DSP TAO 8-bit A/D D/A converter block SAO OP amp. analog SW FAO 34 35 36 37 38 39 95, 96 HCS0, 1 97 to 99 HA0 to 2 Sync. control FOK MIRR DFCT PWM2P Servo block 12-byte packet FIFO Main data error correction Digital out PWM2N PWMI 13 ADIO 33 Subcode deinterleave & ECC CDDSP I/F CLV processor MDP 12 110 to 113, 115 to 118, 120 to 123, HDB0 to F 125 to 128 ATAPI registers Subcode P to W processor Subcode Q processor DMA FIFO Priority resolver PWM1P SQCK 62 SQSO 61 RFDC CE TE SE FE VC Error correction block Timing generator PWM1N ASY BSSD 49 50 27 60 DMA sequencer Address gen. RFAC 47 ASYI ASYO WFCK SCOR DRVSS Clock gen. XWR 44 43 42 45 XINT PCO FILI FILO CLTV 104 105 102 106 101 100 103 94 93 107 XHRD XHWR XHAC HDRQ HINT XS16 REDY DASP XPDI XHRS