CXP820P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP820P60 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, capture timer/counter, fluorescent display panel
controller/driver, remote control reception circuit, and
PWM output circuit besides the basic configurations
of 8-bit CPU, ROM, RAM, and I/O port.
The CXP820P60 also provides sleep/stop function
that enables lower power consumption.
CXP820P60 is the PROM-incorporated version of the
CXP82052/82060 with bult-in mask ROM. This provides
the additional feature of being able to write directly into
the program. Thus, it is most suitable for evaluation
use during system development and for small-quantity
production.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity
60K bytes
• Incorporated RAM capacity
3984 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 3.25µs/16MHz)
— Serial interface
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type, (MSB/LSB first selectable), 1 channel
Start-stop synchronization (UART), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time-base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display panel
Supports the universal grid fluorescent display panel
controller/driver
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix
supportable)
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
17 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP
• Piggy/Evaluation chip
CXP82000 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97638-PS
–2–
RAM
RAM
ADJ
TO
CINT
EC1
16-BIT CAPTURE
TIMER/COUNTER 2
8-BIT TIMER 1
8-BIT TIMER/COUNTER 0
EC0
BUFFER
RAM
SERIAL INTERFACE (CH1)
SERIAL
INTERFACE
(CH0)
CS0
SI0
SO0
SCK0
FIFO
SI1
SO1
SCK1
REMOCON
14-BIT PWM GENERATOR
UART RECEIVER
UART TRANSMITTER
UART BAUD RATE
GENERATOR
KEY SCAN
FDP
CONTROLLER/
DRIVER
A/D CONVERTER
RMC
PWM
TxD
RxD
32
A24 to A56
VFDP
KR0 to KR7
8
8
A16 to A23
G0/A0 to G15/A15 16
8
2
2
2
PRESCALER/
TIME-BASE TIMER
PROM
60K BYTES
SPC 700
CPU CORE
TEX
TX
EXTAL
XTAL
RST
VDD
VSS
Vpp
32kHz
TIMER/COUNTER
RAM
3984 BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
PB0 to PB7
PC0 to PC7
8
8
8
PE6 to PE7
PF0 to PF7
PG0 to PG7
PH0 to PH7
2
8
8
8
4
PI0 to PI4
PE0 to PE5
6
PD0 to PD7
PA0 to PA7
8
PORT B
AN0 to AN7
2
PORT A
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PORT I
INT0
INT1
INT2
INT3/NMI
INTERRUPT CONTROLLER
Block Diagram
CXP820P60
CXP820P60
A20
A19
A18
A17
A16
G15/A15
G14/A14
G13/A13
VDD
G12/A12
G11/A11
G10/A10
G9/A9
G8/A8
G7/A7
G6/A6
G5/A5
G4/A4
G3/A3
G2/A2
Pin Assignment (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
G1/A1
1
80
A21
G0/A0
2
79
A22
Vpp
3
78
A23
PE0/EC0/INT0
4
77
PH7/A24
PE1/EC1/INT1
5
76
PH6/A25
PE2/INT2
6
75
PH5/A26
PE3/INT3/NMI
7
74
PH4/A27
PE4/RMC
8
73
PH3/A28
PE5/CINT
9
72
PH2/A29
PE6/PWM
10
71
PH1/A30
PE7/TO/ADJ
11
70
PH0/A31
PC0/KR0
12
69
PG7/A32
PC1/KR1
13
68
PG6/A33
PC2/KR2
14
67
PG5/A34
PC3/KR3
15
66
PG4/A35
PC4/KR4
16
65
PG3/A36
PC5/KR5
17
64
PG2/A37
PC6/KR6
18
63
PG1/A38
PC7/KR7
19
62
PG0/A39
PB0/TxD
20
61
PF7/A40
PB1/CS0/RxD
21
60
PF6/A41
PB2/SCK0
22
59
PF5/A42
PB3/SI0
23
58
PF4/A43
PB4/SO0
24
57
PF3/A44
PB5/SCK1
25
56
PF2/A45
PB6/SI1
26
55
PF1/A46
PB7/SO1
27
54
PF0/A47
PI0
28
53
PD7/A48
PA0/AN0
29
52
PD6/A49
PA1/AN1
30
51
PD5/A50
Note) 1. Vpp (Pin 3) is left open.
2. VDD (Pins 44 and 89) are both connected to VDD.
–3–
PD4/A51
PD3/A52
PD2/A53
PD1/A54
PD0/A55
VFDP
VDD
PI2/TX
PI3/TEX
Vss
XTAL
RST
EXTAL
PI1
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP820P60
Pin Description
Symbol
I/O
Functions
(Port A)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the program in a unit of
4 bits.
(8 pins)
PA0/AN0
to
PA7/AN7
I/O/
Analog input
PB0/TxD
I/O/Output
UART transmission data output.
PB1/CS0/RxD
I/O/Input/Input
UART reception
Chip select input for
serial interface (CH0). data input.
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
Serial data input (CH1).
PB7/SO1
I/O/Output
Serial data output (CH1).
(Port B)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the program in a unit of
4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
I/O/Input
(Port C)
8-bit I/O port. I/O can be set in a
unit of single bits. Capable of
driving 12mA sink current.
Incorporation of the pull-up
resistor can be set through the
program in a unit of 4 bits.
(8 pins)
Serves as key return inputs when
operating key scan with fluorescent
display panel (FDP) segment signal.
(8 pins)
PD0/A55
to
PD7/A48
I/O/Output
(Port D)
8-bit I/O port. I/O can be set in a
unit of single bits.
(8 pins)
FDP segment signal (anode
connection) outputs.
PE0/INT0/
EC0
Input/Input/Input
PE1/INT1/
EC1
Input/Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/Input
PE4/RMC
Input/Input
PE5/CINT
Input/Input
External capture input for 16-bit
timer/counter.
PE6/PWM
Output/Output
14-bit PWM output.
PE7/TO/
ADJ
Output/Output/
Output
Output for the 16-bit timer/counter
rectangular waves, and 32kHz
oscillation frequency division.
PC0/KR0
to
PC7/KR7
(Port E)
8-bit port. Lower 6 bits are for
inputs; upper 2 bits are for
outputs.
(8 pins)
–4–
Inputs for
external
interruption
request.
(4 pins)
External event inputs
for timer/counter.
(2 pins)
Non-maskable
interruption request input.
Remote control reception circuit input.
CXP820P60
Symbol
I/O
Functions
I/O/Output
(Port F)
8-bit output port. I/O can be set
in a unit of single bits.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
PG0/A39
to
PG7/A32
Output/Output
(Port G)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
PH0/A31
to
PH7/A24
Output/Output
(Port H)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
PI0
Input
PI1
Input
PI2/TX
Input
PI3/TEX
Input/Input
A16 to A23
Output
FDP segment signal (anode connection) outputs.
(8 pins)
G0/A0
to
G15/A15
Output/Output
Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)
PF0/A47
to
PF7/A40
Input
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Input
Low-level active, system reset.
XTAL
RST
Crystal connectors for 32kHz timer/counter clock
oscillation. For usage as event counter, input to TEX,
and leave TX open.
FDP voltage supply for incorporated pull-down (PD) resistor.
VFDP
EXTAL
(Port I)
4-bit input port.
(4 pins)
Vpp
Vcc supply for incorporated PROM writing.
Leave this pin open during normal operation.
VDD
Positive power supply.
VSS
GND.
–5–
CXP820P60
I/O Circuit Format for Pins
Pin
After a reset
Circuit format
Port A
∗
Pull-up registor
"0" after a reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
Input protection circuit
Hi-Z
"0" after a reset
Internal
data bus
RD (Port A)
Port A input selecton
Input multiplexer
"0" after a reset
A/D converter
8 pins
∗ Pull-up transistor approx. 100kΩ
Port B
∗
Pull-up registor
"0" after a reset
TxD
UART output selection
"0" after a reset
PB0/TxD
Hi-Z
Port B data
IP
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
1 pin
∗ Pull-up transistor approx. 100kΩ
Port B
∗
Pull-up registor
"0" after a reset
Port B data
PB1/CS0/RxD
PB3/SI0
PB6/SI1
Port B direction
IP
"0" after a reset
Schmitt input
Internal
data bus
RD (Port B)
3 pins
CS0
SI0
SI1
RxD
∗ Pull-up transistor approx. 100kΩ
–6–
Hi-Z
CXP820P60
Pin
Circuit format
After a reset
Port B
∗
Pull-up registor
"0" after a reset
SCK OUT
Serial clock output enable
Port B output selecton
PB2/SCK0
PB5/SCK1
"0" after a reset
Hi-Z
Port B data
IP
Port B direction
"0" after a reset
Schmitt input
Internal
data bus
RD (Port B)
2 pins
∗ Pull-up transistor approx. 100kΩ
SCK IN
Port B
∗
Pull-up registor
"0" after a reset
SO
Serial data output enable
PB4/SO0
PB7/SO1
Port B outputput selecton
"0" after a reset
Hi-Z
Port B data
IP
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
2 pins
∗ Pull-up transistor approx. 100kΩ
Port C
∗2
Pull-up registor
"0" after a reset
Port C data
PC0/KR0
to
PC7/KR7
∗1
Port C direction
IP
"0" after a reset
Internal
data bus
8 pins
RD (Port C)
Key input signal
∗1 Large current 12mA
∗2 Pull-up transistor approx. 100kΩ
–7–
Hi-Z
CXP820P60
Pin
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CINT
Circuit format
After a reset
Port E
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
CINT
Schmitt input
IP
Hi-Z
Internal data bus
6 pins
RD (Port E)
Port E
PWM
Port E output selecton
"0" after a reset
PE6/PWM
High level
Port E data
Output enable
"1" after a reset
Internal
data bus
RD (Port E)
1 pin
Port E
Internal reset signal
00
Port E data
"1" after a reset
TO
ADJ16K∗1
ADJ2K∗2
PE7/TO/ADJ
01
10
11
MPX
∗2
Port E output selecton (upper)
Port E output selecton (lower)
∗1 ADJ signal is a frequency dividing output
"00" after a reset
High level
(High level at
ON resistance
of pull-up
transistor
during a reset)
for 32kHz oscillation frequency adjustment.
ADJ2K can be used for buzzer output.
TO output enable
∗2 Pull-up transistor approx. 150kΩ
1 pin
Port D
Port F
PD0/A55
to
PD7/A48
PF0/A47
to
PF7/A40
Segment output data
∗
Output selection control signal
("0" after a reset)
Port D and F data
Hi-Z
IP
Port D and F direction
"1" after a reset
Internal
data bus
RD (Port D and F)
∗
∗ High voltage drive transistor
16 pins
–8–
CXP820P60
Pin
After a reset
Circuit format
Port G
Segment output data
Port H
PG0/A39
to
PG7/A32
PH0/A31
to
PH7/A24
∗
Output selection control signal
("0" after a reset)
Port G and H data
Hi-Z
"0" after a reset
∗ High voltage drive transistor
Internal
data bus
16 pins
RD (Port G and H)
Segment output data
A16 to A23
∗
Output selection control signal
("0" after a reset)
Pull-down registor
VFDP
∗ High voltage drive transistor
8 pins
G0/A0
to
G15/A15
Segment output data
Timing output data
∗
Hi-Z or Low
level (when
PD resistor is
connected)
Output selection control signal
("0" after a reset)
Pull-down registor
VFDP
16 pins
EXTAL
XTAL
2 pins
PI0
PI1
2 pins
Hi-Z or Low
level (when
PD resistor is
connected)
∗ High voltage drive transistor
EXTAL
IP
IP
• Diagram shows circuit
composition during
oscillation.
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
XTAL
Internal data bus
IP
RD (Port I)
–9–
Oscillation
Hi-Z
CXP820P60
Pin
After a reset
Circuit format
TEX oscillation circuit control
PI2/TX
PI3/TEX
2 pins
AA
AA
AA
PI3/TEX
A
A
IP
IP
"1" after a reset
Internal
data bus
RD
Internal
data bus
RD
Clock input
Oscillation
stop port
input
PI2/TX
Pull-up registor
RST
Low level
IP
1 pin
Schmitt input
– 10 –
CXP820P60
Absolute Maximum Ratings
Item
Supply voltage
(Vss = 0V reference)
Symbol
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
–0.3 to +13.0
–40∗2 to +7.0∗1
V
FDP display supply voltage VFDP
Remarks
Incorporated PROM
V
Input voltage
VIN
Output voltage
VOUT
–0.3 to +7.0∗1
–0.3 to +7.0∗1
Display output voltage
VOD
–40∗2 to +7.0∗1
V
IOH
–5
mA
All pins excluding display outputs∗3
(value per pin)
IODH1
–15
mA
Display outputs A20 to A55 (value per pin)
IODH2
–50
mA
Display outputs G0/A0 to G15/A15, and
A16 to A19 (value per pin)
∑IOH
–30
mA
Total for all pins excluding display outputs
∑IODH
–120
mA
Total for all display outputs
IOL
15
mA
IOLC
20
mA
Pins excluding large current output
(value per pin)
Large current output pins∗4 (value per pin)
Low level total output current ∑IOL
100
mA
Total for all output pins
High level output current
High level total output
current
Low level output current
V
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
600
mW
Allowable power dissipation PD
∗1
∗2
∗3
∗4
VIN, VOUT and VOD must not exceed VDD + 0.3V.
VFDP and VOD must not exceed VDD – 40V.
Specifies output current of general-purpose I/O ports.
The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 11 –
CXP820P60
Recommended Operating Conditions
Item
Supply voltage
High level input
voltage
Symbol
Min.
Max.
Unit
4.5
5.5
V
Guaranteed operation range during
1/2, 1/4 frequency dividing clock modes
3.5
5.5
V
Guaranteed operation range during
1/16 frequency dividing clock or sleep
modes
2.7
5.5
V
Guaranteed operation range with TEX
clock
2.5
5.5
V
VIH
0.7VDD
VDD
V
Guaranteed data hold range during stop
∗1
VIHS
0.8VDD
VDD
V
∗2
VIHH
0.7VDD
VDD
V
∗3
VDD
Operating temperature
Remarks
VIL
0
0.3VDD
V
EXTAL∗4
∗1
VILS
0
0.2VDD
V
∗2
VILH
0
0.7
V
∗3
VILEX
–0.3
0.4
V
EXTAL∗4
Topr
–20
+75
°C
VIHEX
Low level input
voltage
(Vss = 0V reference)
VDD – 0.4 VDD + 0.3
V
∗1 Value for each pin of normal input port (PA, PB0, PB4, PB7, PC).
∗2 Value of the following pins:
RST, CINT, CS0/RxD, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC.
∗3 Value for each pin (PD, PF).
∗4 Specifies only during external clock input.
– 12 –
CXP820P60
Electrical Characteristics
DC Characteristics
Item
High level
output current
Low level
output current
(Ta = –20 to +75°C, VSS = 0V reference)
Symbol
VOH
VOL
Pins
IIHT
Input current
IILT
VDD = 4.5V, IOH = –1.2mA
3.5
V
PA to PC,
PE6, PE7
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
PC
VDD = 4.5V, IOL = 12.0mA
1.5
V
EXTAL
TEX
PA to PC∗1
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–50
µA
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
A20 to A55
Pull-down
resistance
RL
I/O leakage
current
IIZ
Unit
V
IIL
ILOL
Max.
4.0
RST
Open drain
output leakage
current (P-CH
Tr off state)
Typ.
VDD = 4.5V, IOH = –0.5mA
IILR
Display output
IOH
current
Min.
PA to PD, PE6,
PE7, PF to PH
IIHE
IILE
Conditions
G0/A0 to
G15/A15,
A16 to A19
VDD = 4.5V
VOH = VDD – 2.5V
G0/A0 to
G15/A15,
A16 to A55
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
G0/A0 to
G15/A15,
A16 to A23
PA to PC∗1,
PD∗2,
PE0 to PE5,
PF∗2, PI
VDD = 5V
VOD – VFDP = 30V
VDD = 5.5V
VI = 0, 5.5V
– 13 –
–3.3
µA
–8
mA
–30
mA
30
70
–20
µA
220
kΩ
±10
µA
CXP820P60
Item
Symbol
Pins
Conditions
1/2 frequency dividing clock mode
operation
IDD1
Min.
Typ.
Max.
Unit
27
55
mA
35
110
µA
1.5
8
mA
15
30
µA
10
µA
20
pF
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDD2
Supply
current∗3
Input
capacity
IDDS1
VDD
Sleep mode
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
IDDS2
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS3
Stop mode
VDD = 5.5V, termination of 16MHz
and 32kHz oscillation
CIN
PA to PC,
PD∗2,
Clock 1MHz
PE0 to PE5,
0V for all pins excluding
PF∗2, PI,
measured pins
EXTAL,
RST
10
∗1 PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.
∗2 PD and PF pins specify when they are used as input pins by program.
∗3 When all pins are open.
– 14 –
CXP820P60
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
System clock frequency
fC
Event count input clock
rise time, fall time
tXL
tXH
tCR
tCF
tEH
tEL
tER
tEF
System clock frequency
fC
System clock input pulse width
System clock input rise time,
fall time
Event count input clock
pulse width
Event count input pulse width
Event count input rise time,
fall time
Pin
tTL
tTH
tTR
tTF
Conditions
Typ.
Min.
XTAL
EXTAL
Fig. 1, Fig. 2
1
EXTAL
Fig. 1, Fig. 2
External clock drive
28
EXTAL
Fig. 1, Fig. 2
External clock drive
tsys + 50∗1
EC0,
EC1
Fig. 3
EC0,
EC1
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Max.
Unit
16
MHz
ns
200
ns
ns
20
32.768
ms
kHz
10
µs
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control
clock register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 1. Clock timing
AAAA
AAAA
AAAA
AAAAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 2. Clock applied conditions
0.8VDD
TEX
EC0
EC1
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 3. Event count clock timing
– 15 –
tER
tTR
CXP820P60
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
float delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
float delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0 High level width
tWHCS CS0
Chip select transfer mode
SCK0 cycle time
tKCY
SCK0
tKH
tKL
SCK0
SI0 input setup time
(for SCK0 ↑)
tSIK
SI0
SI0 input hold time
(for SCK0 ↑)
tKSI
SI0
SCK0 ↓ → SO0
delay time
tKSO
SO0
SCK0 High, Low level width
tsys + 200
2tsys + 200
ns
16000/fc
ns
Input mode
tsys + 100
ns
Output mode
8000/fc – 50
ns
SCK0 input mode
100
ns
SCK0 output mode
200
ns
tsys + 200
ns
100
ns
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
tsys + 200
ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 16 –
CXP820P60
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
Fig. 4. Serial transfer CH0 timing
– 17 –
CXP820P60
Serial transfer (CH1)
Item
SCK1 cycle time
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
tKCY
Pin
Condition
SCK1
SCK1
High, Low level width
tKH
tKL
SCK1
SI1 input setup time
(for SCK1 ↑)
tSIK
SI1
SI1 input hold time
(for SCK1 ↑)
tKSI
SCK1 ↓ → SO1 delay time
tKSO
SI1
SO1
Min.
Max.
Input mode
1000
ns
Ouput mode
16000/fc
ns
Input mode
400
ns
Ouput mode
8000/fc – 50
ns
SCK1 input mode
100
ns
SCK1 ouput mode
200
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
SCK1 input mode
200
ns
SCK1 ouput mode
100
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
SI1
Unit
Input data
0.2VDD
tKSO
0.8VDD
SO1
Output dat
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 18 –
CXP820P60
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(3) A/D converter characteristics
Item
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale
transition voltage
VFT∗2
Conversion time
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Pin
Condition
Ta = 25°C
VDD = 5.0V
VSS = 0V
Min.
Typ.
–10
10
70
mV
4910
4970
5030
mV
26/fADC∗3
6/fADC∗3
AN0 to AN7
0
µs
µs
VDD
V
Digital conversion value
FFh
FEh
Linearity error
01h
00h
VFT
VZT
Analog input
∗1 VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
∗3 fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control register (ADC: 00F9h) and bits 7
(PCK1) and 6 (PCK0) of the clock control register (CLC:
00FEh).
However, the selection for fADC = fC (CKS = "0") is limited in
the clock range of fC = 1 to 14MHz (VDD = 4.5 to 5.5V).
Fig. 6. Definition of A/D converter terms
– 19 –
CXP820P60
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
Condition
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
NMI/INT3
Reset input Low level width
tRSL
RST
tIH
Min.
Max.
Unit
1
µs
32/fc
µs
tIL
0.8VDD
INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge.)
0.2VDD
tIL
tIH
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
– 20 –
CXP820P60
Appendix
AAAA
AAAA
AAAA
AAAA
EXTAL
AAAA
AAAA
(ii) Main clock
(i) Main clock
EXTAL
XTAL
Rd
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
Rd
C2
C1
XTAL
TX
C2
C1
C1 C2
Fig. 9. Recommended oscillation circuit
Manufacturer
MURATA
MFG
CO., LTD.
RIVER ELETEC
CO., LTD
KINSEKI
LTD.
CSA10.0MTZ
10.0
CSA12.0MTZ
12.0
CSA16.00MXZ040
CST10.0MTW∗
16.0
C1 (pF)
C2 (pF)
30
30
5
5
30
30
10.0
CST16.00MXW0C1∗
16.0
5
5
8.0
18
18
12.0
12
12
16.0
10
10
8.0
10
10
12.0
5
5
16.0
Open
Open
32.768kHz
18
18
VTC-200
SP-T
Circuit
example
Remarks
0
12.0
HC-49/U03
Rd (Ω)
(i)
CST12.0MTW∗
HC-49/U (-S)
Seiko Instruments
Inc.
fc (MHz)
Model
(ii)
330
(i)
0
330k
(iii)
CL = 12.5pF
Models marked with an asterisk (∗) have the built-in ground capacitance (C1, C2).
Mask Option Table
Item
Package
Mask ROM
CXP820P60Q-1-
100-pin plastic QFP
100-pin plastic QFP
52K/60K byte
PROM 60K byte
Reset pin pull-up resistor
Existent/Non-existent
Existent
High voltage drive pin
pull-down resistor
Existent/Non-existent
Non-existent (PH7/A24 to PD0/A55)
Existent (G0/A0 to A23)
ROM capacitance
– 21 –
CXP820P60
Characteristics Curve
IDD vs. VDD
IDD vs. fc
100
25
1/2 dividing mode
1/2 dividing mode
1/4 dividing mode
20
1/16 dividing mode
Sleep mode
1
0.1
IDD – Supply current [mA]
IDD – Supply current [mA]
10
15
1/4 dividing mode
10
32kHz mode
5
1/16 dividing mode
32kHz
Sleep mode
Sleep mode
0.01
0
0
1
2
3
4
5
6
7
0
VDD – Supply voltage [V]
5
10
fc – System clock [MHz]
– 22 –
15
20
CXP820P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 23 –