CXP86609/86613/86617 CMOS 8-bit Single Chip Microcomputer Description The CXP86609/86613/86617 are the CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, I2C bus interface, PWM output, remote control reception circuit, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP86609/86613/86617 also provide a sleep function that enables to lower the power consumption. 52 pin SDIP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit operation/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM 8K bytes (CXP86609) 12K bytes (CXP86613) 16K bytes (CXP86617) • Incorporated RAM 352 bytes • Peripheral functions — A/D converter 8 bits, 6 channels, successive approximation method (Conversion time of 3.25µs at 16MHz) — Serial interface 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32kHz timer/counter — I2C bus interface — PWM output 8 bits, 4 channels — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — Watchdog timer • Interruption 11 factors, 11 vectors, multi-interruption possible • Standby mode Sleep • Package 52-pin plastic SDIP • Piggyback/evaluator CXP86490 64-pin ceramic PSDIP Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97751-PS SERIAL INTERFACE UNIT 8 BIT TIMER/ COUNTER 0 8 BIT TIMER 1 SI SO SCK EC TO FIFO 2 I2C BUS INTERFACE UNIT SDA0 REMOCON INTERRUPT CONTROLLER INT0 INT1 INT2 SDA1 RMC SCL0 A/D CONVERTER SCL1 6 2 ADJ AN0 to AN5 RAM 352 BYTES ROM 8K/12K/16K BYTES 4 8 BIT PWM 32kHz TIMER/COUNTER WATCHDOG TIMER PRESCALER/ TIME BASE TIMER CLOCK GENERATOR /SYSTEM CONTROL TEX TX EXTAL XTAL RST VDD VSS SPC700 CPU CORE PWM0 to PWM3 PORT A PORT B PORT D PORT E PORT F –2– PORT G Block Diagram PF4 to PF7 4 PG7 PF0 to PF3 4 1 PE4 to PE6 PE0 to PE1 2 PE2 to PE3 PD0 to PD7 8 3 PB0 to PB7 8 2 PA0 to PA7 8 CXP86609/86613/86617 CXP86609/86613/86617 Pin Assignment (Top View) PD7/EC 1 52 PF0/PWM0 PD6/RMC 2 51 PF1/PWM1 PD5 3 50 PF2/PWM2 PD4 4 49 PF3/PWM3 PD3/SI 5 48 PF4/SCL0 PD2/SO 6 47 PF5/SCL1 PD1/SCK 7 46 PF6/SDA0 PD0/INT2 8 45 PF7/SDA1 PA7 9 44 PE0/TO/ADJ PA6 10 43 PE1 RST 11 42 PE2/TEX/INT0 VSS 12 41 PE3/TX XTAL 13 40 VSS EXTAL 14 39 VDD PA5/AN5 15 38 NC PA4/AN4 16 37 NC PA3/AN3 17 36 NC PA2/AN2 18 35 PE4 PA1/AN1 19 34 PE5 PA0/AN0 20 33 PE6 PB7 21 32 NC PB6 22 31 NC PB5 23 30 NC PB4 24 29 PB0 PB3 25 28 PB1 PG7/INT1 26 27 PB2 Note) 1. NC (Pins 30, 31, 32, 36 and 38) are left open. 2. Vss (Pins 12 and 40) are both connected to GND. 3. Pin 37 is the NC pin. However, connect it to VDD because it is the EXLC pin (input) for the piggyback/evaluator and OTP devices. –3– CXP86609/86613/86617 Pin Description Symbol I/O Description PA0/AN0 to PA5/AN5 I/O/ Analog input PA6 to PA7 I/O PB0 to PB7 I/O PD0/INT2 I/O/Input PD1/SCK I/O/I/O PD2/SO I/O/Output PD3/SI I/O/Input PD4 to PD5 I/O PD6/RMC I/O/Input PD7/EC I/O/Input External event input for timer/counter. PE0/TO/ADJ I/O/Output/ Output Rectangular wave output for 8-bit timer/counter. PE1 I/O PE2/TEX/INT0 Input/Input/ Input PE3/TX Input/Output PE4 to PE6 Output (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Analog inputs to A/D converter. (6 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. (8 pins) (Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins) –4– Serial clock I/O. Serial data output. Serial data input. Remote control reception circuit input. 32kHz oscillation frequency dividing output. Connects a crystal for External interruption request input. Active at 32kHz timer/counter the falling edge. clock oscillation. When used as an event counter, input to TEX pin and leave TX pin open. CXP86609/86613/86617 Symbol I/O PF0/PWM0 to PF3/PWM3 Output/Output PF4/SCL0 to PF5/SCL1 Output/I/O PF6/SDA0 to PF7/SDA1 Output/I/O Description (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium voltage drive (12V); upper 4 bits are 5V drive. (8 pins) 8-bit PWM output. (4 pins) I2C bus interface transfer clock I/O. (2 pins) I2C bus interface transfer data I/O. (2 pins) (Port G) 1-bit I/O port. I/O can be set in a unit of single bits. (1 pin) External interruption request input. Active at the falling edge. PG7/INT1 I/O/Input EXTAL Input XTAL Output Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin. RST Input System reset; active at Low level. NC No connected. Connect this pin to VDD under normal operation. VDD Positive power supply. Vss GND. Connect two Vss pins to GND. –5– CXP86609/86613/86617 Input/Output Circuit Formats for Pins Pin Circuit format After reset Port A Port A data Port A direction PA0/AN0 to PA5/AN5 "0" after reset IP Data bus Hi-Z Input protection circuit RD (Port A) Port A function selection "0" after reset A/D converter Input multiplexer 6 pins Port A Port A data PA6 PA7 Port A direction "0" after reset Hi-Z Schmitt input Data bus IP RD (Port A) 2 pins Port B Ports B, G data Port G Ports B, G direction PB0 to PB7 PG7/INT1 "0" after reset Schmitt input only for PG7 Data bus RD (Ports B, G) 9 pins INT1 –6– Hi-Z IP CXP86609/86613/86617 Pin Circuit format After reset Port D Port D data PD0/INT2 PD3/SI PD6/RMC PD7/EC Port D direction ∗ "0" after reset Hi-Z Schmitt input Data bus IP RD (Port D) 4 pins ∗ Large current 12mA INT2, SI, RMC, EC Port D SCK, SO SIO output enable Port D data PD1/SCK PD2/SO ∗ Port D direction Hi-Z "0" after reset IP Schmitt input only for PD1 Data bus RD (Port D) 2 pins ∗ Large current 12mA SCK only Port D Port D data Port D direction PD4 PD5 ∗ "0" after reset Hi-Z Schmitt input Data bus IP RD (Port D) ∗ Large current 12mA 2 pins –7– CXP86609/86613/86617 Pin Circuit format After reset Port E Internal reset signal Port E data 00 "1" after reset TO ∗1 ADJ16K ∗1 ADJ2K PE0/TO/ADJ 01 10 11 MPX ∗2 Port E function selection (upper) Port E function selection (lower) ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency IP adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up transistor approx. 150kΩ "00" after reset Port E direction "1" after reset Data bus 1 pin High level (with the resistor of pull-up transistor ON when reset) RD (Port E) Port E Port E data "1" after reset PE1 Port E direction High level "1" after reset IP Data bus RD (Port E) 1 pin Port E 32kHz oscillation circuit control "1" after reset Schmitt input INT0 Data bus RD (Port E) PE2/TEX/INT0 PE3/TX Data bus PE2/ TEX/ INT0 2 pins RD (Port E) Schmitt input IP IP PE3/ TX –8– Clock input Oscillation stop Port input CXP86609/86613/86617 Pin Circuit format After reset Port E PE4 PE5 PE6 Port E data Hi-Z Output becomes active from high impedance by data writing to port register. Data bus 3 pins RD (Port E) Port F PWM0 to PWM3 Port F function selection PF0/PWM0 to PF3/PWM3 ∗ "0" after reset Hi-Z Port F data "1" after reset Data bus 4 pins ∗ 12V drive Large current 12mA RD (Port F) Port F SCL, SDA I2C output enable PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 ∗ Port F data "1" after reset Hi-Z Schmitt input SCL, SDA (I2C circuit) IP BUS SW 4 pins EXTAL XTAL 2 pins ∗ Large current 12mA EXTAL To internal I2C pins (SCL1 for SCL0) IP • Diagram shows the circuit composition during oscillation. • Feedback resistor is removed during stop. (This device does not enter the stop mode.) XTAL Oscillation Pull-up resistor RST 1 pin AA AA Mask option OP Schmitt input –9– Low level (when reset) CXP86609/86613/86617 Absolute Maximum Ratings Item (Vss = 0V reference) Symbol Ratings Unit V Supply voltage VDD Input voltage VIN –0.3 to +7.0 –0.3 to +7.0∗1 VOUT –0.3 to +7.0∗1 V –0.3 to +15.0 V Output voltage Medium drive output voltage VOUTP Remarks V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Ports excluding large current output (value per pin) Large current output ports (value per pin∗2) Low level total output current ∑IOL 130 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 375 mW Low level output current SDIP-52P-01 ∗1 VIN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage High level input voltage Symbol Min. Max. Unit 4.5 5.5 V Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks 3.5 5.5 V Guaranteed operation range for 1/16 frequency dividing clock or sleep mode 2.7 5.5 V — — V Guaranteed operation range for TEX Guaranteed data hold range for stop∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V ∗3 V VDD Operating temperature ∗1 ∗2 ∗3 ∗4 ∗5 Remarks VIL 0 0.3VDD V EXTAL pin∗4, TEX pin∗5 ∗2 VILS 0 0.2VDD V ∗3 VILEX –0.3 0.4 V EXTAL pin∗4, TEX pin∗5 Topr –20 +75 °C VIHEX Low level input voltage (Vss = 0V reference) VDD – 0.4 VDD + 0.3 This device does not enter the stop mode. PA0 to PA5, PB0 to PB7, PD2, PE0, PE1, PE3, SCL0, SCL1, SDA0, SDA1 pins PA6, PA7, INT2, SCK, SI, PD4, PD5, RMC, EC, INT0, INT1, RST pins Specifies only during external clock input. Specifies only during external event count input. – 10 – CXP86609/86613/86617 Electrical Characteristics (Ta = –20 to +75°C, Vss = 0V reference) DC characteristics Item High level output voltage Low level output voltage Symbol VOH VOL Pins PA, PB, PD, PE0 to PE1, PE4 to PE6, PG7 Input current IIHT IILT I/O leakage current Min. Typ. Max. Unit VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V PA, PB, PD, VDD = 4.5V, IOL = 1.8mA PE0 to PE1, PE4 to PE6, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, PG7 0.4 V 0.6 V PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) VDD = 4.5V, IOL = 3.0mA 0.4 V VDD = 4.5V, IOL = 4.0mA 0.6 V IIHE IILE Conditions EXTAL TEX VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA IILR RST∗1 VDD = 5.5V, VIL = 0.4V IIZ PA, PB, PD, PE, PG7, RST∗1 VDD = 5.5V, VI = 0, 5.5V ±10 µA PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA SCL0: SCL1 SDA0: SDA1 VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 120 Ω 18 28 mA 30 80 µA 1.2 2.1 mA 12 35 µA — — µA Open drain I/O ILOH leakage current (in N-ch Tr off state) I2C bus switch connection impedance RBS (in output Tr off state) 1/2 frequency dividing clock operation IDD1 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) IDD2 Supply current∗2 Sleep mode IDDS1 IDDS2 IDDS3 VDD VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, 32MHz crystal oscillation (C1 = C2 = 47pF) Stop mode∗3 VDD = 5.5V, termination of 16MHz and 32MHz oscillation – 11 – — CXP86609/86613/86617 Item Input capacitance Symbol CIN Pins Conditions PA, PB, PD, Clock 1MHz PE0 to PE3, PF4 to PF7, 0V for no measured pins PG7, EXTAL, TEX, RST Min. Typ. Max. Unit 10 20 pF ∗1 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. ∗2 When all output pins are left open. ∗3 This device does not enter the stop mode. – 12 – CXP86609/86613/86617 AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency fC tXL, tXH System clock input rise and fall tCR, times tCF Event count input clock pulse tEH, width tEL Event count input clock rise and tER, fall times tEF System clock input pulse width System clock frequency fC tTL, tTH Event count input clock rise and tTR, fall times tTF Event count input clock input pulse width Pins Conditions Min. XTAL EXTAL Fig. 1, Fig. 2 8 EXTAL Fig. 1, Fig. 2 External clock drive 28 EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied conditions) TEX Fig. 3 TEX Fig. 3 Typ. Max. Unit 16 MHz ns 200 4tsys∗1 ns ns 20 ms kHz 32.768 µs 10 20 ms ∗1 Indicates three values according to the contents of the clock control register (CLC: 00 FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 1. Clock timing AAAA AAAAA AAAA AAAAAAAAAAAAA Crystal oscillation Ceramic oscillation EXTAL C1 External clock EXTAL XTAL C2 32kHz clock applied condition Crystal oscillation TEX XTAL 74HC04 TX C1 C2 Fig.2. Clock applied conditions 0.8VDD TEX EC 0.2VDD tEH tTH tEF tTF tEL tTL Fig. 3. Event count clock timing – 13 – tER tTR CXP86609/86613/86617 (2) Serial transfer Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins tKCY SCK SCK High and Low level width tKH tKL SCK SI input setup time (for SCK ↑) tSIK SI SI hold time (for SCK ↑) tKSI SI SCK ↓ → SO delay time tKSO SO SCK cycle time Conditions Min. Input mode Max. 1000 ns 8000/fc ns 400 ns 4000/fc – 50 ns SCK input mode 100 ns SCK output mode 200 ns SCK input mode 200 ns SCK output mode 100 ns Output mode SCK input mode SCK output mode SCK input mode 200 ns SCK output mode 100 ns Note) The load of SCK output mode and SO output delay time is 50 pF + 1TTL. tKCY tKL tKH 0.8VDD SCK 0.2VDD tSIK tKSI 0.8VDD Input data SI Unit 0.2VDD tKSO 0.8VDD SO Output data 0.2VDD Fig. 4. Serial transfer timing – 14 – CXP86609/86613/86617 (3) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Max. Unit Resolution 8 Bits Linearity error ±3 LSB Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time Sampling time tCONV tSAMP Analog input voltage VIAN Pins Conditions Ta = 25°C VDD = 5.0V Vss = 0V Min. Typ. –10 10 70 mV 4910 4970 5030 mV 26/fADC∗3 6/fADC∗3 AN0 to AN5 FFh FEh 0 µs VDD V Digital conversion value ∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F6h): Linearity error fADC = fc (CKS = "0"), fc/2 (CKS = "1") 01h 00h µs VZT VFT Analog input Fig. 5. Definitions of A/D converter terms – 15 – CXP86609/86613/86617 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins Conditions Min. Max. Unit External interruption High, Low level width tIH tIL INT0 INT1 INT2 1 µs Reset input Low level width tRSL RST 32/fc µs tIH tIL INT0 INT1 INT2 (falling edge) 0.8VDD 0.2VDD Fig. 6. Interruption input timing tRSL RST 0.2VDD Fig. 7. RST input timing – 16 – CXP86609/86613/86617 (5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 0 100 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 4.7 µs SDA, SCL 4.0 µs SCL 4.7 µs SCL 4.0 µs SDA, SCL µs SDA, SCL 4.7 0∗1 SDA, SCL 250 ns Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 1 µs SDA, SCL 300 ns SDA, SCL 4.7 µs ∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH St tSU; DAT tSU; STO P Fig. 8. I2C bus transfer timing I2C device RS I2C device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 9. I2C device recommended circuit • A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 17 – CXP86609/86613/86617 Appendix AAAA AAAA AAAA (i) Main clock EXTAL XTAL Rd C1 C2 AAAA AAAAA AAAA AAAAA AAAA AAAAA AA A A (ii) Main clock EXTAL (iii) Sub clock TEX XTAL Rd TX Rd C2 C1 C1 C2 Fig. 10. Recommended oscillation circuit Manufacture Model MURATA MFG CO., LTD. fc (MHz) CSA10.0MTZ 10.0 CSA12.0MTZ 12.0 CSA16.00MXZ040 CST10.0MTW∗ 16.0 10.0 C1 (pF) C2 (pF) 30 30 5 5 30 30 12.0 CST16.00MXW0C1∗ 16.0 5 5 8.0 18 18 12.0 12 12 16.0 10 10 8.0 10 10 12.0 5 5 16.0 Open Open 32.768kHz 30 33 HC-49/U (-S) KINSEKI LTD. P3 Circuit example (i) CST12.0MTW∗ RIVER ELETEC HC-49/U03 CORPORATION Rd (Ω) 0 ∗1 (ii) 330 ∗1 (i) 0 ∗1 120k (iii) ∗Models with an asterisk have the built-in ground capacitance (C1, C2). ∗1 The series resistor for XTAL can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Reset pin pull-up resistor Content Non-existent – 18 – Existent CXP86609/86613/86617 IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical) 100 1/2 dividing mode 1/4 dividing mode 15 1/16 dividing mode Sleep mode 1 0.1 32kHz operation mode IDD – Supply current [mA] IDD – Supply current [mA] 10 1/2 dividing mode 10 1/4 dividing mode 5 32kHz sleep mode 1/16 dividing mode 0.01 Sleep mode 1 2 3 4 5 6 7 0 0 VDD – Supply voltage [V] 5 10 fc – System clock [MHz] Fig. 11. Characteristic curves – 19 – 15 CXP86609/86613/86617 Package Outline Unit: mm + 0.1 .05 0.25 – 0 52PIN SDIP (PLASTIC) + 0.4 47.0 – 0.1 15.24 + 0.3 13.5 – 0.1 27 52 0° to 15° 26 1 0.5 ± 0.1 + 0.1 0.9 – 0.05 5.0 MIN 2.8 MIN 0.51 MIN 1.778 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SDIP052-P-0600 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 5.6g JEDEC CODE – 20 –