CXP82712/82716
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82712/82716 microcomputer is composed
of a 8-bit CPU, ROM, RAM, and I/O ports. These
chips feature many other high-performance circuits
in a single-chip CMOS design, including an A/D
converter, serial interface, timer/counter, time base
timer, fluorescent display controller/driver, remote
control receiver, PWM output circuit and 32kHz
timer/counter.
This device also includes sleep/stop functions which
can be used to achieve low power consumption.
64 pin SDIP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Instruction set which supports a wide array of data types
— 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and
boolean bit operations.
• Minimum instruction cycle
400ns for 10MHz, 122µs for 32kHz operation
• On-chip ROM
12K bytes (CXP82712)
16K bytes (CXP82716)
• On-chip RAM
448 bytes (Including fluorescent display data area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation system
(conversion rate 32µs/10MHz)
— Serial interface
On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer),
1 circuit 2-channel
— Timers
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
— Fluorescent display controller/driver
24 high voltage tolerance output ports
Maximum of 144 segments display available
1 to 16 digits dynamic display
Dimmer function
High voltage tolerance output (40V)
On-chip pull-down resistor (Mask option)
Hardware key scan function (Maximum of 8 × 8 key matrix available)
— Remote control receiver circuit
On-chip 6-stage FIFO 8-bit pulse measurement counter
— PWM output
8-bit, 1-channel
• Interruption
13 factors, 13 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
64-pin plastic SDIP
• Piggyback/evaluator
CXP82700 64-pin ceramic SDIP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93Y23A79-PS
–2–
PE6/ADJ
PE6/TO
PE0/EC
PE5/PWM
FIFO
FIFO
RAM
80 BYTES
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
8 BIT PWM
SERIAL
INTERFACE
UNIT
PB1/CS0
PB3/SI0
PB4/SO0
PB2/SCK0
PB0/CS1
PB6/SI1
PB7/SO1
PB5/SCK1
FDP
CONTROLLER/
DRIVER
A/D CONVERTER
REMOCON
8
8
8
8
PE4/RMC
T0 to T7
T8/S28
to
T15/S21
S13 to S20
VFDP
PA0/AN0
to
PA7/AN7
2
PE0/INT0
PE1/INT1
PE2/INT2
PE3/INT3
PE3/NMI
2
PRESCALER/
TIME BASE TIMER
ROM
12K/16K BYTES
SPC700
CPU CORE
PH1/TEX
PH0/TX
EXTAL
XTAL
RST
VDD
Vss
32kHz
TIMER/COUNTER
RAM
448 BYTES
CLOCK GEN./
SYSTEM CONTROL
PB0 to PB7
8
8
PE5 to PE6
PF5 to PF7
2
3
2
PH0 to PH1
PE0 to PE4
6
PC0 to PC7
PA0 to PA7
8
PORT A
PORT B
PORT C
PORT E
PORT F
PORT H
INTERRUPT CONTROLLER
Block Diagram
CXP82712/82716
CXP82712/82716
Pin Assignment (Top View)
PH0/TX
1
64
VDD
PH1/TEX
2
63
PE5/PWM
NC
3
62
PE4/RMC
PE6/ADJ/TO
4
61
PE3/INT3/NMI
PB0/CS1
5
60
PE2/INT2
PB1/CS0
6
59
PE1/INT1
PB2/SCK0
7
58
PE0/EC/INT0
PB3/SI0
8
57
VFDP
PB4/SO0
9
56
T0
PB5/SCK1
10
55
T1
PB6/SI1
11
54
T2
PB7/SO1
12
53
T3
PC0/KR0
13
52
T4
PC1/KR1
14
51
T5
PC2/KR2
15
50
T6
PC3/KR3
16
49
T7
PC4/KR4
17
48
T8/S28
PC5/KR5
18
47
T9/S27
PC6/KR6
19
46
T10/S26
PC7/KR7
20
45
T11/S25
PA0/AN0
21
44
T12/S24
PA1/AN1
22
43
T13/S23
PA2/AN2
23
42
T14/S22
PA3/AN3
24
41
T15/S21
PA4/AN4
25
40
S20
PA5/AN5
26
39
S19
PA6/AN6
27
38
S18
PA7/AN7
28
37
S17
RST
29
36
S16
EXTAL
30
35
PF7/S15
XTAL
31
34
PF6/S14
Vss
32
33
PF5/S13
Note) 1. NC (Pin 3) is always connected to VDD.
2. PH0/TX (Pin 1) is input port during port selection;
oscillation output during oscillation selection
–3–
CXP82712/82716
Pin Description
Symbol
I/O
PA0/AN0
to
PA7/AN7
I/O/Analog Input
PB0/CS1
I/O/Input
PB1/CS0
I/O/Input
PB2/SCK0
I/O/I/O
PB3/SI0
I/O/Input
PB4/SO0
I/O/Output
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
Functions
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
Chip select input for serial interface (CH1).
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can
be set in a bit unit.
Capable of driving
12mA sink current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
PC0/KR0
to
PC7/KR7
I/O/Input
PE0/INT0/
EC0
Input/Input/
Input
PE1/INT1
Input/Input
PE2/INT2
Input/Input
PE3/INT3/
NMI
Input/Input/
Input
PE4/RMC
Input/Input
PE5/PWM
Output/Output
8-bit PWM output.
PE6/ADJ/TO
Output
Output for timer/counter rectangular waveform
and 32kHz oscillation frequency division.
(Port E)
Lower 5 bits are for
inputs; upper 2 bits are
for outputs.
(7 pins)
–4–
Key return input for FDP segment signal which
performs key scanning.
External interrupt
requests.
(4 pins)
External event input to
timer/counter. (1 pin)
Non-maskable interruption request input.
Input for remote control receiver circuit.
CXP82712/82716
Symbol
I/O
Functions
PF5/S13
to
PF7/S15
Output/Output
(Port F)
3-bit output port.
(3 pins)
S16 to S20
Output
Segment signal output for FDP.
T8/S28
to
T15/S21
Output/Output
Dual purpose output for FDP timing and segment signals.
T0 to T7
Output
Timing signal output for FDP.
Segment signal output for FDP.
Provides voltage for FDP when on-chip resistor is selected under mask option.
VFDP
EXTAL
Input
XTAL
Output
PH1/TEX
Input/Input
PH0/TX
Input/Output
RST
Input
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
(Port H)
2-bit input
port.
(2 pins)
Crystal connectors for 32kHz timer/counter clock
oscillation circuit. Connect a 32kHz crystal oscillator
between TEX and TX. For usage as event input, connect
clock oscillation source to TEX, and leave TX open.
System reset pin of active "L" level. RST is input pin.
NC
NC.
Under normal operating conditions, connect to VDD.
VDD
Vcc supply.
Vss
GND
–5–
CXP82712/82716
I/O Circuit Format for Pins
Pin
Port A
AAA
AAA
AAA
AAA
AAA
When reset
Circuit format
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
IP
"0" when reset
AAA
AAA
AAA
AAA
AAA
AAA
AAA
Data bus
Input protection
circuit
Hi-Z
RD (Port A)
Port A input
selection
"0" when reset
Input multiplexer
A/D converter
8 pins
Port B
∗ Pull-up transistors
approx. 100kΩ
∗
Pull-up resistor
"0" when reset
AA
AA
AA
Port B data
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
IP
"0" when reset
Schmitt input
Data bus
RD (Port B)
4 pins
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
CS0
CS1
SI0
SI1
∗ Pull-up transistors
approx. 100kΩ
∗
Pull-up resistor
"0" when reset
SCK OUT
Output enable
AA
AA
AA
Port B output
selection
"0" when reset
PB2/SCK0
PB5/SCK1
IP
Port B data
Port B direction
"0" when reset
Schmitt input
Data bus
RD (Port B)
2 pins
Hi-Z
SCK in
–6–
∗ Pull-up transistors
approx. 100kΩ
Hi-Z
CXP82712/82716
Pin
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
When reset
Circuit format
∗
Pull-up resistor
"0" when reset
SO
Output enable
AA
AA
AA
Port B output
selection
"0" when reset
PB4/SO0
PB7/SO1
IP
Port B data
Port B direction
Hi-Z
"0" when reset
Data bus
RD (Port B)
2 pins
Port C
∗ Pull-up transistors
approx. 100kΩ
AAA
AAA
AAA
AAA
AAA
∗2
Pull-up resistor
"0" when reset
AA
AA
AA
Port C data
PC0/KR0
to
PC7/KR7
∗1
Port C direction
"0" when reset
Data bus
IP
Hi-Z
RD (Port C)
Key input signal
8 pins
∗1 Large current drive of 12mA possible
∗2 Pull-up transistors approx. 100kΩ
Port E
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
5 pins
AA A
AA
EC/INT0
INT1
INT2
INT3/NMI
RMC
Schmitt input
IP
Data bus
RD (Port E)
–7–
Hi-Z
CXP82712/82716
Pin
When reset
Circuit format
Port E
AAA
AAA
AAA
AAA
PWM
Port E output
selection
PE5/PWM
AA
"0" when reset
Port E data
Output enable
"1" when reset
High level
Data bus
RD (Port E)
1 pin
Port H
AA
AAA
AA
AAA
AAA
AAA
AAA
Output enable
TO
ADJ16K
ADJ2K
PE6/TO/ADJ
MPX
Port E output
selection
Port E output
selection
"00" when reset
High level
High level with
150kΩ resistor
when reset
AA (
Port E output
selection
"0" when reset
Port E data
1 pin
)
∗ ADJ signals are frequency division outputs
"1" when reset
Data bus
RD (Port E)
for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.
Port F
∗ High voltage tolerance transistor
Segment output data
PF5/S13
to
PF7/S15
∗
Output selection control signal
("0" when reset)
AAA
A (
A
A
OP Mask option
Port F data
Pull-down
resistor
VFDP
Data bus
RD (Port F)
3 pins
–8–
Hi-Z or
Low level
When PD
resistor is
connected
)
CXP82712/82716
Pin
When reset
Circuit format
∗ High voltage tolerance transistor
S16 to S20
T15/S21
to
T8/S28
T0 to T7
Segment output data
∗
Output selection control signal
("0" when reset)
2 pins
(
OP Mask option
Pull-down
resistor
21 pins
EXTAL
XTAL
AA
AA
AA
AA
AA
AA
AA
AA
EXTAL
VFDP
A
AA
A AA
IP
IP
Hi-Z or
Low level
When PD
resistor is
connected
• Diagram shows circuit
construction for oscillation.
• During stop feedback
resistor is disconnected.
At this time XTAL pin
outputs "H" level.
Oscillation
XTAL
32kHz oscillation
circuit control
"1" when reset
Data
bus
PH1/TEX
PH0/TX
AA
AA
AA AA
AA
AA
PH2/TEX
2 pins
A
A
IP
IP
RD
Data
bus
RD
Clock
input
Oscillation
halted
port input
PH0/TX
Pull-up resistor
RST
AA
AA
AA
OP Mask option
1 pin
Low level
IP
–9–
Schmitt input
)
CXP82712/82716
Absolute Maximum Ratings
Item
(Vss = 0V)
Symbol
Rating
Unit
V
Remarks
Supply voltage
VDD
Input voltage
VIN
–0.3 to +7.0
–0.3 to +7.0∗1
Output voltage
VOUT
–0.3 to +7.0∗1
V
Display output voltage
VOD
VDD – 40 to VDD + 0.3
V
As P channel transistor is open drain,
VDD voltage is determined as standard.
IOH
–5
mA
Other than display output pins∗2: per pin
IODH1
–15
mA
Display output S13 to S20: per pin
IODH2
–35
mA
Display output T0 to T7,
T8/S28 to T15/S21: per pin
∑IOH
–40
mA
Total of pins other than display output pins
∑IODH
–100
mA
Total of display output pins
IOL
15
mA
Port 1 pin
IOLC
20
mA
Large current port∗3 : per pin
Low level total output current ∑IOL
100
mA
Entire pin total
High level output current
High level
total output current
Low level output current
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
1000
mW
∗1 VIN and VOUT must not exceed VDD + 0.3V.
∗2 Specifies output current of general-purpose I/O ports.
∗3 The large current drive transistor is an N-ch transistor of Port C (PC).
Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing
recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected.
– 10 –
CXP82712/82716
Recommended Operating Conditions
Item
Supply voltage
High level
input voltage
Symbol
(Vss = 0V)
Min.
Max.
Unit
4.5
5.5
V
High speed mode (1/2, 1/4 dividing clock)
guaranteed operation range
3.5
5.5
V
Low speed mode (1/16 dividing clock)
guaranteed operation range
2.7
5.5
V
Guaranteed operation range with TEX clock
2.5
5.5
V
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
VDD
VIHEX
VDD – 0.4 VDD + 0.3
Guaranteed data hold operation range
during stop
∗1
V
Hysteresis input∗2
EXTAL pin∗3
∗1
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Operating temperature Topr
–20
+75
°C
Low level
input voltage
Remarks
Hysteresis input∗2
EXTAL pin∗3
∗1 All regular input port (PA, PB4, PB7, PC, PH).
∗2 For pins RST, CS0, CS1, SCK0, SI0, SI1, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC.
∗3 Specifies only for external clock input.
– 11 –
CXP82712/82716
Electrical Characteristics
(Ta = –20 to +75°C, Vss = 0V)
DC Characteristics
Item
Symbol
High level
VOH
output voltage
Low level
output voltage VOL
Pin
PA, PB,
PC, PE5,
PE6
PC
IIHE
IILE
EXTAL
IIHT
Input current
IILT
IILR
IIH
IIL
TEX
RST∗1
PA to PC∗2
Condition
Min.
Typ.
Max.
Unit
VDD = 4.5V, IOH = –0.5mA
4.0
V
VDD = 4.5V, IOH = –1.2mA
3.5
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12.0mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
VDD = 5.5V, VIL = 0.4V
–1.5
–400
µA
VDD = 4.5V, VIH = 4.0V
3.3
µA
50
VDD = 5.5V, VIL = 0.4V
S13 to S20
VDD = 4.5V
VOH = VDD – 2.5V
Display
IOH
output current
S21/T15 to
S28/T8
T0 to T7
Open drain
output leak
current (P-CH
Tr off state)
ILOL
S13 to S20
S21/T15 to
S28/T8
T0 to T7
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
Pull-down
resistor∗3
RL
S13 to S20
S21/T15 to
S28/T8
T0 to T7
VDD = 5V
VFDP = VDD – 35V
Input/Output
leak current
IIZ
PA to PC∗2,
PE0 to PE4
RST∗2
VDD = 5.5V
VI = 0, 5.5V
µA
–8
mA
–20
mA
60
–20
µA
270
kΩ
±10
µA
20
40
mA
35
100
µA
1.2
8
mA
9
30
µA
10
µA
100
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDD2
Supply
current∗4
VDD
IDDS1
Sleep mode
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
IDDS2
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
IDDS3
Stop mode
VDD = 5.5V, 10MHz termination of
10MHz and 32kHz crystal oscillation.
– 12 –
CXP82712/82716
Item
Input
capacitance
Symbol
CIN
Pin
Pins other
than
S13 to S28,
T0 to T7,
PE5, PE6,
VDD, Vss,
VFDP
Codition
1MHz clock
0V for pins other than the
measured pins
Min.
Typ.
Max.
Unit
10
20
pF
∗1 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗2 Pins PA to PC specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.
∗3 Applies when the on-chip pull-down resistor is selected under the mask option.
∗4 All output pins are left open.
– 13 –
CXP82712/82716
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
System clock frequency
fC
Event count input clock
rise and fall time
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count input clock
input pulse width
tTL,
tTH
tTR,
tTF
System clock input pulse width
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
Pins
Conditions
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
External clock drive
EXTAL
Fig. 1, Fig. 2
External clock drive
EC
Fig. 3
EC
Fig. 3
TEX
TX
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
Min.
Typ.
1
Max.
Unit
10
MHz
ns
37.5
200
tsys + 50∗
ns
ns
20
ms
kHz
32.768
µs
10
20
ms
∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
AAAA
AAAA
AAAA
AAAAAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
C1
External clock
EXTAL
XTAL
C2
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
TX
C2
C1
Fig. 2. Clock applied conditions
0.8VDD
TEX
EC
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 3. Event count clock timing
– 14 –
tER
tTR
CXP82712/82716
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
(2) Serial transfer
Item
Symbol
CS0 ↓ → SCK0 (CS1 ↓ → SCK1)
delay time
tDCSK
CS0 ↑ → SCK0 (CS1 ↑ → SCK1)
float delay time
tDCSKF SCK0 Chip select transfer mode
CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time
tDCSO
CS0 ↑ → SO0 (CS1 ↑ → SO1)
float delay time
Pin
Condition
Min.
SCK0 Chip select transfer mode
(SCK1) (SCK0 (SCK1) = output mode)
Unit
1.5tsys + 200 ns
1.5tsys + 200 ns
(SCK1) (SCK0 (SCK1) = output mode)
SO0
(SO1)
Max.
Chip select transfer mode
1.5tsys + 200 ns
tDCSOF SO0
Chip select transfer mode
1.5tsys + 200 ns
CS0 (CS1) high level width
tWHCS CS0
Chip select transfer mode
SCK0 (SCK1) cycle time
tKCY
SCK0 (SCK1)
high and low level widths
(SO1)
tsys + 200
ns
SCK0 Input mode
(SCK1) Output mode
2tsys + 200
ns
16000/fc
ns
tKH
tKL
SCK0 Input mode
(SCK1) Output mode
tsys+100
ns
8000/fc – 50
ns
SI0 (SI1) input seup time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
100
ns
tSIK
SCK0 (SCK1) output mode
200
ns
SI0 (SI1) input hold time
(for SCK0 ↑ (SCK1 ↑) )
SI0
(SI1)
SCK0 (SCK1) input mode
tsys + 200
ns
tKSI
100
ns
SCK0 ↓ → SO0
(SCK1 ↓ → SO1) delay time
tKSO
SO0
(SO1)
SCK0 (SCK1) input mode
(CS1)
SCK0 (SCK1) output mode
SCK0 (SCK1) output mode
tsys + 200 ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
– 15 –
CXP82712/82716
tWHCS
CS0
(CS1)
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
(SCK1)
0.2VDD
tSIK
tKSI
0.8VDD
Input
data
SI0
(SI1)
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
(SO1)
Output data
0.2VDD
Fig. 4. Serial transfer timing
– 16 –
CXP82712/82716
(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V)
Item
Symbol
Max.
Unit
Resolution
8
Bits
Linearity error
±3
LSB
Zero transition
voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Conversion time
tCONV
tSAMP
Sampling time
Analog input voltage VIAN
Pin
Condition
Min.
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
Typ.
–10
70
150
mV
4930
5050
5120
mV
160/fADC∗3
12/fADC∗3
0
AN0 to AN7
µs
µs
VDD
Digital conversion value
FFH
FEH
∗1 VZT : Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT : Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the Bit6 (CKS) of
A/D control register (address: 00F9H) and the Bit7 (PCK1)
and Bit6 (PCK0) of clock control register (address: 00FEH)
Linearity error
01H
00H
VZT
VFT
Analog input
Fig. 5. Definition of A/D converter terms
CSK
0 (φ/2 selection)
1 (φ selection)
00 (φ = fEX/2)
fADC = fC/2
fADC = fC
01 (φ = fEX/4)
fADC = fC/4
fADC = fC/2
11 (φ = fEX/16)
fADC = fC/16
fADC = fC/8
PCK1, 0
– 17 –
V
CXP82712/82716
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
External interruption
high and low level widths
tIH
tIL
INT0
INT1
INT2
INT3
NMI
Reset input low level width
tRSL
RST
Condition
Min.
Max.
Unit
1
µs
32/fc
µs
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
NMI
(NMI is specified only for
the falling edge)
0.2VDD
tIL
tIH
Fig 6. Interruption input timing
tRSL
RST
0.2VDD
Fig. 7. RST input timing
– 18 –
CXP82712/82716
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Appendix
(i) Main clock
EXTAL
EXTAL
XTAL
Rd
(iii) Sub clock
EXTAL
TEX
XTAL
Rd
C2
C1
AAAA
AAAA
AAAA
(ii) Main clock
XTAL
TX
Rd
C2
C1
C1 C2
Fig. 8. Recommended oscillation circuit
Model
Manufacturer
MURATA
MFG
CO., LTD.
CSA4.19MG
4.19
CSA8.00MTZ
8.00
CSA10.0MTZ
10.00
CST4.19MGW∗
CST8.00MTW∗
CST10.0MTW∗
RIVER
ELETEC
HC-49/U03
CORPORATION
.
C1 (pF)
fc (MHz)
HC-49/U (-S)
P3
Rd (Ω)
Circuit
example
(i)
30
30
0
4.19
(ii)
8.00
10.00
4.19
12
8.00
12
0
10.00
(i)
4.19
KINSEKI
LTD.
C2 (pF)
27
27
10.00
20
20
32.768kHz
50
22
0
8.00
1M
(iii)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
Mask Option Table
Content
Item
Reset pin pull-up resistor
Non-existent
Existent
High tension proof pull-down resistor
Non-existent
Existent (selected every pin)
– 19 –
CXP82712/82716
Characteristics Curves
IDD vs. VDD
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
20.0
1/2 dividing mode
1/4 dividing mode
10.0
1/16 dividing mode
1/2 dividing mode
20
5.0
1.0
Sleep mode
0.5
0.1
(100µA)
0.05
(50µA)
32kHz mode
(instruction)
IDD – Supply current [mA]
IDD – Supply current [mA]
(fc = 10MHz, Ta = 25°C, Typical)
15
1/4 dividing mode
1/16 dividing mode
10
5
32kHz
Sleep mode
Sleep mode
0.01
(10µA)
3
6
2
4
5
VDD – Supply voltage [V]
7
0
– 20 –
5
10
fc – System clock [MHz]
15
CXP82712/82716
Package Outline
Unit: mm
+ 0.1
0.05
0.25 –
64PIN SDIP (PLASTIC)
+ 0.4
57.6 – 0.1
64
19.05
+ 0.3
17.1 – 0.1
33
1
0° to 15°
32
0.5 ± 0.1
0.9 ± 0.15
3.0 MIN
0.5 MIN
+ 0.4
4.75 – 0.1
1.778
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SDIP-64P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP064-P-0750
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
8.6g
JEDEC CODE
– 21 –