CXP88152/88160
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88152/88160 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, PWM for tuner, VISS/ VASS circuit, 32kHz
timer/counter, remote control receiving circuit,
fluorescent display panel (FDP) controller/driver,
VSYNC separator and the measurement circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Also, CXP88152/88160 provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity
52K bytes (CXP88152)
60K bytes (CXP88160)
• Incorporated RAM capacity
1296 bytes (including fluorescent display area)
• Peripheral function
— A/D converter
8 bits, 8 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time base timer
32kHz timer/counter
— High precision timing pattern generation PPG 8 pins 32-stage programmable circuit
RTG 5 pins, 2 channels
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 4 channels
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1 channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Fluorescent display panel controller/driver Maximum 148-segment display possible
Hardware key scan function (Maximum 16 × 3 key matrix available)
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
— Tri-state output
PPG 1 pin, RTG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
22 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP88100A 100-pin ceramic GFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95324-ST
HGO
PWM0
DAA0
DAB0
PWM1
DAA1
DAB1
PWM
RMC
SYNC0/EC2
SYNC1
EXI0
EXI1
ADJ
CFG
DFG
DPG
PBCTL
EC0
EC1
EC2
TO/DDO/ADJ
SI1
SO1
SCK1
AVDD
FIFO
AVss
8 BIT TIMER/COUNTER1
8 BIT TIMER/COUNTER 0
PSEUDO HSYNC GENERATOR
12 BIT PWM GENERATOR CH1
12 BIT PWM GENERATOR CH0
14 BIT PWM GENERATOR
VISS/VASS
FIFO
SERVO INPUT
CONTROL
REMOCON INPUT
CTL
DRUM
CAPSTAN
V SYNC SEPARATOR
EC
SELECT
SERIAL INTERFACE UNIT
(CH1)
SERIAL
INTERFACE UNIT
(CH0)
3
2
4
2
2
2
2
INT1/NMI
CH0
5
RAM
PROGRAMABLE
PATTERN
GENERATOR
1
CH
REALTIME
PULSE
GENERATOR
2
ROM
52K/60K BYTES
SPC700
CPU CORE
8
FIFO
INT2
FRC
CAPTURE UNIT
INTERRUPT CONTROLLER
AVREF
A/D CONVERTER
PPO0 to PPO7
CS0
SI0
SO0
SCK0
8
RTO3 to RTO7
AN0 to AN7
2
8
8
8
FDP
CONTROLLER
/DRIVER
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RAM
1296 BYTES
RAM
VDD
Vss
CLOCK
GENERATOR/
SYSTEM CONTROL
EXTAL
XTAL
TEX
TX
RST
MP
VFDP
T0 to T7
–2–
T8/S15
to
T15/S8
S0 to S7
PORT A
PORT B
PORT C
PORT D
PORT E
PD0 to PD7
8
3
7
PG0 to PG7
8
PI1 to PI7
PH0 to PH2
PF4 to PF7
4
PE2 to PE7
PF0 to PF3
6
PE0 to PE1
PC0 to PC7
8
2
PB0 to PB7
PA0 to PA7
8
4
4
4
PORT F
PORT G
PORT H
AA
PORT I
Block Diagram
CXP88152/88160
INT0
CXP88152/88160
PI5/SCK0
PI4/INT1/NMI/CS0
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
NC
PH2/KR2
PH1/KR1
PH0/KR0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Pin Configuration (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB0
1
80
PI6/SO0
PC7/RTO7
2
79
PI7/SI0
PC6/RTO6
3
78
VFDP
PC5/RTO5
4
77
PD0/S0
PC4/RTO4
5
76
PD1/S1
PC3/RTO3
6
75
PD2/S2
PC2
7
74
PD3/S3
PC1
8
73
PD4/S4
PC0
9
72
PD5/S5
PA7/PPO7
10
71
PD6/S6
(HAMP) PA6/PPO6
11
70
PD7/S7
(ROTA) PA5/PPO5
12
69
S8/T15
(RF-PLS) PA4/PPO4
13
68
S9/T14
PA3/PPO3
14
67
S10/T13
PA2/PPO2
15
66
S11/T12
PA1/PPO1
16
65
S12/T11
HGO/PA0/PPO0
17
64
S13/T10
PF7
18
63
S14/T9
SI1/PF6
19
62
S15/T8
SO1/PF5
20
61
T7
SCK1/PF4
21
60
T6
PF3/AN7
22
59
T5
PF2/AN6
23
58
T4
PF1/AN5
24
57
T3
PF0/AN4
25
56
T2
AN3
26
55
T1
AN2
27
54
T0
AVREF
28
53
PE0/INT0 (ENV-DET)
AVSS
29
52
PE1/EC0/INT2
AVDD
30
51
PWM0/PE2
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) must be connected to GND.
–3–
PE4/DAA0
PE3/PWM1
PE5/DAA1
DAB0/PE6
DAB1/PE7
PG0/CFG
PG1/DFG
XTAL
EXTAL
VSS
RST
MP
PG2/DPG
PG3/PBCTL/EC1
PG4/SYNC0/EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP88152/88160
Pin Description
Symbol
PA0/PPO0/
HGO
I/O
Output/Real time
output/Output
PA1/PPO1
PA2/PPO2
I/O/
Real time output
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
Output/
Real time output
Description
Pseudo HSYNC
output pin.
(Port A)
PA0 and PA5 to PA7 are
for putputs; PA1 to PA4
are for I/O. I/O can be set
in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output.
(8 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)
Head switching
output pins.
(2 pins)
PA7/PPO7
PB0 to PB7
Output
PC0 to PC2
I/O
8-bit output port. Tri-state can be controlled.
(8 pins)
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)
PC3/PPO3
to
PC7/PPO15
I/O/
Real time output
T0 to T7
Output
FDP timing signal output pin. (8 pins)
T8/S15
to
T15/S8
Output/Output
Output pins for FDP timing signal and segment signal. (8 pins)
PD0/S0
to
PD7/S7
Output/Output
(Port D)
8-bit output port.
(8 pins)
PE0/INT0
Input/Input
PE1/EC0/
INT2
Input/Input/Input
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PE4/DAA0
Output/Output
PE5/DAA1
Output/Output
PE6/DAB0
Output/Output
PE7/DAB1
Output/Output
AN0 to AN3
Input
PF0/AN4
to
PF3/AN7
Input/Input
PF4/SCK1
I/O/I/O
PF5/SO1
I/O/Output
PF6/SI1
I/O/Input
PF7
I/O
FDP segment signal output pin. (8 pins)
Trigger pulse
Input pin to request
input pin for head external interruption.
switching output. Active when falling edge.
(Port E)
8-bit port.
Lower 2 bits are for
inputs; upper 6 bits are for
outputs.
(8 pins)
External event
input pin for
timer/counter.
Input pin to request
external interruption.
Active when falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Analog input pins to A/D converter. (8 pins)
(Port F)
Lower 4 bits are for
inputs; upper 4 bits are
for I/O. I/O can be set
in a unit of single bits.
(8 pins)
–4–
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
CXP88152/88160
Symbol
I/O
Description
PG0/CFG
Input/Input
Capstan FG input pin.
PG1/DFG
Input/Input
Drum FG input pin.
PG2/DPG
Input/Input
Drum PG input pin.
PG3/
PBCTL/EC1
Input/Input/Input
Playback CTL input pin.
PG4/
SYNC0/EC2
Input/Input/Input
PG5/SYNC1
Input/Input
PG6/EXI0
Input/Input
PG7/EXI1
Input/Input
PH0/KR0
to
PH2/KR2
I/O/Input
PI1/RMC
I/O/Input
Remote control reception circuit input pin.
PI2/PWM
I/O/Input
14-bit PWM output pin.
PI3/TO/
DDO/ADJ
I/O/Input
PI4/INT1/
NMI/CS0
I/O/Input/
Input/Input
PI5/SCK0
I/O/I/O
PI6/SO0
I/O/Output
Serial data (CH1) output pin.
PI7/SI0
I/O/Input
Serial data (CH1) input pin.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)
RST
Input
System reset pin of active “L” level.
MP
Input
Test mode pin. Always connect to GND.
(Port G)
8-bit input port.
(8 pins)
Composite sync signal input pin.
External event
input pin for
timer/counter.
External event
input pin for
timer/counter.
External input pin for FRC capture unit.
(Port H)
3-bit I/O port.
(3 pins)
(Port I)
7-bit I/O port.
I/O can be set
in a unit of
single bits.
(7 pins)
Key return input signal for key scanning at FDP
segment signal. (3 pins)
Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.
Input pin to request external interruption,
non-maskable interruption and for serial chip select
(CH0). Active when falling edge.
Serial clock (CH1) I/O pin.
Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.
VFDP
FPD voltage supply pin when specifying internal resistor by mask
option.
AVDD
Positive power supply pin of A/D converter.
AVREF
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
NC
Not connected. Under normal operation, connect to VDD.
–5–
CXP88152/88160
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
AA
AA
AA
AA
AAAA AA
AAA
AAA
AA
AAAA
AA
AAAA
AAAA
AA
HSEL
HOUT
PPO0
PA0/PPO0/
HGO
MPX
PA0
Hi-Z
Data bus
RD
(Port A)
1 pin
HSEL
MPX
HOUTE
Output becomes active from high impedance
by data writing to port register.
PPO1
PPG control status
register bit 0
Tri-state control selection
PPO1
PA1/PPO1
PA1
Hi-Z
PA1 direction
IP
Data bus
1 pin
RD (Port A)
Port A
A
AAAA
AAAA
AAAA
PPO data
PA2/PPO2
to
PA4/PPO4
AA
Port A data
Port A direction
IP
Data bus
3 pins
RD (Port A)
Port A
AA
AA
AAAA
PPO data
PA5/PPO5
to
PA7/PPO7
Port A data
Data bus
RD (Port A)
3 pins
Hi-Z
Output becomes active from high impedance
by data writing to port register.
–6–
Hi-Z
CXP88152/88160
AAA
AAA
AAA
AAA
Pin
Port B
Port B data
PB0
to
PB7
Data bus
RD (Port B)
Port C
AA
AA
AA
AAAA
AAAA
AAAA
Port C data
Port C direction
3 pins
AA
AA
AA
AA
AAA
AAA
AAA
RTO3
PC3
PC3 direction
Hi-Z
IP
Data bus
1 pin
RD (Port C)
AA
AA
AA
AA
RTO4
RTG interruption
control register bit 7
Tri-state control selection
AAA
AAA
AAA
RTO4
PC4
PC4 direction
IP
Data bus
1 pin
Hi-Z
RD (Port C)
Port C
PC4/RTO4
Hi-Z
IP
Data bus
PC3/RTO3
AA
AA
Port B tri-state
control
8 pins
PC0
to
PC2
When reset
Circuit format
RD (Port C)
–7–
Hi-Z
CXP88152/88160
Pin
Circuit format
AA
AA
AA
AA
Port C
AAA
AAA
AAA
RTO data
PC5/RTO5
to
PC7/RTO7
Port C data
Port C direction
Data bus
3 pins
When reset
Hi-Z
IP
RD (Port C)
Port D
High voltage drive
transistor
AAA
AAA
Segment output data
PD0/S0
to
PD7/S7
Output selection control signal
("0" when reset)
Port D data
OP Mask option
Data bus
8 pins
AA
AA
AA
AA
AA
AA
Pull-down resistor
Hi-Z or Low
level (when
PD resistor is
connected)
VFDP
RD (Port D)
High voltage drive
transistor
Timing output data
Output selection control signal
("0" when reset)
T0 to T7
OP Mask option
Pull-down resistor
Hi-Z or Low
level (when
PD resistor is
connected)
VFDP
8 pins
High voltage drive
transistor
Timing output data
T8/S15
to
T15/S8
Output selection control signal
("0" when reset)
Segment output data
A
A
OP Mask option
Pull-down resistor
8 pins
–8–
VFDP
Hi-Z or Low
level (when
PD resistor is
connected)
CXP88152/88160
Pin
When reset
Circuit format
Port E
PE0/INT0
PE1/EC0/INT2
AA
AA
AAAA
AAAA
AAAA AA
AA
AAAA
AA
AAAA AA
Schmitt input
INT0
EC0/INT2
IP
2 pins
Hi-Z
Data bus
RD (Port E)
Port E
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E function
select
DA gate output or
PWM output
AA
MPX
Port E data
Hi-Z
Data bus
4 pins
AAAA
AAAAAA
AA
AAAA
AA
AAAA
Hi-Z control
RD (Port E)
Port E
Port E function
select
PE6/DAB0
PE7/DAB1
DA gate output
AA
AA
MPX
Port E data
High level
Data bus
2 pins
Hi-Z control
RD (Port E)
Port F
PF0/AN4
to
PF3/AN7
AA
A
AA
A
AAAA
Input multiplexer
To A/D converter
IP
Hi-Z
Data bus
Port F function select
4 pins
Port F
RD (Port F)
AA
AAA
AA
AAA
AA
AAA
SCK1 output enable
From serial interface
MPX
Port F data
PF4/SCK1
Port F direction
AA
AA
AA
AA
IP
Data bus
1 pin
RD (Port F)
Schmitt input
To serial interface
–9–
Hi-Z
CXP88152/88160
Pin
When reset
Circuit format
Port F
AAA
AAA
AAAA
AAA
AAAA
Port F output selection
AA
AA
AA
AA
From serial interface
MPX
PF5/SO1
Port F data
Port F direction
Data bus
IP
RD (Port F)
1 pin
Port F
AAAA
AAAA
AAAA
AA
AA
AA
Port F data
PF6/SI1
Port F direction
Hi-Z
Hi-Z
IP
Data bus
RD (Port F)
Schmitt input
1 pin
To serial interface
Port F
AAA
AAA
AAA
AAA
AA
AA
AA
Port F data
PF7
Port F direction
IP
Data bus
RD (Port F)
1 pin
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL/
EC1
PG4/SYNC0/
EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
Hi-Z
Port G
AA
AA
AAAA
Schmitt input
IP
Data bus
RD (Port G)
Note) For PG4/SYNC0 and PG5/SYNC1, CMOS schmitt input or TTL schmitt input can be
selected with the mask option.
8 pins
– 10 –
Hi-Z
CXP88152/88160
Pin
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AA
AA
AAAA
AAAA
AAAA
AA
AA
AA
AA
When reset
Circuit format
Port I
Port I function
select
PI2: From 14-bit PWM,
timer/counter
PI3: From CTL duty detection
circuit, 32kHz timer
PI2/PWM
PI3/TO/
DDO/ADJ
MPX
Port I data
Port I direction
Data bus
2 pins
IP
RD (Port I)
Port I
Port I data
PI1/RMC
PI4/INT1/
NMI/CS0
PI7/SI0
Port I direction
IP
Data bus
RD (Port I)
3 pins
Hi-Z
Hi-Z
Schmitt input
PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH0
AAAA
AAAAAA
AA
AAAA
AA
AA
AAAA AAAA
AA
AAA
AAA
AAA
Port I
Port I function
select
PI5/SCK0
PI6/SO0
From
serial CH0
Port I data
Port I direction
MPX
RD (Port I)
PI5: To serial CH0
Schmitt input
Port H
Port H data
PH0/KR0
to
PH2/KR2
Port H direction
Data bus
RD (Port H)
3 pins
Hi-Z
IP
Note)
P15 is schmitt input
Data bus
2 pins
AA
AA
AA
MPX
Key input signal
– 11 –
AA
AA
AA
AA
IP
Hi-Z
CXP88152/88160
Pin
When reset
Circuit format
EXTAL
XTAL
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA AA
EXTAL
IP
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during stop,
and XTAL becomes
High.
Oscillation
XTAL
2 pins
• Shows the circuit composition
during oscillation.
TEX
TX
2 pins
RST
TEX
IP
• Feedback resistor is removed
during 32kHz oscillation circuit
stop by software. At this time
TEX pin outputs "L" level and
TX pin outputs "H" level.
TX
Pull-up resistor
Mask option
OP
Schmitt input
IP
1 pin
Oscillation
– 12 –
Low level
CXP88152/88160
Absolute Maximum Ratings
Item
Symbol
(Vss = 0V)
Rating
Unit
–0.3 to +7.0
AVss to +7.0∗1
V
V
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Display output voltage
VOD
VDD – 4.0 to VDD + 0.3
V
IOH
–5
mA
All pins excluding display outputs
(value per pin)∗3
IODH1
–15
mA
Display outputs S0 to S7 (value per pin)
IODH2
–35
mA
Display outputs T0 to T7,
and T8/S15 to T15/S8 (value per pin)
∑IOH
–50
mA
Total for all pins excluding display outputs
∑IODH
–100
mA
Total for all display outputs
15
mA
130
mA
VDD
Supply voltage
AVDD
AVSS
Input voltage
High level output current
High level total
output current
Low level output current
IOL
Low level total output current ∑IOL
Remarks
V
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
As P-channel transistor is open drain,
VDD is reference.
Total for all outputs
∗1 AVDD must not exceed VDD + 0.3V.
∗2 VIN and VOUT should not exceed VDD + 0.3V.
∗3 It specifies output current of general-purpose I/O port.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 13 –
CXP88152/88160
Recommended Operating Conditions
Item
Supply voltage
Analog power supply
High level input voltage
Low level input voltage
Operating temperature
Symbol
(Vss = 0V)
Min.
Max.
4.5
5.5
Guaranteed range during high speed mode
(1/2 dividing clock) operation
3.5
5.5
Guaranteed range during low speed mode
(1/16 dividing clock) operation
2.7
5.5
2.5
5.5
4.5
5.5
V
Guaranteed data hold operation range
during STOP
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
VIHEX
VDD – 0.4
VDD + 0.3
V
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILTS
0
0.8
V
CMOS schmitt input∗3
TTL schmitt input∗4
VILEX
–0.3
0.4
V
EXTAL pin∗5 TEX pin∗6
Topr
–20
+75
°C
VDD
AVDD
Unit
V
Remarks
Guaranteed operation range by TEX clock
CMOS schmitt input∗3
TTL schmitt input∗4
EXTAL pin∗5 TEX pin∗6
∗2
∗1 AVDD and VDD should be set to the same voltage.
∗2 Normal input port (each pin of PA1 to PA4, PC, PF0 to PF3, PF5, PF7, PH, PI2, PI3 and PI6), MP pin
∗3 Each pin of RST, PE0/INT0, PE1/EC0/INT2, PF4/SCK1, PF6/SI1, PI1/RMC, PI4/CS0/NMI/INT1, PI5/SCK0,
PI7/SI1 and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option)
∗4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
∗5 It specifies only when the external clock is input.
∗6 It specifies only when the external event is input.
– 14 –
CXP88152/88160
DC Characteristics
Item
Symbol
High level
VOH
output voltage
Low level
VOL
output voltage
Display
output current
(Ta = –20 to +75°C, Vss = 0V)
Pin
Condition
Min.
V
3.5
V
S0 to S7
–8
mA
–20
mA
VDD = 4.5V,
VOH = VDD – 2.5V
Open drain
output leakage
current (P-CH ILOL
Tr OFF in state)
S0 to S7,
S8/T15 to
S15/T8,
T0 to T7
VDD = 5.5V,
VOL = VDD – 35V
VFDP = VDD – 35V
Pull-down
resistor∗2
RL
S0 to S7,
S8/T15 to
S15/T8,
T0 to T7
VDD = 5V,
VFDP – VDD = 30V
60
VDD = 5.5V, VIH = 5.5V
IIHE
EXTAL
IILE
TEX
Supply
current∗3
Input
capacity
Unit
4.0
S8/T15 to
S15/T8,
T0 to T7
I/O leakage
current
Max.
VDD = 4.5V, IOH = –0.5mA
PA to PC, PE
PF4 to PF7, VDD = 4.5V, IOH = –1.2mA
PH,
VDD = 4.5V, IOL = 1.8mA
PI1 to PI7
VDD = 4.5V, IOL = 3.6mA
IOH
Input
current
Typ.
0.4
V
0.6
V
–20
µA
270
kΩ
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
±10
µA
VDD = 5.5V,
VIL = 0.4V
IILR
RST∗1
IIZ
PA to PC,
PE to PI,
AN1 to AN3, VDD = 5.5V, VI = 0, 5.5V
MP,
RST∗1
100
IDD1
16MHz crystal oscillation
(C1 = C2 = 15pF), VDD = 5V ± 0.5V∗4
30
50
mA
IDDS1
16MHz crystal oscillation (C1 = C2 = 15pF),
VDD = 5V ± 0.5V, SLEEP mode
1.8
8
mA
32kHz crystal oscillation (C1 = C2 = 47pF),
VDD = 3V ± 0.3V
25
110
µA
IDDS2
32kHz crystal oscillation (C1 = C2 = 47pF),
VDD = 3V ± 0.3V, SLEEP mode
4
35
µA
IDDS3
VDD = 5.5V, STOP mode
(32kHz, 16MHz oscillation stop)
10
µA
20
pF
IDD2
CIN
VDD, Vss
PA1 to PA4,
PC0 to PC7,
PE0, PE1,
AN0 to AN3, Clock 1MHz
PF0 to PF7, 0V other than the measured pins
PG0 to PG7,
PH0 to PH2,
PI1 to PI7
– 15 –
10
CXP88152/88160
∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗2 When built-in pull-down resistor is selected with mask option.
∗3 When entire output pins are open.
∗4 When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to “00” and
operating in high speed mode (1/2 dividing clock).
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
Min.
System clock frequency
fC
XTAL
EXTAL
Fig. 1, Fig. 2
1
System clock input pulse width
tXL,
tXH
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
28
System clock input rise and
fall times
tCR,
tCF
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
Event count clock input
pulse width
EC0, EC1,
Fig. 3
EC2
Event count clock input
rise and fall times
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count clock input
pulse width
tTL,
tTH
tTR,
tTF
Event count clock input
rise and fall times
Typ.
Max.
Unit
16
MHz
ns
200
tsys+200∗1
ns
EC0, EC1,
Fig. 3
EC2
20
TEX
TX
VDD=2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
ns
ms
kHz
32.768
µs
10
20
ms
∗1 tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
XTAL
0.4V
tXH
tCF
tXL
tCR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA AAAA AAAA
Fig. 2. Clock applied condition
Crystal oscillation
Ceramic oscillation
EXTAL
C1
XTAL
C2
External clock
EXTAL
32kHz clock applied condition
Crystal oscillation
TEX
XTAL
74HC04
– 16 –
C1
TX
C2
CXP88152/88160
Fig. 3. Event count clock timing
TEX
EC0
EC1
EC2
0.8VDD
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer (CH0)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys + 200
ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys + 200
ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys + 200
ns
SCK0
cycle time
tKCY
Input mode
2tsys + 200
ns
SCK0
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
tsys + 100
ns
SCK0
8000/fc – 50
ns
SI0 input set-up time
(against SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
tKSI
tsys + 200
ns
SI0
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 17 –
CXP88152/88160
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 18 –
CXP88152/88160
Serial transfer (CH1)
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input set-up time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Min.
Input mode
Max.
1000
ns
16000/fc
ns
400
ns
8000/fc–50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer timing (CH1)
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 19 –
CXP88152/88160
(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VDD = AVss = 0V
Linearity error
Absolute error
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
Conversion time
Operation mode
AVREF = 4.0 to 5.5V
AVREF current
IREF
AVREF
Max.
Unit
8
Bits
±1
LSB
±2
LSB
160/fADC
µs
12/fADC
µs
AVDD – 0.5
AVDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
SLEEP mode
STOP mode
32kHz operation mode
Fig. 6. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗ The value of fADC is as follows by selecting ADC
operation clock (MSC: 01FEH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 20 –
CXP88152/88160
(4) Interruption, reset input
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
Min.
Max.
Unit
External interruption high and
low level widths
tIH
tIL
INT0
INT1
INT2
NMI
1
µs
Reset input low level width
tRSL
RST
32/fc
µs
Fig. 7. Interruption input timing
tIH
INT0
INT1
INT2
NMI
(Falling edge)
tIL
0.8VDD
0.2VDD
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
(5) Others
Item
Symbol
DPG minimum pulse width
tCFH
tCFL
tDFH
tDFL
tDPW
DPG minimum removal time
trem
PBCTL input high and low
level widths
tCTH
tCTL
tEIH
tEIL
CFG input high and
low level widths
DFG input high and
low level widths
EXI input high and low level
widths
Pin
Condition
Min.
Max.
Unit
CFG
tFRC × 24 + 200
ns
DFG
tFRC × 16 + 200
ns
DPG
tFRC × 8 + 200
ns
DPG
tFRC × 16 + 200
ns
PBCTL
tsys = 2000/fc
tFRC × 8 + tsys + 200
ns
EXI0
EXI1
tsys = 2000/fc
tFRC × 8 + tsys + 200
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) tFRC = 1000/fc (ns)
– 21 –
CXP88152/88160
Fig. 9. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
DFG
tDFL
0.8VDD
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
EXI0
EXI1
tEIL
0.8VDD
0.2VDD
– 22 –
CXP88152/88160
Supplement
Fig. 10. Recommended oscillation circuit
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
(i)
EXTAL
(ii)
TEX
XTAL
Rd
Manufacturer
RIVER
ELETEC
CO., LTD.
Rd
C2
C1
Model
HC-49/U03
C2
C1
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
22 (15)
22 (15)
12.00
15
15
16.00
12
12
32.768kHz
30
18
Rd (Ω)
Circuit
example
0
(i)
0
(i)
470k
(ii)
10.00
12.00
TX
16.00
8.00
KINSEKI LTD.
HC-49/U (-S)
P3
10.00
Mask option table
Content
Item
Reset pin pull-up resistor
Non-existent
Existent
High voltage drive output port pull-down resistor
Input circuit format∗1
Non-existent
Existent
CMOS schmitt
TTL schmitt
∗1 In PG4/SYNC0/EC2 pin and PG5/SYNC1 pin, the input circuit format can be selected every pin.
– 23 –
CXP88152/88160
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5.0V, Ta = 25°C, Typical)
30
1/2 dividing mode
100
1/4 dividing mode
10
1/16 dividing mode
SLEEP mode
1
32kHz mode
(instruction)
0.1
25
IDD – Supply current [mA]
IDD – Supply current [mA]
1/2 dividing mode
20
1/4 dividong mode
15
10
32kHz
SLEEP mode
1/16 dividing mode
5
0.01
SLEEP mode
3
4
5
0
6
VDD – Supply voltage [V]
5
10
15
fc – System clock [MHz]
– 24 –
20
CXP88152/88160
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
(16.3)
0.15
0° to 15°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
SONY CODE
QFP-100P-L01
EIAJ CODE
∗QFP100-P-1420-A
JEDEC CODE
– 25 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g