SONY CXP847P60Q

CXP847P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP847P60 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, FRC capture unit, highprecision timing pattern generation circuit, PWM
output, and the like besides the basic configurations
of 8-bit CPU, PROM, RAM, and I/O ports.
The CXP847P60 also provides the sleep/stop
functions that enable to execute the power-on reset
function and lower the power consumption.
The CXP847P60 is the PROM-incorporated version
of the CXP84716/84720/84724 with built-in mask
ROM. This provides the additional feature of being
able to write directly into the program. Thus, it is
most suitable for evaluaiton use during system
development and for small-quantity production.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which covers various types of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (3.0 to 5.5V)
• Incorporated PROM capacity
60K bytes
• Incorporated RAM capacity
2144 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 1.6µs at 16MHz)
— Serial interface
Srart-stop synchronization (UART), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
16-bit capture timer/counter
— FRC capture unit
Incorporated 24-bit and 6-stage FIFO
— High-precision timing pattern generation circuit
PPG: maximum of 11 pins, 16 stages programmable, 2 channels
— PWM output
8 bits, 8 channels
• Interruption
19 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin plastic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97119-PS
AVREF
AVSS
8 BIT PWM GENERATOR 4
8 BIT PWM GENERATOR 5
8 BIT PWM GENERATOR 6
PWM4
PWM5
PWM6
TO
CINT
EC1
16 BIT CAPTURE
TIMER/COUNTER 2
8 BIT TIMER 1
8 BIT TIMER/COUNTER 0
EC0
BUFFER
RAM
SERIAL INTERFACE UNIT
(CH2)
SERIAL
INTERFACE
UNIT (CH1)
CS1
SI1
SO1
SCK1
BUFFER
RAM
SI2
SO2
SCK2
SERIAL
INTERFACE
UNIT (CH0)
CS0
SI0
SO0
SCK0
8 BIT PWM GENERATOR 7
8 BIT PWM GENERATOR 2
8 BIT PWM GENERATOR 3
PWM7
8 BIT PWM GENERATOR 1
PWM2
PWM3
8 BIT PWM GENERATOR 0
UART BAUD RATE
GENERATOR
UART RECEIVER
UART TRANSMITTER
PWM0
PWM1
TxD
AVDD
A/D CONVERTER
2
2
NMI
FIFO
4
11
PROGRAMMABLE
PATTERN
BUFFER
GENERATOR
RAM
(CH1)
FRC
CAPTURE UNIT
RAM
2144 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
11
PROGRAMMABLE
PATTERN
BUFFER
GENERATOR
RAM
(CH0)
PRESCALER/
TIME BASE TIMER
PROM
60K BYTES
SPC 700
CPU CORE
PPO0
to
PPO10
RxD
8
INTERRUPT CONTROLLER
NMI
INT0
INT1
INT2
INT3
INT4
PPO11
to
PPO21
AN0 to AN7
EXTAL
XTAL
RST
VDD
VSS
EXI0
to
EXI3
–2–
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PORT J
Block Diagram
PI0 to PI7
8
PJ0 to PJ7
PH0 to PH7
8
8
PG0 to PG7
PF6
PF7
PF0 to PF5
PE6 to PE7
PE0 to PE5
PD0 to PD7
PC0 to PC7
PB0 to PB7
PA0 to PA7
8
6
2
6
8
8
8
8
CXP847P60
CXP847P60
PI2/INT2
PI3/INT3
PI4/INT4
PI5/SCK2
PI6/SI2
PI7/SO2
PG0/PWM0
VDD
VSS
Vpp
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/PWM4
PG5/PWM5
PG6/PWM6
PG7/PWM7
PF0
PF1
PF2
Pin Assignment (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PF3
1
80
PI1/INT1
PF4
2
79
PI0/INT0
PF5
3
78
PE7/TO
PF6/TxD
4
77
PE6
PF7/RxD
5
76
PE5
PD0/PPO0
6
75
PE4
PD1/PPO1
7
74
PE3/NMI
PD2/PPO2
8
73
PE2
PD3/PPO3
9
72
PE1/EC1
PD4/PPO4
10
71
PE0/EC0
11
70
PB7/SO1
PD5/PPO5
PD6/PPO6
12
69
PB6/SI1
PD7/PPO7
13
68
PB5/SCK1
PC0
14
67
PB4/CS1
PC1
15
66
PB3
PC2
16
65
PB2
PC3
17
64
PB1
PC4
18
63
PB0/CINT
PC5
19
62
SO0
PC6
20
61
SI0
PC7
21
60
SCK0
PH0/PPO8
22
59
CS0
PH1/PPO9
23
58
PA7
PH2/PPO10
24
57
PA6
PH3/PPO11
25
56
PA5
PH4/PPO12
26
55
PA4
PH5/PPO13
27
54
PA3/AN7
PH6/PPO14
28
53
PA2/AN6
PH7/PPO15
29
52
PA1/AN5
PJ0/PPO16
30
51
PA0/AN4
Note) 1. Vpp (Pin 90) is left open.
2. VSS (Pins 41 and 88) are both connected to GND.
–3–
AN3
AN2
AN1
AN0
AVDD
AVREF
AVSS
EXI3
EXI2
VSS
XTAL
EXTAL
RST
PJ7/EXI1
PJ6/EXI0
PJ5/PPO21
PJ4/PPO20
PJ3/PPO19
PJ2/PPO18
PJ1/PPO17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP847P60
PE7/TO
PI0/INT0
PI1/INT1
PI2/INT2
PI3/INT3
PI4/INT4
PI5/SCK2
PI6/SI2
PI7/SO2
PG0/PWM0
VDD
VSS
Vpp
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/PWM4
PG5/PWM5
PG6/PWM6
PG7/PWM7
PF0
PF1
PF2
PF3
PF4
Pin Assignment (Top View) 100-pin LQFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PF5
1
75
PE6
PF6/TxD
2
74
PE5
PF7/RxD
3
73
PE4
PD0/PPO0
4
72
PE3/NMI
PD1/PPO1
5
71
PE2
PD2/PPO2
6
70
PE1/EC1
PD3/PPO3
7
69
PE0/EC0
PD4/PPO4
8
68
PB7/SO1
PD5/PPO5
9
67
PB6/SI1
PD6/PPO6
10
66
PB5/SCK1
PD7/PPO7
11
65
PB4/CS1
PC0
12
64
PB3
PC1
13
63
PB2
PC2
14
62
PB1
PC3
15
61
PB0/CINT
PC4
16
60
SO0
PC5
17
59
SI0
PC6
18
58
SCK0
PC7
19
57
CS0
PH0/PPO8
20
56
PA7
PH1/PPO9
21
55
PA6
PH2/PPO10
22
54
PA5
PH3/PPO11
23
53
PA4
PH4/PPO12
24
52
PA3/AN7
PH5/PPO13
25
51
PA2/AN6
Note) 1. Vpp (Pin 88) is left open.
2. VSS (Pins 39 and 86) are both connected to GND.
–4–
PA1/AN5
AN3
PA0/AN4
AN2
AN1
AN0
AVDD
AVSS
AVREF
EXI3
EXI2
VSS
XTAL
EXTAL
RST
PJ7/EXI1
PJ6/EXI0
PJ5/PPO21
PJ4/PPO20
PJ3/PPO19
PJ2/PPO18
PJ1/PPO17
PJ0/PPO16
PH7/PPO15
PH6/PPO14
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP847P60
Pin Description
Symbol
AN0
to
AN3
I/O
Input
PA0/AN4
to
PA3/AN7
I/O/Input
PA4 to PA7
I/O
PB0/CINT
I/O/Input
PB1 to PB3
I/O
PB4/CS1
I/O/Input
PB5/SCK1
I/O/I/O
PB6/SI1
I/O/Input
PB7/SO1
I/O/Output
Description
Analog inputs to A/D converter.
(4 pins)
(Port A)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(4 pins)
External capture input to 16-bit
timer/counter.
(Port B)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the
software in a unit of 4 bits.
(8 pins)
Chip select input for serial interface
(CH1).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
I/O
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the software in
a unit of 4 bits.
(8 pins)
PD0/PPO0
to
PD7/PPO7
I/O/Real-time
output
(Port D)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)
PE0/EC0
Input/Input
PE1/EC1
Input/Input
PE2
Input
PE3/NMI
Input/Input
PE4 to PE5
Input
PE6
Output
PE7/TO
Output/Output
PC0 to PC7
PPO0 to PPO7 outputs for programmable
pattern generator (PPG0). Functions as
high-precision real-time pulse output port.
(PPG0: 11 pins; PPG1: 11 pins)
External event inputs for timer/counter.
(2 pins)
(Port E)
8-bit port. Lower 6 bits are for
input; upper 2 bits are for
output.
(8 pins)
Non-maskable interruption request.
Rectangular wave output for 16-bit
timer/counter.
–5–
CXP847P60
Symbol
I/O
Description
(Port F)
Lower 6 bits are for I/O. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits (PF0 to PF3) or 2 bits (PF4, PF5).
PF6 is for output; PF7 is for input.
(8 pins)
PF0 to PF5
I/O
PF6/TXD
Output/Output
UART transmission data output.
PF7/RXD
Input/Input
UART reception data input.
I/O/Output
(Port G)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)
PWM outputs.
(8 pins)
PH0/PPO8
to
PH7/PPO15
I/O/Real-time
output
(Port H)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)
PPO8 to PPO11 (PPG0) outputs and
PPO12 to PPO15 (PPG1) outputs for
programmable pattern generator (PPG0,
PPG1).
Functions as high-precision real-time pulse
output port.
PI0/INT0
to
PI4/INT4
I/O/Input
PI5/SCK2
I/O/I/O
PI6/SI2
I/O/Input
PI7/SO2
I/O/Output
PG0/PWM0
to
PG7/PWM7
PJ0/PPO16
to
PJ5/PPO21
I/O/Real-time
output
PJ6/EXI0
I/O/Input
PJ7/EXI1
I/O/Input
EXI2 to EXI3 Input
(Port I)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
(8 pins)
(Port J)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)
External interruption request inputs.
(5 pins)
Serial clock I/O (CH2).
Serial data input (CH2).
Serial data output (CH2).
PPO16 to PPO21 outputs for
programmable pattern generator (PPG1).
Functions as high-precision real-time
pulse output port.
External inputs to FRC capture unit.
(2 pins)
External inputs to FRC capture unit.
(2 pins)
CS0
Input
Chip select input for serial interface (CH0).
SCK0
I/O
Serial clock I/O (CH0).
SI0
Input
Serial data input (CH0).
SO1
Output
Serial data output (CH0).
–6–
CXP847P60
Symbol
I/O
EXTAL
Input
XTAL
Output
RST
I/O
Description
Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
pin.
System reset; active at Low level. This pin is I/O pin, and outputs Low
level at the power on with the power-on reset function executed. (Mask
option)
Vpp
Positive power supply for incorporated PROM writing.
Leave this pin open for normal operation. (Internally connected to VDD.)
AVDD
Positive power supply of A/D converter.
AVREF
Input
Reference voltage input of A/D converter.
AVSS
GND of A/D converter.
VDD
Positive power supply.
VSS
GND.
–7–
CXP847P60
I/O Circuit Format for Pins
Pin
Port A
AAA
AAA
AAA
AAA
AAA
AAA
AAA
∗
Pull-up resistor
AA
AA
AA
AA
"0" when reset
Port A data
PA0/AN4
to
PA3/AN7
When reset
Circuit format
Port A direction
Input
protection
circuit
IP
"0" when reset
Data bus
Hi-Z
RD (Port A)
Port A function
selection
Input multiplexer
"0" when reset
4 pins
Port A
Port B
Port F
A/D converter
AAAA
AAAA
AAAAA
AAAAA
AAAAA
Pull-up resistor
"0" when reset
Ports A, B, F data
PA4 to PA7
PB1 to PB3
PF0 to PF5
Ports A, B, F direction
"0" when reset
Data bus
RD (Ports A, B, F)
13 pins
Port B
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
Pull-up resistor
"0" when reset
Port J
PB0/CINT
PB4/CS1
PB6/SI1
PI6/SI2
PJ6/EXI0
PJ7/EXI1
Ports B, I, J data
Ports B, I, J direction
"0" when reset
Data bus
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
∗
AA
AA
AA
AA
IP
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
∗
AA
AA
AA
AA
IP
Schmitt input
RD (Ports B, I, J)
6 pins
CINT
CS1
SI1
SI2
EXI0
EXI1
–8–
Hi-Z
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Hi-Z
CXP847P60
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Pin
When reset
Circuit format
Port B
∗
Pull-up resistor
Port I
"0" when reset
SCK OUT
Serial clock output enable
AA
AAAA
Ports B, I function
selection
"0" when reset
PB5/SCK1
PI5/SCK2
IP
Ports B, I data
Ports B, I direction
Hi-Z
"0" when reset
Data bus
Schmitt input
RD (Ports B, I)
SCK in
2 pins
Port B
AAAA
AAAA
AAAA
AAAA
AAAA
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
∗
Pull-up resistor
Port I
"0" when reset
SO
Serial data output enable
AA
AAAA
Ports B, I function
selection
"0" when reset
PB7/SO1
PI7/SO2
IP
Ports B, I data
Ports B, I direction
Hi-Z
"0" when reset
Data bus
RD (Ports B, I)
2 pins
Port C
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
AAA
AAA
AAA
AAA
AAA
∗2
Pull-up resistor
AA
AA
AA
AA
"0" when reset
Port C data
PC0 to PC7
∗1
Port C direction
"0" when reset
Data bus
RD (Port C)
IP
∗1 Large current 12mA
∗2 Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
8 pins
–9–
Hi-Z
CXP847P60
Pin
Port D
PD0/PPO0
to
PD7/PPO7
Port H
Port J
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
PPO data
AAA
Ports D, H, J data
PH0/PPO8
to
PH7/PPO15
Ports D, H, J direction
PJ0/PPO16
to
PJ5/PPO21
"0" when reset
22 pins
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Port E
A A
Port F
Schmitt input (Inverter input for PE2, PE4, PE5)
IP
EC0, EC1, NMI, RxD
Hi-Z
Data bus
RD (Ports E, F)
7 pins
AAAA
AAAA
AA
AA
Port E
PE6
Hi-Z
IP
Data bus
RD (Ports D, H, J)
PE0/EC0
PE1/EC1
PE2
PE3/NMI
PE4
PE5
PF7/RxD
When reset
Circuit format
Port E data
"1" when reset
Data bus
1 pin
High level
RD (Port E)
Port E
AAAA
AAAA
AAAAA
AAAAA
Internal reset signal
00
Port E data
PE7/TO
"1" when reset
TO
MPX
AA
(
AA
∗
01
Port E function selection (upper)
Port E function selection (lower)
∗ Pull-up transistors
"00" when reset
TO output enable
1 pin
– 10 –
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 400kΩ (VDD = 3.0 to 3.6V)
High level
with the
resistor of pullup transistor
ON for reset
)
CXP847P60
Pin
AAAAA
AAAAA
AAAA
AAAA
When reset
Circuit format
Port F
UART transmission circuit
Control for
transmission and ports
PF6/TxD
A
"0" when reset
Port F data
"1" when reset
High level
Data bus
1 pin
RD (Port F)
Port G
AAAA
AAAA
AAAA
AAAA
AAAA
∗
Pull-up resistor
"0" when reset
PWM
AA
AAAA
Port G function
selection
PG0/PWM0
to
PG7/PWM7
"0" when reset
IP
Port G data
Port G direction
Hi-Z
"0" when reset
Data bus
RD (Port G)
8 pins
Port I
AAAA
AAAA
AAAA
AAAA
AAAA
Pull-up resistor
"0" when reset
Port I data
PI0/INT0
to
PI4/INT4
Port I direction
"0" when reset
Data bus
RD (Port I)
5 pins
AN0
to
AN3
4 pins
INT0
INT1
INT2
INT3
INT4
AA
AA
AAAA
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
∗
AA
AA
AA
AA
IP
Hi-Z
Schmitt input
∗ Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Input multiplexer
IP
– 11 –
A/D converter
Hi-Z
CXP847P60
Pin
When reset
Circuit format
AA
A
AA
AAAA
AA
EXI2
EXI3
Schmitt input
EXI2, EXI3
IP
2 pins
CS0
SI0
Schmitt input
2 pins
AA
AA
SO0
SO0 from SIO
SO0 output enable
AA
AA
AA
AA
Internal serial clock
from SIO
SCK0
External serial clock to SIO
1 pin
2 pins
Hi-Z
High level
IP
SCK0 output enable
EXTAL
XTAL
Hi-Z
SIO
IP
1 pin
Hi-Z
Schmitt input
AA AA A
AA
AA AA
EXTAL
IP
IP
• Diagram shows the circuit
composition during oscillation.
• Feedback resistor is removed
during stop mode and XTAL
becomes High level.
Oscillation
XTAL
Pull-up resistor
RST
OP
Mask option
IP
1 pin
Schmitt input
From power-on reset circuit
(Mask option)
See the Selection Guide for the Mask option.
– 12 –
Low level
(During a
reset)
CXP847P60
Absolute Maximum Ratings
Item
(Vss = 0V reference)
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
V
AVDD
–0.3 to +13.0
AVSS to +7.0∗1
AVSS
–0.3 to +0.3
V
AVREF
V
VIN
AVSS to +7.0
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
High level output current
IOH
–5
mA
Output (value per pin)
–50
mA
Total for all output pins
IOL
15
mA
All pins excluding large current
outputs (value per pin)
IOLC
20
mA
Large current outputs (value per pin) ∗3
Low level total output current
∑IOL
100
mA
Total for all output pins
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
Supply voltage
Input voltagte
Symbol
High level total output current ∑IOH
Low level output current
600
380
Remarks
Incorporated PROM
V
V
mW
QFP package
LQFP package
∗1 AVDD and VDD must be set to the same voltage.
∗2 VIN and VOUT must not exceed VDD + 0.3V.
∗3 The large current output pins are Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP847P60
Recommended Operating Conditions
Item
Supply voltage
Analog voltage
Symbol
VDD
AVDD
VIH
High level input
voltage
VIHS
VIHEX
VIL
Low level input
voltage
VILS
VILEX
Operating temperature Topr
(Vss = 0V reference)
Min.
Max.
Unit
Remarks
4.5
5.5
V
3.0
5.5
V
fc = 16MHz or less Guaranteed operation
range for 1/2 and 1/4
fc = 12MHz or less frequency dividing clock.
2.7
5.5
V
2.5
5.5
V
3.0
5.5
V
Guaranteed data hold range during stop
mode
∗1
0.7VDD
VDD
V
∗2, ∗5
0.8VDD
VDD
V
∗2, ∗6
0.8VDD
VDD
V
VDD – 0.4 VDD + 0.3
V
VDD – 0.2 VDD + 0.2
V
Guaranteed operation range for 1/16
frequency dividing clock or sleep mode
Hysteresis input∗3
EXTAL pin∗4, ∗5
0
0.3VDD
V
EXTAL pin∗4, ∗6
∗2, ∗5
0
0.2VDD
V
∗2, ∗6
0
0.2VDD
V
–0.3
0.4
V
Hysteresis input∗3
EXTAL pin∗4, ∗5
–0.3
0.2
V
EXTAL pin∗4, ∗6
–10
+75
°C
∗1 AVDD and VDD must be set to the same voltage.
∗2 Normal input port (PA, PB1 to PB3, PB7, PC, PD, PE2, PE4, PE5, PF0 to PF5, PG, PH, PI7, PJ0 to PJ5)
∗3 RST, CINT, CS0, CS1, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, NMI, RxD, INT0, INT1, INT2, INT3,
INT4, EXI0, EXI1, EXI2 and EXI3
∗4 Specifies only when the external clock is input.
∗5 This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
∗6 This case applies to the range of 3.0 to 5.5V supply voltage (VDD).
– 14 –
CXP847P60
Electrical Characteristics
(Ta = –10 to +75°C, VSS = 0V reference)
DC Characteristics (VDD = 4.5 to 5.5V)
Item
Symbol
High level
VOH
output voltage
Low level
VOL
output voltage
Pins
PA to PD,
VDD = 4.5V, IOH = –0.5mA
PE6, PE7,
PF0 to PF6,
PG to PJ,
VDD = 4.5V, IOH = –1.2mA
SCK0, SO0
IILE
IIHT
Input current
IILT
IILR
IIL
I/O leakage
current
IIZ
Min.
EXTAL
TEX
Typ.
Max.
Unit
4.0
V
3.5
V
PA to PD,
VDD = 4.5V, IOL = 1.8mA
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0, VDD = 4.5V, IOL = 3.6mA
RST∗1
PC
IIHE
Conditions
VDD = 4.5V, IOL = 12.0mA
0.4
V
0.6
V
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIL = 5.5V
0.1
10
µA
VDD = 5.5V, VIL = 0.4V
–0.1
–10
µA
–1.5
–400
µA
–45
µA
RST∗2
VDD = 5.5V, VIL = 0.4V
PA to PD∗3,
PF0 to PF5∗3,
VDD = 4.5V, VIL = 4.0V
PG to PJ∗3
∗
3
PA to PD ,
PE0 to PE5,
PF0 to PF5∗3,
PF7,
PG to PJ∗3,
VDD = 5.5V
CS0, SCK0,
VI = 0, 5.5V
SI0, EXI2,
EXI3,
AN0 to AN3
RST∗2
– 15 –
–2.78
µA
±10
µA
CXP847P60
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
24
50
mA
1.5
10
mA
10
µA
20
pF
1/2 frequency dividing clock operation
IDD
Supply
current∗4
Sleep mode
IDDS1
IDDS2
Input
capacity
VDD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
CIN
VDD
VDD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
VDD = 5.5V, termination of 16MHz
crystal oscillation
PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,
PG to PJ,
Clock 1MHz
CS0, SCK0, 0V for all pins excluding measured
SI0, EXI2,
pins
EXI3,
AN0 to AN3,
EXTAL,
RST
10
∗1 RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.
∗2 RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.
∗3 PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.
∗4 When all pins are open.
Note) See the Selection Guide for the mask option.
– 16 –
CXP847P60
Electrical Characteristics
(Ta = –10 to +75°C, VSS = 0V reference)
DC Characteristics (VDD = 3.0 to 3.6V)
Item
Symbol
High level
VOH
output voltage
Low level
VOL
output voltage
Pins
PA to PD,
VDD = 3.0V, IOH = –0.15mA
PE6, PE7,
PF0 to PF6,
PG to PJ,
VDD = 3.0V, IOH = –0.5mA
SCK0, SO0
IILE
IIHT
Input current
IILT
IILR
IIL
I/O leakage
current
IIZ
Min.
EXTAL
TEX
Typ.
Max.
Unit
2.7
V
2.3
V
PA to PD,
VDD = 3.0V, IOL = 1.2mA
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0, VDD = 3.0V, IOL = 1.6mA
RST∗1
PC
IIHE
Conditions
VDD = 3.0V, IOL = 5.0mA
0.3
V
0.5
V
1
V
VDD = 3.6V, VIH = 3.6V
0.3
20
µA
VDD = 3.6V, VIL = 0.3V
–0.3
–20
µA
VDD = 3.6V, VIL = 3.6V
0.1
10
µA
VDD = 3.6V, VIL = 0.4V
–0.1
–10
µA
–0.9
–200
µA
–20
µA
RST∗2
VDD = 3.6V, VIL = 0.3V
PA to PD∗3,
PF0 to PF5∗3,
VDD = 3.0V, VIL = 2.7V
PG to PJ∗3
∗
3
PA to PD ,
PE0 to PE5,
PF0 to PF5∗3,
PF7,
PG to PJ∗3,
VDD = 3.6V
CS0, SCK0,
VI = 0, 3.6V
SI0, EXI2,
EXI3,
AN0 to AN3
RST∗2
– 17 –
–1.0
µA
±10
µA
CXP847P60
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
Unit
10
25
mA
0.5
2.0
mA
10
µA
20
pF
1/2 frequency dividing clock operation
IDD
Supply
current∗4
Sleep mode
IDDS1
IDDS2
Input
capacity
VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
CIN
VDD
VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
VDD = 3.6V, termination of 12MHz
crystal oscillation
PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,
PG to PJ,
Clock 1MHz
CS0, SCK0, 0V for all pins excluding measured
SI0, EXI2,
pins
EXI3,
AN0 to AN3,
EXTAL,
RST
10
∗1 RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.
∗2 RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.
∗3 PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.
∗4 When all pins are open.
Note) See the Selection Guide for the mask option.
– 18 –
CXP847P60
AC Characteristics
(1) Clock timing
Item
(Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Symbol
Pin
Conditions
Min.
VDD = 4.5 to 5.5V
fC
XTAL
EXTAL
Fig. 1, Fig. 2
System clock input pulse
width
tXL
tXH
XTAL
EXTAL
Fig. 1, Fig. 2 VDD = 4.5 to 5.5V
External clock drive
System clock input
rise time, fall time
tCR
tCF
tEH
tEL
tER
tEF
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
EC0
EC1
Fig. 3
EC0
EC1
Fig. 3
System clock frequency
Event count input clock
pulse width
Event count input clock
rise time, fall time
Typ. Max.
1
16
1
12
28
Unit
MHz
ns
37.5
200
tsys + 50∗1
ns
ns
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
EXTAL
0.4V (VDD = 4.5 to 5.5V)
0.3V
tCF
tXH
tXL
tCR
AAAA
AAAA
AAAA
AAAA
AAAA AAAA
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
C1
External clock
EXTAL
C2
XTAL
74HC04
Fig. 3. Event count clock timing
0.8VDD
EC0
EC1
0.2VDD
tEH
tEF
– 19 –
tEL
tER
CXP847P60
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
(2) Serial transfer (CH0, CH1)
Item
Symbol
Pin
Conditions
Min.
Max.
Unit
CS↓ → SCK
delay time
tDCSK
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS↑ → SCK
floating delay time
tDCSKF
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS↓ → SO delay time
tDCSO
SO0
SO1
Chip select transfer mode
1.5tsys + 200
ns
CS↑ → SO floating
delay time
tDCSOF
SO0
SO1
Chip select transfer mode
1.5tsys + 200
ns
CS High level width
tWHCS
CS0
CS1
Chip select transfer mode
tsys + 200
ns
SCK cycle time
tKCY
SCK0
SCK1
Input mode
2tsys + 200
ns
8000/fc
ns
SCK High and Low
level widths
tKH
tKL
SCK0
SCK1
Input mode
tsys + 100
ns
Output mode
4000/fc – 50
ns
SI input setup time
(for SCK↑)
tSIK
SI0
SI1
SCK input mode
–tsys + 100
ns
200
ns
SI input hold time
(for SCK↑)
tKSI
SI0
SI1
SCK input mode
2tsys + 200
ns
100
ns
SCK↓ → SO
delay time
tKSO
SO0
SO1
SCK input mode
Output mode
SCK output mode
SCK output mode
SCK output mode
2tsys + 200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 20 –
CXP847P60
Serial transfer (CH0, CH1)
Item
Symbol
(Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Pin
Conditions
Min.
Max.
Unit
CS↓ → SCK
delay time
tDCSK
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 250
ns
CS↑ → SCK
floating delay time
tDCSKF
SCK0
SCK1
Chip select transfer mode
(SCK = output mode)
1.5tsys + 200
ns
CS↓ → SO delay time
tDCSO
SO0
SO1
Chip select transfer mode
1.5tsys + 250
ns
CS↑ → SO floating
delay time
tDCSOF
SO0
SO1
Chip select transfer mode
1.5tsys + 200
ns
CS High level width
tWHCS
CS0
CS1
Chip select transfer mode
tsys + 200
ns
SCK cycle time
tKCY
SCK0
SCK1
Input mode
2tsys + 200
ns
8000/fc
ns
SCK High and Low
level widths
tKH
tKL
SCK0
SCK1
Input mode
tsys + 100
ns
4000/fc – 100
ns
SI input setup time
(for SCK↑)
tSIK
SI0
SI1
SCK input mode
–tsys + 100
ns
200
ns
SI input hold time
(for SCK↑)
tKSI
SI0
SI1
SCK input mode
2tsys + 200
ns
100
ns
SCK↓ → SO
delay time
tKSO
SO0
SO1
SCK input mode
Output mode
Output mode
SCK output mode
SCK output mode
SCK output mode
2tsys + 250
ns
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 21 –
CXP847P60
Fig. 4. Serial transfer CH0, CH1 timing
tWHCS
CS0
CS1
0.8VDD
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
SI0
SI1
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
SO1
Output data
0.2VDD
– 22 –
CXP847P60
Serial transfer (CH2)
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Pin
tKCY
SCK2
SCK High and Low
level widths
tKH
tKL
SCK2
SI input setup time
(for SCK↑)
tSIK
SI2
SI input hold time
(for SCK↑)
tKSI
SI2
SCK↓ → SO delay time
tKSO
SO2
SCK cycle time
Conditions
Input mode
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 50
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Output mode
Input mode
Output mode
SCK input mode
200
ns
SCK output mode
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Serial transfer (CH2)
Item
(Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Symbol
Pin
tKCY
SCK2
SCK High and Low
level widths
tKH
tKL
SCK2
SI input setup time
(for SCK↑)
tSIK
SI2
SI input hold time
(for SCK↑)
tKSI
SI2
SCK↓ → SO delay time
tKSO
SO2
SCK cycle time
Conditions
Input mode
Min.
Max.
Unit
1000
ns
8000/fc
ns
400
ns
4000/fc – 100
ns
SCK input mode
100
ns
SCK output mode
200
ns
SCK input mode
200
ns
SCK output mode
100
ns
Output mode
Input mode
Output mode
SCK input mode
250
ns
SCK output mode
125
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.
– 23 –
CXP847P60
Fig. 5. Serial transfer CH2 timing
tKCY
tKL
tKH
0.8VDD
SCK2
0.2VDD
tSIK
tKSI
0.8VDD
SI2
Input data
0.2VDD
tKSO
0.8VDD
SO2
Output data
0.2VDD
– 24 –
CXP847P60
(3) A/D converter characteristics (Ta = –10 to +75°C, VDD = AVDD = 3.0 to 5.5V, Vss = AVSS = 0V reference)
Item
Symbol
Pin
Conditions
Min.
Typ.
Resolution
Linearity errror
Zero
transition voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Ta = 25°C
VDD = AVDD = AVREF
= 5.0V
VSS = AVSS = 0V
Zero
transition voltage
VZT∗1
Full-scale transition
voltage
VFT∗2
Convertion time
tCONV
tSAMP
Sampling time
8
Bits
±3
LSB
10
70
mV
4910
4970
5030
mV
±5
LSB
–10
6.5
70
mV
3215
3280
3345
mV
26/fADC∗3
6/fADC∗3
Reference input
voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
µs
AVDD – 0.5
AVDD
V
VDD = AVDD = 3.0 to 3.6V
AVDD – 0.3
AVDD
V
0
AVREF
V
AVREF
VDD = 5.5V
0.6
1.0
mA
VDD = 3.6V
0.4
0.7
mA
10
µA
Sleep mode
Stop mode
IREFS
µs
VDD = AVDD = 4.5 to 5.5V
Operation
mode
IREF
AVREF current
Unit
–50
Linearity errror
Ta = 25°C
VDD = AVDD = AVREF
= 3.3V
VSS = AVSS = 0V
Max.
Fig.6. Definition of A/D converter terms
∗1 VZT: Value at which the digital conversion value changes
from 00H to 01H and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 00F9H).
PS1 selected
fADC = fc
PS2 selected
fADC = fc/2
Digital conversion value
FFH
FEH
Linearity error
01H
00H
VFT
VZT
Analog input
– 25 –
CXP847P60
(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
External interruption
High, Low level width
tIH
tIL
INT0
INT1
INT2
INT3
INT4
NMI
Reset input Low level width
tRSL
RST
Conditions
Min.
Max.
Unit
1
µs
32/fc
µs
Fig. 7. Interruption input timing
tIH
INT0
INT1
INT2
INT3
INT4
NMI
(NMI is specified only for
the falling edge)
tIL
0.8VDD
0.2VDD
tIL
tIH
Fig. 8. RST input timing
tRSL
RST
0.2VDD
(5) Power-on reset∗1
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Symbol
Power supply rise time
tR
tOFF
Power supply cut-off time
Pin
Conditions
Power-on reset
VDD
Min.
Max.
Unit
0.05
50
ms
1
Repetitive power-on reset
∗1 Power-on reset function is selected by the mask option. See the Selection Guide for the mask option.
Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V.
Fig. 9. Power-on reset
4.5V
VDD
0.2V
0.2V
tR
tOFF
Turn the power on smoothly.
– 26 –
ms
CXP847P60
Appendix
Fig. 10. Recommended oscillation circuit for SPC700 Series
AAAA
AAAA
AAAA
(i) Main clock
EXTAL
XTAL
Rd
C1
C2
Manufacturer
RIVER ELETEC
CO., LTD.
Model
HC-49/U03
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
22 (15)
22 (15)
12.00
15
15
16.00
12
12
10.00
12.00
Rd (Ω)
Circuit
example
0
(i)
0
(i)
16.00
8.00
KINSEKI LTD.
HC-49/U (-S)
10.00
Selection Guide
Option item
Mask
CXP847P60Q-1-
CXP847P60R-1-
Reset pin pull-up resistor
Non-existent/Existent
Existent
Existent
Power-on reset function
Non-existent/Existent∗1
Existent
Existent
∗1 Power-on reset function "Existent" is not selected under the using condition in the range of VDD=3.0 to 4.5V.
– 27 –
CXP847P60
Characteristics Curve (Reference)
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
20
1/2 dividing mode
1/2 dividing mode
20.0
1/4 dividing mode
10.0
IDD – Supply current [mA]
Sleep mode
1.0
0.5
0.1
(100µA)
0.05
(50µA)
IDD – Supply current [mA]
1/16 dividing mode
5.0
15
1/4 dividing mode
10
5
1/16 dividing mode
0.01
(10µA)
Stop mode
Sleep mode
3
4
5
6
5
10
fc – System clock [MHz]
0
VDD – Supply voltage [V]
IDD vs. VDD
(fc = 12MHz, Ta = 25°C, Typical)
20.0
1/2 dividing mode
10.0
1/4 dividing mode
20
1.0
Sleep mode
0.5
0.1
(100µA)
0.05
(50µA)
IDD vs. fc
(VDD = 3.3V, Ta = 25°C, Typical)
15
1/16 dividing mode
IDD – Supply current [mA]
IDD – Supply current [mA]
5.0
16
10
1/2 dividing mode
5
1/4 dividing mode
0.01
(10µA)
1/16 dividing mode
Sleep mode
3
6
4
5
VDD – Supply voltage [V]
0 1
– 28 –
5
10
fc – System clock [MHz]
15
CXP847P60
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
15.8 ± 0.4
+ 0.4
14.0 – 0.01
17.9 ± 0.4
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 29 –