ILX137K
10700-pixel × 6-line CCD Linear Sensor (Color)
Description
The ILX137K is a reduction type CCD linear sensor
developed for color image scanner. This sensor
reads A4-size documents at a density of pseudo
2400DPI.
• Input clock voltage
• Operating temperature
• Storage temperature
15
7
–10 to +60
–30 to +80
1
1
1
1
1
1
φ2
1
24
φ1
φ1L'
2
23
φ2L
φ4
3
22
φ3
GND
4
21
φRS
VOUT-R
5
20
VDD
VOUT-G
6
19
VOUT-B
V
V
°C
°C
NC
7
18
NC
NC
8
17
NC
GND
9
16
φ1
φROG-B 10
15
φ2
φROG-R 11
14
φROG-G
NC 12
13
VDD
10700
10700
10700
10700
10700
10700
Absolute Maximum Ratings
• Supply voltage
VDD
Pin Configuration (Top View)
R (Sub)
R (Main)
G (Sub)
G (Main)
B (Sub)
B (Main)
Features
• Number of effective pixels:
64200 pixels (10700 pixels × 6)
• Pixel size: 2.4µm × 4µm (4µm pitch)
• Distance between line:
2 lines between the same color (8µm)
16 lines between different colors (64µm)
• On-chip microlens
Cylindrical lens (width 6µm)
• Single-sided readout
• Supply voltage:
Single 12V power supply
• Input clock pulse: CMOS 5V drive
• Number of output: 3 (R, G, B)
• Package:
24-pin Plastic-DIP
24 pin DIP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01651-PS
Block Diagram
VDD
φ4
φ1L'
VDD
φ2
φ2
20
3
2
13
1
15
D104
D83
Main Line (Blue)
S10700
S2
S3
S1
D82
D66
CCD register
Driver
10 φROG-B
Driver
14 φROG-G
Driver
11 φROG-R
D104'
Sub Line (Blue)
D83'
S10700'
S3'
S2'
S1'
D82'
D66'
VOUT-B 19
CCD register
OFD
D104
D83
S10700
S2
S3
S1
D82
Main Line (Green)
D104'
Sub Line (Green)
D83'
S10700'
S3'
S2'
S1'
D82'
6
D66'
VOUT-G
CCD register
OFD
D104
D83
S10700
S2
S3
S1
Main Line (Red)
D104'
D83'
Sub Line (Red)
S10700'
S3'
S2'
S1'
5
D82'
VOUT-R
D82
D66
CCD register
D66'
–2–
D66
CCD register
CCD register
OFD
4
21
GND φRS
22
23
9
16
24
φ3
φ2L
GND
φ1
φ1
ILX137K
ILX137K
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
φ2
Clock pulse input
13
VDD
12V power supply
2
φ1L'
Clock pulse input
14
φROG-G
Clock pulse input
3
φ4
Clock pulse input
15
φ2
Clock pulse input
4
GND
GND
16
φ1
Clock pulse input
5
VOUT-R
Signal output (red)
17
NC
NC
6
VOUT-G
Signal output (green)
18
NC
NC
7
NC
NC
19
VOUT-B
Signal output (blue)
8
NC
NC
20
VDD
12V power supply
9
GND
GND
21
φRS
Clock pulse input
10
φROG-B
Clock pulse input
22
φ3
Clock pulse input
11
φROG-R
Clock pulse input
23
φ2L
Clock pulse input
12
NC
NC
24
φ1
Clock pulse input
Recommended Supply Voltage
Item
VDD
Min.
Typ.
Max.
Unit
11.4
12.0
12.6
V
Input Pin Capacitance
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacitance of φ1, φ2
Cφ1, Cφ2
—
2350
—
pF
Input capacitance of φ1L', φ2L
Cφ1L', Cφ2L
—
20
—
pF
Input capacitance of φ3, φ4
Cφ3, Cφ4
—
20
—
pF
Input capacitance of φRS
CφRS
—
10
—
pF
Input capacitance of φROG
CφROG
—
10
—
pF
∗ φROG represents φROG-R, φROG-G and φROG-B.
Clock Frequency
Item
Symbol
Min.
Typ.
Max.
Unit
φ1, φ2, φ1L', φ2L
fφ1, fφ2, fφ1L', fφ2L
—
1
6
MHz
φ3, φ4
fφ3, fφ4
—
2
6
MHz
φRS
fφRS
—
2
6
MHz
Input Clock Voltage Conditions
Item
φ1L', φ2L, φ3, φ4
φ1, φ2, φRS, φROG
Min.
Typ.
Max.
Unit
High level
4.75
5.0
5.25
V
Low level
0
—
0.1
V
High level
4.75
5.0
5.25
V
Low level
0
—
0.5
V
–3–
ILX137K
Electro-optical Characteristics (Note 1)
Ta = 25°C, VDD = 12V, fφRS = 2MHz, Input clock = 5Vp-p, Light source = 3200K,
IR cut filter CM-500S (t = 1.0mm)
Item
Sensitivity
Symbol
Min.
Typ.
Max.
Red
RR
0.62
0.96
1.30
Green
RG
0.81
1.25
1.69
Blue
RB
0.54
0.84
1.14
Unit
Remarks
V/(lx . s)
Note 2
Sensitivity nonuniformity
PRNU
—
4
18
%
Note 3
Adjacent pixel difference
PDF
—
4
16
%
Note 4
Saturation output voltage
VSAT
1
1.5
—
V
Note 5
Overflow exposure
OE
3 × SEmin
—
—
Red
SER
—
1.56
—
Green
SEG
—
1.20
—
Blue
SEB
—
1.79
—
Dark voltage average
VDRK
—
0.1
Dark signal nonuniformity
DSNU
—
Image lag
IL
Current consumption
Note 6
lx . s
Note 7
2.0
mV
Note 8
0.6
4.0
mV
Note 9
—
0.02
—
%
Note 10
IVDD
—
18
35
mA
—
Total transfer efficiency
TTE
92
98
—
%
—
Output impedance
ZO
—
300
—
Ω
—
Offset level
VOS
5.0
6.5
8.0
V
Note 11
Offset level difference
∆VOS
—
—
100
mV
Note 12
Saturation exposure
Notes)
1. For each color, the black level of Main Line is defined as the average value of D66, D67 to D81, and the
black level of Sub Line is defined as the average value of D66', D67' to D81'. The following electro-optical
characteristics signal processing is performed.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
PRNU =
(VMAX – VMIN)/2
VAVE
× 100 [%]
Where the maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the
average output to VAVE.
4. PDF = (∆VMAX/VAVE) × 100 [%]
Here, VAVE is defined as the average output, and ∆VMAX, the maximum value of ∆Vi in the range of the
following pixel.
Red, green, blue pixel arrangement PDF is when i = 1 to 10699. However, the definition of ∆Vi is as follows.
∆Vi = ABS {VOUT (i) – VOUT (i + 1)}
VOUT (i) is signal output of an effective pixel (i pixel) and VOUT (i + 1) is of the adjacent pixel (i + 1 pixel).
–4–
ILX137K
5. Specifies at the minimum value of the saturation output voltage.
6. SEmin is the exposure at the minimum value (1V) of the saturation output voltage.
7. Saturation exposure is defined as in the following figure for each color.
SE = VSAT/R
8. For each color, Main Line is defined by the difference between the average value of D2 to D64 dummy
signal during no incident light and of D66 to D82, S1 to S700. Sub Line is defined by the difference
between the average value of D2' to D64' dummy signal during no incident light and of D66' to D82', S1' to
S10700'. Optical signal integration time τ int stands at 20ms.
9. For each color, calculate the difference as follows; the maximum and minimum values of the dark output
voltage of respective Main Line and Sub Line; the dark voltage average value of respective Main Line and
Sub Line. Then, the highest value is defined as dark signal nonuniformity. Optical signal integration time τ int
stands at 20ms.
10. VOUT = 500mV (Typ.)
11. Vos is defined as the output DC value when φRS is high.
12. For each color, the Main Line offset level of the optical black pixel is defined as Vos-main, the Sub Line
offset level, Vos-sub. Then, the offset level difference is defined as indicated below.
∆Vos = | Vos-main – Vos-sub |
∆Vos
–5–
Clock Timing Chart 1 (Using both Main Line and Sub Line)
φROG
5
φ1, φ1L'
φ2, φ2L
2
5
1
0
0
5
φ3
3
2
5
1
0
0
φ4
5
φRS
5
D104'
D104
D103'
D83'
D83
S10700'
S10700
S10700'
S1'
S1
D82'
D82
D66'
D66
D65'
D65
D2
VOUT
D1'
0
D1
–6–
0
Optical black
(16 pixels × 2)
Dummy signal
(82 pixels × 2)
Effective pixel signal
(10700 pixels × 2)
Dummy signal
(22 pixels × 2)
1-line output period
ILX137K
Note) The transfer pulse φ1, φ2, φ1L' and φ2L must have more than 10805 cycles.
φ3 and φ4 must have more than 21610 cycles.
Clock Timing Chart 2 (Using only Main Line)
φ1, φ3
φ2, φ4, φ2L
5
4
3
5
2
0
1
φROG
0
5
0
φRS
5
0
D95
D94
S2
S1
D93
D92
D91
D78
D77
D76
D3
D2
D1
–7–
S10700
0V
S10699
φ1L'
VOUT
Optical black
(16 pixels)
Dummy signal
(93 pixels)
Effective pixel signal
(10700 pixels)
Dummy signal
(22 pixels)
1-line output period
Note) The transfer pulse φ1, φ2, φ1L', φ2L, φ3 and φ4 have must more than 10816 cycles.
ILX137K
ILX137K
Clock Timing Chart 3
t5
t4
φROG
t2
t6
φ1
t7
t1
t3
φ2
t6
t7
Clock Timing Chart 4
t7
t6
t6
t7
t9
t8
t8
t9
φ1
φ2
φ1L'
φ2L
t15
t11
t10
t18
φ3
t16
t19
φ4
t10
t11 t12
t13
t17
φRS
t14
t21
t22
t20
Main Line
VOUT
Sub Line
φ1, φ2, φ1L' and φ2L Cross Point
φ1, φ1L' 5V
φ2, φ2L 0V
(1.5V and above)
(1.5V and above)
(1.5V and above)
(1.5V and above)
φ3 and φ4 Cross Point
φ3
5V
φ4
0V
–8–
ILX137K
Clock Pulse Recommended Timing
Item
Symbol
Min.
Typ.
Max.
Unit
φROG, φ1 pulse timing
t1
50
100
—
ns
φROG pulse high level period
t2
100
—
—
µs
φROG, φ1 pulse timing
t3
1200
1500
—
ns
φROG pulse rise time
t4
0
5
30
ns
φROG pulse fall time
t5
0
5
30
ns
φ1 pulse rise/φ2 pulse fall time
t6
0
20
60
ns
φ1 pulse fall/φ2 pulse rise time
t7
0
20
ns
φ1L' pulse rise/φ2L pulse fall time
t8
0
10
60
30∗1
φ1L' pulse fall/φ2L pulse rise time
t9
0
10
φ3 pulse rise/φ4 pulse fall time
t10
0
10
30∗1
30∗1
10
30∗1
ns
30∗1
ns
30∗1
ns
—
ns
—
ns
—
ns
φ3 pulse fall/φ4 pulse rise time
t11
0
ns
ns
ns
φRS pulse rise time
t12
0
10
φRS pulse fall time
t13
0
φRS pulse high level period
t14
20
10
100∗1
φ1L', φ2L – φ3, φ4 pulse timing 1
t15
0
φ1L', φ2L – φ3, φ4 pulse timing 2
t16
35
40
210∗1
φRS, φ3 pulse timing
t17
50
125∗1
—
ns
t18
35
250
—
ns
t19
35
250
—
ns
t20
—
30
—
ns
t21
—
10
—
ns
t22
—
30
—
ns
φ3, φ4 pulse low level period
Signal output delay time
The recommended duty of φ1, φ2, φ1L', φ2L, φ3 and φ4 = 50%.
∗1 These timing is the recommended condition under fφRS = 2MHz.
–9–
Application Circuit
φ1
IC1
φ2L
φ3
φRS
φROG-G
1kΩ
VOUT-B
Tr1
IC2
2Ω
0.1µF
19
NC
NC
φ1
φ2
φROG-G
NC
NC
GND
φROG-B
φROG-R
NC
1
2
3
4
5
6
7
8
9
10
11
12
2Ω
47µF/
16V
51Ω
30Ω
100Ω
100Ω
IC2
Tr1
IC1
φ4
100Ω
100Ω
IC2
φ1L'
VDD
VOUT-B
VOUT-G
13
VDD
14
VOUT-R
15
φRS
16
GND
17
φ3
18
φ4
20
φ2L
21
φ1L'
22
– 10 –
12V
100Ω
100Ω
10Ω
φ1
23
30Ω
φ2
24
51Ω
IC2
VOUT-R
1kΩ
Tr1
VOUT-G
1kΩ
φROG-B φROG-R
IC1: 74AC04
IC2: 74HC04
Tr1: 2SC2785
φ2
ILX137K
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX137K
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the
following protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Packages
The following points should be observed when handling and installing packages.
a) Remain within the following limits when applying static load to the package:
(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter
of the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm
Cover glass
Plastic portion
29N
39N
0.9Nm
29N
Adhesive
Ceramic portion
(1)
(2)
(3)
(4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the package to crack or dust to be generated.
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating.
(4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer.
(5) Applying the metal a crash or a rub against the plastic portion.
Note that the preceding notes should also be observed when removing a component from a board
after it has already been soldered.
d) The notch of the plastic portion is used for directional index, and that can not be used for reference of
fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap
with the notch of the plastic portion.
– 11 –
ILX137K
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering
iron with a ground wire and solder each pin in less then 2 seconds. For repairs and remount, cool
sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to
scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 12 –
Package Outline
Unit: mm
24Pin DIP ( 400mil )
0˚ to 9˚
55.7 ± 0.3
42.8 ( 4µm × 10700Pixels )
24
5.0 ± 0.3
V
H
No.1Pixel ( Main Green )
0.25
10.0 ± 0.3
13
10.16
7.4 ± 0.3
12
1
(8.893)
5.334
0.46
0.3
PACKAGE STRUCTURE
Plastic, Ceramic
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
5.43g
DRAWING NUMBER
LS-B36(E)
M
1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
ILX137K
Sony Corporation
PACKAGE MATERIAL
4.28 ± 0.5
3.58
4.0 ± 0.5
– 13 –
1.778