ILX128MA
5350-pixel × 6-line CCD Linear Sensor (Color)
For the availability of this product, please contact the sales office.
Description
The ILX128MA is a reduction type CCD linear
sensor developed for color image scanner, and has
shutter function per each color. This sensor reads
A3-size documents at a density of pseudo 800DPI,
and reads A4-size at a density of pseudo 1200DPI.
Features
• Number of effective pixels:
32100 pixels (5350 pixels × 6)
• Pixel size:
6µm × 8µm (8µm pitch)
• Distance between line:
48µm (6 lines: Rsub – Rmain,
Rmain – Gsub, Gsub – Gmain,
Gmain – Bsub, Bsub – Bmain)
• Single-sided readout
• Shutter function
• Ultra-high sensitivity/Ultra-low lag
• Supply voltage:
Single 12V power supply
• Input clock pulse: CMOS 5V drive
• Number of output: 3 (R, G, B)
• Package:
24-pin Plastic-DIP
15
7
–10 to +55
–30 to +80
1
1
1
1
1
1
Pin Configuration (Top View)
1
24
φ4
φ1L'
2
23
φ2L
φRS
3
22
φ3
VOUT-R
4
21
GND
VOUT-G
5
20
VOUT-B
VDD
6
19
NC
NC
7
18
NC
NC
8
17
VDD
GND
9
16
NC
φ2 10
15
φ1
φSHUT-B 11
14
φROG
φSHUT-G 12
13
φSHUT-R
R (Sub)
R (Main)
G (Sub)
G (Main)
B (Sub)
B (Main)
φ1L
V
V
°C
°C
5350
5350
5350
5350
5350
5350
Absolute Maximum Ratings
• Supply voltage
VDD
• Input clock voltage
• Operating temperature
• Storage temperature
24 pin DIP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00462-PS
4
VOUT-R
21
GND
9
GND
22
φ3
3
φRS
24
17
6
φ1L'
2
φ1L
1
φ2L
23
S1
CCD register
Sub Line (Red)
CCD register
Main Line (Red)
CCD register
Sub Line (Green)
CCD register
Main Line (Green)
CCD register
Sub Line (Blue)
CCD register
Main Line (Blue)
φ1
15
10
φ2
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Driver
14 φROG
13 φSHUT-R
12 φSHUT-G
11 φSHUT-B
Note) D24 and D24' are the start pixels for the optical black of Main Line and Sub Line. (These are not pixels immediately before multiplex.)
5
VOUT-G
VOUT-B 20
φ4
VDD
VDD
D24
D24
D24
D24'
D24'
D24'
D40
D40
D40
D40'
D40'
D40'
S1
S1
S2
S2
S2
S1'
S1'
S1'
D44'
D44'
S3
S3
S3
S2'
S2'
S2'
S5350
S5350
S5350
D41
D41
D41
D44
D44
D44
S3'
S3'
S3'
D41'
D41'
D41'
S5350'
S5350'
S5350'
–2–
D44'
Block Diagram
ILX128MA
ILX128MA
Pin Description
Pin
No.
Symbol
Description
Pin
No.
Symbol
Description
1
φ1L
Clock pulse input
13
φSHUT-R
Clock pulse input
2
φ1L'
Clock pulse input
14
φROG
Clock pulse input
3
φRS
Clock pulse input
15
φ1
4
VOUT-R
Signal output (red)
16
NC
Clock pulse input
NC∗
5
VOUT-G
Signal output (green)
17
VDD
12V power supply
6
VDD
12V power supply
18
NC
NC
7
NC
NC
19
NC
NC
8
NC
NC
20
VOUT-B
Signal output (blue)
9
GND
GND
21
GND
GND
10
φ2
Clock pulse input
22
φ3
Clock pulse input
11
φSHUT-B
Clock pulse input
23
φ2L
Clock pulse input
12
φSHUT-G
Clock pulse input
24
φ4
Clock pulse input
∗ Connecting to GND is recommended.
Recommended Supply Voltage
Item
VDD
Min.
Typ.
Max.
Unit
11.4
12
12.6
V
Input Pin Capacity
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φ1, φ2
Cφ1, Cφ2
—
1530
—
pF
Input capacity of φ1L, φ1L', φ2L
Cφ1L, Cφ1L', Cφ2L
—
20
—
pF
Input capacity of φ3, φ4
Cφ3, Cφ4
—
20
—
pF
Input capacity of φRS
CφRS
—
20
—
pF
Input capacity of φROG
CφROG
—
10
—
pF
Input capacity of φSHUT∗1
CφSHUT
—
10
—
pF
∗1 φSHUT represents φSHUT-R, φSHUT-G and φSHUT-B.
–3–
ILX128MA
Clock Frequency
Item
Symbol
Min.
Typ.
Max.
Unit
φ1, φ2, φ1L, φ1L', φ2L
fφ1, fφ2, fφ1L, fφ1L', fφ2L
—
1
3
MHz
φ3, φ4
fφ3, fφ4
—
2
6
MHz
φRS
fφRS
—
2
6
MHz
Min.
Typ.
Max.
Unit
High level
4.75
5.0
5.25
V
Low level
0
—
0.1
V
High leve
4.75
5.0
5.25
V
Low level
0
—
0.5
V
Input Clock Voltage Condition
Item
φ1L, φ1L', φ2L, φ3, φ4
φ1, φ2, φRS, φROG, φSHUT
–4–
ILX128MA
Electrooptical Characteristics (Note 1)
(Ta = 25°C, VDD = 12V, fφRS = 2MHz, Input clock = 5Vp-p,
Light source = 3200K, IR cut filter CM-500S (t = 1mm))
Symbol
Min.
Typ.
Max.
Red
RR
1.33
1.9
2.47
Green
RG
3.01
4.3
5.59
Blue
RB
1.82
2.6
3.38
Item
Sensitivity
Unit
Remarks
V/(lx · s)
Note 2
Sensitivity nonuniformity
PRNU
—
4
15
%
Note 3
Adjacent pixel difference
PDF
—
4
15
%
Note 4
Saturation output voltage
VSAT
2
3
—
V
Note 5
Overflow exposure
OE
2 × SEmin
—
—
Red
SER
0.8
1.6
—
Green
SEG
0.4
0.7
—
Blue
SEB
0.6
1.2
—
Dark voltage average
VDRK
—
0.3
Dark signal nonuniformity
DSNU
—
Image lag
IL
Current consumption
Note 6
lx · s
Note 7
2.0
mV
Note 8
1.5
5.0
mV
Note 9
—
0.02
—
%
Note 10
IVDD
—
32
50
mA
—
Total transfer efficiency
TTE
92
98
—
%
—
Output impedance
ZO
—
250
—
Ω
—
Offset level
VOS
4.7
6.2
7.7
V
Note 11
Offset level difference
∆VOS
—
40
200
mV
Note 12
Dynamic range
DR
1000
10000
—
—
Note 13
Saturation exposure
Note)
1. For each color, the black level of Main Line is defined as the average value of D24, D25 to D39, and the
black level of Sub Line is defined as the average value of D24', D25' to D39'. The following electrooptical
characteristics signal processing is performed.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
PRNU =
4.
(VMAX – VMIN)/2
× 100 [%]
VAVE
Where the maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the
average output to VAVE.
PDF = (∆VMAX/VAVE) × 100 [%]
Here, VAVE is defined as the average output, and ∆VMAX, the maximum value of ∆Vi in the range of the
following pixel.
Red, green, blue pixel arrangement PDF is when i = 1 to 5349. However, the definition of ∆Vi is as follows.
∆Vi = ABS {VOUT (i) – VOUT (i + 1)}
VOUT (i) is signal output of an effective pixel (i pixel) and VOUT (i + 1) is of the adjacent pixel (i + 1 pixel).
–5–
ILX128MA
5.
6.
7.
8.
Specifies at the minimum value of the saturation output voltage.
SEmin is the exposure at the minimum value (2V) of the saturation output voltage.
Saturation exposure is defined as in the right figure. SE = VSAT/R
For each color, Main Line is defined by the difference between the average value of D2 to D22 dummy
signal during no incident light and of D24 to D40, S1 to S5350. Sub Line is defined by the difference
between the average value of D2' to D22' dummy signal during no incident light and of D24' to D40', S1' to
S5350'.
Optical signal integration time τint stands at 10ms.
9. For each color, calculate the difference as follows; the maximum and minimum values of the dark output
voltage of respective Main Line and Sub Line; the dark voltage average value of respective Main Line and
Sub Line. Then, the highest value is defined as dark signal nonuniformity.
Optical signal integration time τint stands at 10ms.
10. VOUT = 500mV (Typ.)
11. Vos is defined as the output DC value when φRS is high.
12. For each color, the Main Line offset level of the optical black pixel is defined as Vos-main, the Sub Line
offset level, Vos-sub. Then, the offset level difference is defined as indicated below.
∆VOS = | VOS-main – VOS-sub |
φ1L and φ1L' are set to the same clock input.
∆Vos
13. Dynamic range is defined as follows.
DR = VSAT/VDRK
When the optical signal integration time is shorter, the dynamic range gets wider because the optical
signal integration time is in proportion to the dark voltage.
–6–
VOUT
φRS
φ4
φ3
φ2, φ2L
φ1, φ1L
φ1L'
0
5
0
5
0
5
0
0
5
5
1
–7–
D40
D24'
D24
D23'
D23
S5350
S1'
Effective pixel signal
(5350 pixels × 2)
S5349'
D40'
1-line output period (5394 pixels × 2)
Dummy signal (30 pixels + 25 pixels × 2)
Optical black (16 pixels × 2)
D44
D43'
D41'
Dummy signal
(4 pixels × 2)
S1
Note) The transfer pulse φ1, φ2, φ1L, φ1L' and φ2L must have more than 5394 cycles.
φ3 and φ4 must have more than 10788 cycles.
1
0
2
2
D1
5
3
D1'
φROG
4
D2
Clock Timing Chart 1
ILX128MA
D44'
D41
S5350'
–8–
φSHUT
φRS
φ4
φ3
φ2, φ2L
φ1, φ1L
φ1L'
4
Note) Shutter pulse must not be high to low level or low to high level during effective pixel period.
0
0
5
5
0
5
0
5
0
0
5
5
0
1
1
5
2
2
φROG
3
Clock Timing Chart 2 (shutter operation)
Integration time
ILX128MA
ILX128MA
Clock Timing Chart 3
t4
t5
φROG
t2
t6
φ1
t7
t1
t3
φ2
t7
t6
Clock Timing Chart 4
t7
t6
t6
t7
t9
t8
t8
t9
φ1
φ2
φ1L
φ1L'
φ2L
t15
t11
t10
t18
φ3
t19
,
,
φ4
t16
t10
t11 t12
t13
t17
φRS
t14
t21
VOUT
t22
t20
Main Line
Sub Line
φ1 and φ2 Cross Point
φ1
5V
φ2
0V
1.5V or more
1.5V or more
1.5V or more
1.5V or more
φ3 and φ4 Cross Point
φ3
5V
φ4
0V
–9–
ILX128MA
Clock Pulse Recommended Timing
Symbol
Item
Min.
Typ.
Max.
Unit
φROG, φ1 pulse timing
t1
50
100
—
ns
φROG pulse high level period
t2
1200
1500
—
ns
φROG, φ1 pulse timing
t3
1200
1500
—
ns
φROG pulse rise time
t4
0
5
10
ns
φROG pulse fall time
t5
0
5
10
ns
φ1 pulse rise/φ2 pulse fall time
t6
0
20
60
ns
φ1 pulse fall/φ2 pulse rise time
t7
0
20
ns
φ1L, φ1L' pulse rise/φ2L pulse fall time
t8
0
10
60
30∗1
φ1L, φ1L' pulse fall/φ2L pulse rise time
t9
0
10
φ3 pulse rise/φ4 pulse fall time
t10
0
10
φ3 pulse fall/φ4 pulse rise time
t11
0
10
φRS pulse rise time
t12
0
10
φRS pulse fall time
t13
0
φRS pulse high level period
t14
20
10
250∗1
φ1L', φ2L – φ3, φ4 pulse timing 1
t15
35
φ1L', φ2L – φ3, φ4 pulse timing 2
t16
35
40
210∗1
φRS, φ3 pulse timing
t17
50
t18
φ3, φ4 pulse low level period
Signal output delay time
30∗1
30∗1
ns
ns
ns
ns
30∗1
ns
—
ns
—
ns
—
ns
125∗1
—
ns
35
250
—
ns
t19
35
250
—
ns
t20
—
35
—
ns
t21
—
8
—
ns
t22
—
35
—
ns
The recommended duty of φ1, φ2, φ1L, φ2L, φ3 and φ4 = 50%.
∗1 These timing is the recommended condition under fφRS = 2MHz.
– 10 –
30∗1
30∗1
ns
ILX128MA
Application Circuit∗1
φ4
φ2L
φ1 φROG
φ3
VOUT-B
IC2
10Ω
10Ω
10Ω
2Ω
21
NC
NC
VDD
NC
φ1
φROG
φSHUT-R
VDD
NC
NC
GND
φ2
φSHUT-B
φSHUT-G
13
VOUT-B
14
VOUT-G
15
GND
16
VOUT-R
17
φ3
18
φRS
19
φ2L
20
100Ω
φ1L'
22
100Ω
φ4
23
IC2
φ1L
24
12V
IC1
Tr1
10Ω
1
2
3
4
5
6
7
8
9
10
11
12
2Ω
0.1µF
φSHUT-R
5.1kΩ
47µF/ 10Ω
16V
10Ω
10Ω
100Ω
100Ω
10Ω
10Ω
IC1
IC2
Tr1
φ1L
φ1L'
φRS VOUT-R
5.1kΩ
IC2
Tr1
VOUT-G
5.1kΩ
φ2
φSHUT-G
φSHUT-B
IC1: 74AC04
IC2: 74HC04
Tr1: 2SC2785
∗1 Data rate fφRS = 2MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 11 –
ILX128MA
Example of Representative Characteristics (VDD = 12V, Ta = 25°C)
Spectral sensitivity characteristics
(Standard characteristics)
Relative sensitivity
1
0.8
0.6
0.4
0.2
0
400
500
450
550
600
Wavelength [nm]
Dark signal output temperature characteristics
(Standard characteristics)
700
650
Integration time output voltage characteristics
(Standard characteristics)
10
Output voltage rate
Output voltage rate
5
1
0.5
0.1
0
10
20
30
40
50
1
0.5
0.1
60
1
10
5
Ta – Ambient temperature [°C]
τ int – Integration time [ms]
Offset level vs. VDD characteristics
(Standard characteristics)
Offset level vs. temperature characteristics
(Standard characteristics)
12
12
Ta = 25°C
10
Vos – Offset level [V]
Vos – Offset level [V]
10
8
6
4
∆Vos
≈ 0.1
∆VDD
6
4
∆Vos ≈ 8mV/°C
∆Ta
2
2
0
11.4
8
12
0
12.6
0
10
20
30
40
50
Ta – Ambient temperature [°C]
VDD [V]
– 12 –
60
ILX128MA
Notes on Handling
1. Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
,
,
,
,
2) Notes on Handling CCD Packages
The following points should be observed when handling and installing plastic packages.
a) Remain within the following limits when applying static load to the package.
(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter
of the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm
Cover glass
Plastic portion
Ceramic portion
39N
(1)
Adhesive
29N
29N
0.9Nm
(2)
(3)
(4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the package to crack or dust to be generated.
(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating.
(4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer.
(5) Applying the metal a crash or a rub against the plastic portion.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
d) The notch of the plastic portion is used for directional index, and that can not be used for reference of
fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap
with the notch of the plastic portion.
3. Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount,
cool sufficiently.
c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering
tool, ground the controller. For the temperature control system, use a zero-cross type.
– 13 –
ILX128MA
4. Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch mirror surfaces by hand or have any object come in contact with mirror surfaces.
Should dirt stick to a mirror surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the mirror surfaces are grease stained. Be careful not to
scratch the mirror surfaces.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation on the mirror surfaces,
preheat or precool when moving to a room with great temperature differences.
5. Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 14 –
5.0 ± 0.3
4.0 ± 0.5
– 15 –
H
42.8(8µmX5350pixels)
55.7 ± 0.3
24pin SDIP(400mil)
1.778
1
LS-B27(E)
DRAWING NUMBER
42ALLOY
LEAD MATERIAL
5.43g
GOLD PLATING
LEAD TREATMENT
PACKAGE MASS
Plastic-Ceramic
PACKAGE MATERIAL
5.334
No.1Pixel (Green(main line))
24
PACKAGE STRUCTURE
V
7.6 ± 0.3
Unit: mm
0.46
12
13
0.3
M
0˚ to 9˚
10.16
4.28 ± 0.5
10.0 ± 0.3
3.58
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.
0.25
Package Outline
ILX128MA
Sony Corporation