WINBOND W78L51P-24

W78L51
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78L51 microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C51 microcontroller
series.
The W78L51 contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O port
(Port 4) and two additional external interrupts ( INT2 , INT3 ), two 16-bit timer/counters, one watchdog
timer and a serial port. These peripherals are supported by a seven-source, two-level interrupt
capability. There are 128 bytes of RAM and an 4K byte mask ROM for application programs.
The W78L51 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• Fully static design
• Supply voltage of 1.8V to 5.5V
• DC-24 MHz operation
• 128 bytes of on-chip scratchpad RAM
• 4K bytes of on-chip mask ROM
• 64K bytes program memory address space
• 64K bytes data memory address space
• Four 8-bit bidirectional ports
• Two 16-bit timer/counters
• One full duplex serial port
• Seven-source, two-level interrupt capability
• One extra 4-bit bit-addressable I/O port
• Two additional external interrupts INT2 / INT3
• Watchdog timer
• EMI reduction mode
• Built-in power management
• Code protection
• Packages:
− DIP 40: W78L51-24
− PLCC 44: W78L51P-24
− QFP 44: W78L51F-24
-1-
Publication Release Date: January 1999
Revision A2
W78L51
PIN CONFIGURATIONS
40-Pin DIP (W78L51)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
9
10
11
12
13
32
31
30
29
28
27
26
14
15
16
17
18
19
20
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
25
24
23
22
21
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
6 5 4 3 2 1 44 43 42 41 40
39
38
37
9
36
10
35
11
34
33
32
12
13
14
15
31
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
/
I
A
N
D
T
0
3
,
,
P P P P P P
P
1 1 1 1 1 4 V 0
. . . . . . D .
4 3 2 1 0 2 D 0
A
D
3
,
P
0
.
3
7
8
P
3
.
6
,
/
W
R
P0.0, AD0
P0.1, AD1
P0.2, AD2
44-Pin QFP (W78L51F)
44-Pin PLCC (W78L51P)
/
I
N
T
3
,
P P P P P P
1 1 1 1 1 4 V
. . . . . . D
4 3 2 1 0 2 D
VDD
P1.5
P1.6
P1.7
RST
RXD, P3.0
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
INT2, P4.3
TXD, P3.1
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
P2.6, A14
P2.5, A13
P
2
.
4
,
A
1
2
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
1
2
P
3
.
6
,
/
W
R
-2-
A
D
1
,
P
0
.
1
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P P
T S 4 2 2
A S . . .
L
0 0 1
1
, ,
A A
8 9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
W78L51
PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
ALTERNATE FUNCTION
P3.0
RXD Serial Receive Data
P3.1
TXD Serial Transmit Data
P3.2
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
P3.4
T0 Timer 0 Input
P3.5
T1 Timer 1 Input
P3.6
WR Data Write Strobe
P3.7
RD Data Read Strobe
P4.0−P4.3
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ).
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
-3-
Publication Release Date: January 1999
Revision A2
W78L51
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state during
reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
Port 1
Latch
ACC
B
INT2
Port 0
Interrupt
INT3
T1
Latch
T2
Port
0
P0.0
~
P0.7
DPTR
Timer
0
Stack
Pointer
PSW
ALU
Temp Reg.
Timer
1
PC
Incrementor
UART
Addr. Reg.
P3.0
~
P3.7
Port
3
Port 3
SFR RAM
Address
Instruction
Decoder
&
Sequencer
Latch
128bytes
RAM & SFR
Bus & Clock
Controller
P4.0
~
P4.3
Port
4
Port 2
Latch
4KB
ROM
Port 4
Latch
Watchdog
Timer
Oscillator
XTAL1
Reset Block
XTAL2 ALE PSEN
RST
-4-
Power control
VDD
GND
Port
2
P2.0
~
P2.7
W78L51
FUNCTIONAL DESCRIPTION
The W78L51 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.
Timers 0, 1
Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1
and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0, 1.
Clock
The W78L51 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78L51 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78L51 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input high level of greater than 3.5 volts when VDD = 5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L51 is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
-5-
Publication Release Date: January 1999
Revision A2
W78L51
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts
INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt informations:
INTERRUPT
SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
03H
0 (highest)
IE.0
TCON.0
Timer/Counter 0
0BH
1
IE.1
-
External Interrupt 1
13H
2
IE.2
TCON.2
Timer/Counter 1
1BH
3
IE.3
-
Serial Port
23H
4
IE.4
-
External Interrupt 2
33H
5
XICON.2
XICON.0
External Interrupt 3
3BH
6 (lowest)
XICON.6
XICON.3
-6-
W78L51
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 /
INT3 ).
Example: P4
REG 0D8H
MOV
P4, #0AH
; Output data "A" through P4.0−P4.3.
MOV
A, P4
; Read P4 status to Accumulator.
SETB
P4.0
; Set bit P4.0
CLR
P4.1
; Clear bit P4.1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a flag is set, and a system reset can also be caused if it is enabled. The main use of
the Watchdog timer is as a system monitor. This is important in real-time control applications. In case
of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If
this is left unchecked the entire system may crash. The watchdog time-out selection will result in
different time-out values depending on the clock speed. The Watchdog timer will de disabled on
reset. In general, software should restart the Watchdog timer to put it into a known state. The control
bits that support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
3
2
1
0
ENW
CLRW
WIDL
-
-
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2
0
0
0
0
1
1
1
1
PS1
0
1
0
1
0
0
1
1
PS0
0
0
1
1
0
1
0
1
PRESCALER SELECT
2
4
8
16
32
64
128
256
-7-
Publication Release Date: January 1999
Revision A2
W78L51
The time-out period is obtained using the following formula:
1
× 2 14 × PRESCALER × 1000 × 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL
IDLE
EXTERNAL
RESET
OSC
PRESCALER
1/12
INTERNAL
RESET
14-BIT TIMER
CLEAR
CLRW
Watchdog Timer Block Diagram
Typical Watchdog time-out period when OSC = 20 MHz
PS2 PS1 PS0
0 0
0
0 1
0
0 0
1
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
WATCHDOG TIME-OUT PERIOD
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Reduce EMI Emission
Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space.
AUXR - Auxiliary Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
AO
Mnemonic: AUXR
AO:
Address: 8Eh
Turn off ALE signal.
-8-
W78L51
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VCC−VSS
-0.3
+7.0
V
Input Voltage
VIN
VSS -0.3
VCC +0.3
V
Operating Temperature
TA
0
70
°C
Storage Temperature
TST
-55
+150
°C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
(VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
PECIFICATION
MIN.
MAX.
UNIT
TEST CONDITIONS
Operating Voltage
VDD
1.8
5.5
V
Operating Current
IDD
-
20
mA
No load, VDD = 5.5V, 20 MHz
-
3
mA
No load, VDD = 2.0V, 16 MHz
-
6
mA
VDD = 5.5V, Fosc = 20 MHz
-
1.5
mA
VDD = 2.0V, Fosc = 16 MHz
-
50
µA
VDD = 5.5V, Fosc = 20 MHz
-
20
µA
VDD = 2.0V, Fosc = 16 MHz
-50
+10
µA
VDD = 5.5V
Idle Current
Power Down Current
Input Current
IIDLE
IPWDN
IIN1
P1, P2, P3, P4
Input Current
VIN = 0V or VDD
IIN2
-10
+300
µA
RST
Input Leakage Current
0 < VIN < VDD
ILK
-10
+10
µA
VDD = 5.5V
0V < VIN < VDD
P0, EA
Logic 1 to 0 Transition
Current
VDD = 5.5V
ITL [*4]
-500
-
µA
VDD = 5.5V
VIN = 2.0V
P1, P2, P3, P4
Input Low Voltage
VIL1
P0, P1, P2, P3, P4, EA
Input Low Voltage
RST[*1]
VIL2
0
0.8
V
VDD = 4.5V
0
0.5
V
VDD = 2.0V
0
0.8
V
VDD = 4.5V
0
0.3
V
VDD = 2.0V
-9-
Publication Release Date: January 1999
Revision A2
W78L51
DC Characteristics, continued
PARAMETER
Input Low Voltage
SYM.
VIL3
XTAL1 [*3]
Input High Voltage
VIH1
P0, P1, P2, P3, P4, EA
Input High Voltage
VIH2
RST[*1]
Input High Voltage
VIH3
XTAL1 [*3]
Output Low Voltage
VOL1
P1, P2, P3, P4
Output Low Voltage
VOL2
P0, ALE, PSEN [*2]
Sink Current
ISK1
P1, P2, P3, P4
Sink Current
ISK2
P0, ALE, PSEN
Output High Voltage
VOH1
P1, P2, P3, P4
Output High Voltage
VOH2
P0, ALE, PSEN [*2]
Source Current
ISR1
P1, P2, P3, P4
Source Current
P0, ALE, PSEN
ISR2
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
0
0.8
V
VDD = 4.5V
0
0.6
V
VDD = 2.0V
2.0
VDD +0.2
V
VDD = 5.5V
1.4
VDD +0.2
V
VDD = 2.0V
3.5
VDD +0.2
V
VDD = 5.5V
1.7
VDD +0.2
V
VDD = 2.0V
3.5
VDD +0.2
V
VDD = 5.5V
1.6
VDD +0.2
V
VDD = 2.0V
-
0.45
V
VDD = 4.5V, IOL = +2 mA
-
0.25
V
VDD = 2.0V, IOL = +1 mA
-
0.45
V
VDD = 4.5V, IOL = +4 mA
-
0.25
V
VDD = 2.0V, IOL = +2 mA
4
9
mA
VDD = 4.5V, Vin = 0.45V
1.8
5.4
mA
VDD = 2.0V, Vin = 0.45V
8
16
mA
VDD = 4.5V, Vin = 0.45V
4.5
9
mA
VDD = 2.0V, Vin = 0.45V
2.4
-
V
VDD = 4.5V, IOH = -100 µA
1.4
-
V
VDD = 2.0V, IOH = -8 µA
2.4
-
V
VDD = 4.5V, IOH = -400 µA
1.4
-
V
VDD = 2.0V, IOH = -200 µA
-100
-250
µA
VDD = 4.5V, Vin = 2.4V
-10
-30
µA
VDD = 2.0V, Vin = 1.4V
-8
-16
mA
VDD = 4.5V, Vin = 2.4V
-1.0
-2.4
mA
VDD = 2.0V, Vin = 1.4V
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and /PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
- 10 -
W78L51
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T CH
T CL
F OP,
PARAMETER
T CP
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
FOP
0
-
24
MHz
1
Clock Period
Clock High
TCP
TCH
25
10
-
-
nS
nS
2
3
Clock Low
TCL
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
TAAS
1 TCP-∆
-
-
nS
4
Address Hold from ALE Low
TAAH
1 TCP-∆
-
-
nS
1, 4
ALE Low to PSEN Low
TAPL
1 TCP-∆
-
-
nS
4
PSEN Low to Data Valid
TPDA
-
-
2 TCP
nS
2
Data Hold after PSEN High
TPDH
0
-
1 TCP
nS
3
Data Float after PSEN High
ALE Pulse Width
TPDZ
0
-
1 TCP
nS
TALW
2 TCP-∆
2 TCP
-
nS
4
PSEN Pulse Width
TPSW
3 TCP-∆
3 TCP
-
nS
4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
- 11 -
Publication Release Date: January 1999
Revision A2
W78L51
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
TDAR
3 TCP-∆
-
3 TCP+∆
nS
1, 2
RD Low to Data Valid
TDDA
-
-
4 TCP
nS
1
Data Hold from RD High
TDDH
0
-
2 TCP
nS
Data Float from RD High
TDDZ
0
-
2 TCP
nS
RD Pulse Width
TDRD
6 TCP-∆
6 TCP
-
nS
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
TDAW
3 TCP-∆
-
3 TCP+∆
nS
Data Valid to WR Low
TDAD
1 TCP-∆
-
-
nS
Data Hold from WR High
TDWD
1 TCP-∆
-
-
nS
WR Pulse Width
TDWR
6 TCP-∆
6 TCP
-
nS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
TPDS
1 TCP
-
-
nS
Port Input Hold from ALE Low
TPDH
0
-
-
nS
Port Output to ALE
TPDA
1 TCP
-
-
nS
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
ITEM
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 12 -
2
W78L51
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
TALW
ALE
TAPL
PSEN
TPSW
TAAS
PORT 2
TPDA
TAAH
TPDH, TPDZ
PORT 0
A0-A7
Code
A0-A7
Data
Code
A0-A7
Data
S5
S1
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S6
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
T DAR
T DDA
T DDH, TDDZ
RD
TDRD
- 13 -
Publication Release Date: January 1999
Revision A2
W78L51
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
A0-A7
DATA OUT
T DWD
TDAD
WR
T DWR
T DAW
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
T PDA
T PDH
DATA OUT
PORT
INPUT
SAMPLE
- 14 -
S3
W78L51
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
VDD
VDD
31
19
10 u
R
C1
XTAL1
18
XTAL2
9
RST
12
13
14
15
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
CRYSTAL
8.2 K
EA
C2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
GND 1
11
OC
G
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
GND
20
22
A0
A1
A2
A3
A4
A5
A6
A7
74HC373
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CE
OE
27512
W78L51
Figure A
CRYSTAL
C1
C2
R
16 MHz
30P
30P
−
24 MHz
15P
15P
33 MHz
10P
10P
−
6.8K
40 MHz
5P
5P
4.7K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 15 -
Publication Release Date: January 1999
Revision A2
W78L51
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V DD
V DD
31
10 u
19
EA
XTAL1
18
XTAL2
9
RST
12
13
14
15
INT0
OSCILLATOR
8.2 K
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
RD
17
16
29
30
11
10
WR
PSEN
ALE
TXD
RXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
11
OC
G
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND
20
22
27
CE
OE
A0
A1
A2
A3
A4
A5
A6
A7
74HC373
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
WR
20256
W78L51
Figure B
PACKAGE DIMENSIONS
40-pin DIP
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
a
1
eA
S
20
Dimension in inch
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
5.334
0.210
0.010
0.254
0.150
0.155
0.160
3.81
3.937
4.064
0.016
0.018
0.022
0.406
0.457
0.559
0.048
0.050
0.054
1.219
1.27
1.372
0.008
0.010
0.014
0.203
0.254
0.356
2.055
2.070
52.20
52.58
0.600
0.610
14.986
15.24
15.494
0.590
0.540
0.545
0.550
13.72
13.84
13.97
0.090
0.100
0.110
2.286
2.54
2.794
0.120
0.130
0.140
3.048
3.302
3.556
15
0
0.670
16.00
16.51
17.01
0
0.630
0.650
15
0.090
Notes:
E
S
c
A A2
A1
Base Plane
Seating Plane
L
B
B1
e1
a
- 16 -
eA
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
. parting line.
are determined at the mold
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
2.286
W78L51
Package Dimensions, continued
44-pin PLCC
HD
D
6
1
44
40
Symbol
7
39
E
17
HE
GE
29
18
28
c
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.185
4.699
0.508
0.020
0.145
0.150
0.155
3.683
3.81
3.937
0.026
0.028
0.032
0.66
0.711
0.813
0.016
0.018
0.022
0.406
0.457
0.559
0.008
0.010
0.014
0.203
0.254
0.356
0.648
0.653
0.658
16.46
16.59
16.71
0.648
0.653
0.658
16.46
16.59
16.71
0.050
1.27
BSC
BSC
16.00
0.590
0.610
0.630
14.99
15.49
0.590
0.610
0.630
14.99
15.49
16.00
0.680
0.690
0.700
17.27
17.53
17.78
0.680
0.690
0.700
17.27
17.53
17.78
0.090
0.100
0.110
2.296
2.54
2.794
0.10
0.004
L
Notes:
A2 A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
θ
e
b
b1
Seating Plane
A1
y
GD
44-pin QFP
HD
Symbol
34
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
33
1
E HE
11
12
e
Dimension in mm
Dimension in inch
D
44
b
22
Min. Nom. Max.
Min. Nom.
Max.
---
---
---
---
0.002
0.01
0.02
0.05
0.25
0.5
0.075
0.081
0.087
1.90
2.05
2.20
0.01
0.014
0.018
0.25
0.35
0.45
0.004
0.006
0.010
0.101
0.152
0.254
0.390
0.394
0.398
9.9
10.00
10.1
0.390
0.394
0.398
9.9
10.00
10.1
0.025
0.031
0.036
0.635
0.80
0.952
0.510
0.520
0.530
12.95
13.2
13.45
13.45
---
---
0.510
0.520
0.530
12.95
13.2
0.025
0.031
0.037
0.65
0.8
0.95
0.051
0.063
0.075
1.295
1.6
1.905
0.08
0.003
0
7
0
7
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
c
A2 A
A1
Seating Plane
See Detail F
y
θ
L
L1
Detail F
- 17 -
Publication Release Date: January 1999
Revision A2
W78L51
Headquarters
Winbond Electronics (H.K.) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792697
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 18 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798