PRELIMINARY W986432DH 512K × 4 BANKS × 32 BITS SDRAM GENERAL DESCRIPTION W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology, W986432DH delivers a data bandwidth of up to 800M bytes per second (5). For different application, W986432DH is sorted into four speed grades: -5, -55, -6, -7,-8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in high performance applications. FEATURES • • • • • • • • • • • • • 3.3V ±0.3V power supply 524288 words × 4 banks × 32 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page Sequential and Interleave burst Burst read, single write operation Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 86-pin TSOP II, 400 mil - 0.50 -1- Publication Release Date: May 2000 Revision A0 PRELIMINARY W986432DH 512K × 4 BANKS × 32 BITS SDRAM VSS DQ24 43 VCC 44 VSSQ 42 DQ23 45 DQ25 41 VCCQ 46 DQ26 40 DQ22 47 VCCQ 39 DQ21 48 DQ27 38 VSS Q 49 DQ28 37 DQ20 50 VSSQ 36 DQ19 51 DQ29 35 VCCQ 52 DQ30 34 DQ18 53 VCCQ 33 DQ17 54 DQ31 32 VSS Q 55 NC 31 56 VSS DQ16 57 30 A3 DQM3 NC 58 29 VCC 59 28 DQM2 A4 27 A2 60 A5 26 A1 61 A6 25 A0 62 A7 24 63 A8 A10/AP 64 23 CKE A9 BS1 65 22 BS0 66 21 NC CLK 67 CS 20 NC 68 19 NC RAS 69 18 DQM1 CAS 70 17 VSS WE 71 16 NC DQM0 72 15 DQ8 VCC 73 14 VCCQ NC 74 13 DQ9 DQ7 75 12 DQ10 VSSQ 76 11 DQ11 VSSQ DQ6 77 10 DQ5 78 9 VCCQ DQ12 8 DQ4 79 VCCQ 7 DQ3 80 DQ13 6 VSS Q 81 DQ14 5 DQ2 82 VSSQ 4 DQ1 83 DQ15 3 VCCQ 84 2 DQ0 85 1 VCC 86 Vss PIN CONFIGURATION PIN DESCRIPTION PIN NAME A0−A10 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A10. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. DQ0−DQ31 Data Input/ Output Multiplexed pins for data output and input. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. CAS Column Address Strobe Referred to RAS WE Write Enable Referred to RAS -2- Publication Release Date: May 2000 Revision A0 W986432DH DQM0− DQM3 Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. VCC Power (+3.3V) Power for input buffers and logic circuit inside DRAM. VSS Ground Ground for input buffers and logic circuit inside DRAM. VCCQ Power (+3.3V) for Separated power from VCC, to improve DQ noise immunity. I/O buffer VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. NC No Connection No connection -3- Publication Release Date: May 2000 Revision A0 W986432DH BLOCK DIAGRAM CLK CLOCK BUFFER CKE CONTROL CS SIGNAL RAS GENERATOR COMMAND CAS DECODER COLUMN DECODER A10 MODE REGISTER A0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DATA CONTROL CIRCUIT DQ BUFFER DQ0 DQ31 COLUMN COUNTER DQM0~3 COLUMN DECODER CELL ARRAY BANK #2 COLUMN DECODER ROW DECODER REFRESH COUNTER ROW DECODER A9 BS0 BS1 CELL ARRAY BANK #0 COLUMN DECODER ROW DECODER ROW DECODER WE SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * 32 -4- CELL ARRAY BANK #3 SENSE AMPLIFIER W986432DH DC CHARACTERISTICS Absolute Maximum Rating PARAMETER Input, Column Output Voltage SYM. RATING -0.3 − VCC +0.3 UNIT V NOTES 1 VIN, VOUT Power Supply Voltage VCC, VCCQ -0.3 − 4.6 V 1 Operating Temperature TOPR 0 − 70 °C 1 Storage Temperature TSTG -55 − 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to 70°C) PARAMETER SYM. MIN. TYP. MAX. UNIT NOTE S VCC 3.0 3.3 3.6 V 2 VCCQ 3.0 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VCC +0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 UNIT Power Supply Voltage Power Supply Voltage (for I/O Buffer) Note: VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS CAPACITANCE (VDD = 3.3V, TA = 25 °C, f = 1 MHz) PARAMETER Input Capacitance (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , SYM. MIN. MAX. Ci 2.5 4 pf CCLK 2.5 4 pf Co 4 6.5 pf DQM, CKE) Input Capacitance (CLK) Input/Output capacitance (DQ0−DQ31) Note: These parameters are periodically sampled and not 100% tested -5- Publication Release Date: May 2000 Revision A0 W986432DH DC CHARACTERISTICS (VCC = 3.3V ±0.3V, TA = 0°~70°C) PARAMETER SYM. -5 -55 -6 -7 -8 MAX. MAX. MAX. MAX. MAX. UNIT NOTES 1 bank operation ICC1 TBD TBD TBD TBD TBD 3 CKE = VIH ICC2 TBD TBD TBD TBD TBD 3 Bank: inactive state CKE = VIL (Power Down mode) ICC2P TBD TBD TBD TBD TBD 3 Standby Current CKE = VIH ICC2S TBD TBD TBD TBD TBD CKE = VIL (Power Down mode) ICC2P TBD TBD TBD TBD TBD CKE = VIH ICC3 TBD TBD TBD TBD TBD CKE = VIL (Power Down mode) ICC3P TBD TBD TBD TBD TBD (tCK = min.) ICC4 TBD TBD TBD TBD TBD 3, 4 (tCK = min.) ICC5 TBD TBD TBD TBD TBD 3 (CKE = 0.2V) ICC6 TBD TBD TBD TBD TBD Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) BANK: inactive state No Operating Current mA S tCK = min., CS = VIH (min.) BANK: active state (4 banks) Burst Operating Current Read/Write command cycling Auto Refresh Current Auto refresh command cycling Self Refresh Current Self refresh mode PARAMETER Input Leakage Current SYMBOL MIN. MAX. UNIT II(L) -5 5 µA VO(L) -5 5 µA VOH 2.4 - V VOL - 0.4 V (0V ≤ VIN ≤ VCC, all other pins not under test = 0V) Output Leakage Current 7(Output disable, 0V ≤ VOUT ≤ VCCQ) LVTTL Output ″H″ Level Voltage (IOUT = -2 mA) LVTTL Output "L″ Level Voltage (IOUT = 2 mA) -6- NOTES W986432DH AC CHARACTERISTICS (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6.) PARAMETER Symbol -5 MIN -55 MAX MIN -6 MAX UNIT NOTE MAX Ref/Active to Ref/Active Command Period tRC 54 Active to precharge Command Period tRAS 40 Active to Read/Write Command Delay Time tRCD 14 15 18 Read/Write(a) to Read/Write(b)Command tCCD Period 1 1 1 Cycle Precharge to Active(b) Command Period tRP 14 15 18 ns Active(a) to Active(b) Command Period tRRD 10 10.8 12 Write Recovery Time tWR 7 7.5 7.5 CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 55 MIN 100000 5 tCK CL* = 3 40 5.4 42 ns 100000 6 7 1000 7.5 1000 7.5 1000 5 1000 5.4 1000 6 1000 CLK High Level tCH 2 2 CLK Low Level tCL 2 2 Access Time from CLK 60 100000 2 2 CL* = 2 tAC 4.5 5.5 5.5 CL* = 3 4.5 5 5 Output Data Hold Time tOH 2.75 Output Data High Impedance Time tHZ 2.75 2.75 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB Transition Time of CLK (Rise and Fall) tT Data-in-Set-up Time tDS 1 1.5 1.5 Data-in Hold Time tDH 0.5 0.5 0.5 Address Set-up Time tAS 1.3 1.5 1.5 Address Hold Time tAH 0.8 1 0.5 CKE Set-up Time tCKS 1.3 1.5 1.5 CKE Hold Time tCKH 0.8 1 0.5 Command Set-up Time tCMS 1 1.5 1.5 Command Hold Time tCMH 0.5 0.5 0.5 Refresh Time tREF Mode Register Set Cycle Time tRSC 5 2.75 2.75 5.4 0 2.75 6 0 0 5 0 5.4 0 6 0.5 10 0.5 10 0.5 10 64 10 64 10.8 -7- 64 12 ms ns Publication Release Date: May 2000 Revision A0 W986432DH AC CHARACTERISTICS (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6.) PARAMETER Symbol -7 MIN -8 MAX MIN UNIT NOTE MAX MAX Ref/Active to Ref/Active Command Period tRC 65 Active to precharge Command Period tRAS 45 Active to Read/Write Command Delay Time tRCD 20 20 Read/Write(a) to Read/Write(b)Command Period 1 1 Cycle ns tCCD 68 MIN 100000 48 ns 100000 Precharge to Active(b) Command Period tRP 20 20 Active(a) to Active(b) Command Period tRRD 14 20 Write Recovery Time CL* = 2 tWR 7.5 10 CLK Cycle Time CL* = 2 tCK 7.5 1000 10 1000 7 1000 8 1000 CL* = 3 7 CL* = 3 CLK High Level tCH 2 CLK Low Level tCL 2 Access Time from CLK CL* = 2 8 3 3 tAC CL* = 3 5.5 6 5 6 Output Data Hold Time tOH 3 Output Data High Impedance Time tHZ 3 3 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 7 0 8 Transition Time of CLK (Rise and Fall) tT 0.5 10 0.5 10 Data-in-Set-up Time tDS 0.5 7 3 8 0 2 Data-in Hold Time tDH 1 1 Address Set-up Time tAS 0.5 2 Address Hold Time tAH CKE Set-up Time tCKS CKE Hold Time Command Set-up Time 1 1 0.5 2 tCKH 1 1 tCMS 0.5 2 Command Hold Time tCMH 1 1 Refresh Time tREF Mode Register Set Cycle Time tRSC 64 14 -8- 64 16 ms ns W986432DH PACKAGE DIMENSIONS 86L TSOP (II)-400 mil 86 44 HE E 1 43 e b C D q L A2 A L1 A1 ZD Y SEATING PLANE Controlling Dimension: Millimeters DIMENSION (MM) DIMENSION (INCH) SYM. MIN. NOM. A1 A2 b D 22.12 E HE NOM. MAX. 0.047 0.006 0.002 0.039 0.27 0.21 0.007 0.005 22.22 22.62 0.871 0.875 0.905 10.06 10.16 10.26 0.396 0.400 0.404 11.56 11.76 11.96 0.455 0.463 0.471 e 0.50 0.40 0.50 0.011 0.008 0.020 0.60 0.016 0.80 Y ZD MIN. 1.00 0.17 0.12 L 0.15 0.05 c L1 MAX. 1.20 A 0.020 0.024 0.032 0.004 0.10 0.61 0.024 -9- Publication Release Date: May 2000 Revision A0 W986432DH Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 10 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.