APPLICATION NOTE A V A I L A B L E X20C16 AN56 X20C16 16K 2K x 8 Bit High Speed AUTOSTORE™ NOVRAM FEATURES DESCRIPTION • • The Xicor X20C16 is a 2K x 8 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E 2 PROM) and the AUTOSTORE feature which automatically saves the RAM contents to E2PROM at power-down. The X20C16 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C16 features a compatible JEDEC approved pinout for byte-wide memories, for industry standard RAMs, ROMs, EPROMs, and E2PROMs. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years. PIN CONFIGURATION PLASTIC CERDIP TSOP 26 AS 4 25 A8 A5 A4 5 24 A9 6 23 NC A3 A2 7 22 OE 8 X20C16 21 A1 A0 9 20 18 12 17 I/O2 VSS 13 16 14 15 I/O7 I/O6 I/O5 I/O4 I/O3 3826 FHD F02 3826 FHD F15.1 4 2 1 32 31 30 NC 1 28 A10 OE 2 27 CE A9 3 26 29 4 25 A6 5 A8 I/O7 I/O6 A8 6 28 AS 5 24 A9 27 NC 6 23 A4 7 WE I/O5 I/O4 A5 8 26 NC VCC 7 A3 9 25 8 OE NE A2 9 20 10 24 NC A1 A10 10 19 11 23 CE A7 A0 18 12 22 A6 11 NC I/O7 A5 12 21 13 14 15 16 17 18 19 20 I/O6 A4 A3 22 X20C16 I/O3 VSS I/O2 I/O1 A3 A4 A5 A6 A7 NC NE VCC VCC WE AS NC A8 A9 NC OE 19 11 CE SOIC 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10 I/O0 I/O1 A10 LCC PLCC AS 3 3826 ILL F17.2 17 I/O0 A0 13 16 A1 14 15 A2 X20C16 21 3826 FHD F03 I/O0 3 X20C16 (TOP VIEW) I/O5 WE A7 A6 VCC WE VCC 27 I/O3 I/O4 28 2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 A2 A1 A0 N/C I/O0 I/O1 I/O2 VSS VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 NE NC NE • NC • VSS NC • The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 10µs or less. An automatic array recall operation reloads the contents of the E2PROM into RAM upon power-up. A7 NC • I/O1 I/O2 • Fast Access Time: 35ns, 45ns, 55ns High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum AUTOSTORE™ NOVRAM —Automatically Stores RAM Data Into the E2PROM Array When VCC Low Threshold is Detected —User Enabled Option —Open Drain AUTOSTORE Status Output Pin Power-on Recall —E2PROM Data Automatically Recalled Into RAM Upon Power-up Software Data Protection —Locks Out Inadvertent Store Operations Low Power CMOS —Standby: 250µA Infinite E2PROM Array Recall, and RAM Read and Write Cycles AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1991, 1995, 1996 Patents Pending 3826-2.9 7/31/97 T4/C0/D0 SH 1 Characteristics subject to change without notice X20C16 PIN DESCRIPTIONS Nonvolatile Enable (NE) Addresses (A0–A10) The Nonvolatile Enable input controls the recall function to the E2PROM array. The Address inputs select an 8-bit memory location during a read or write operation. AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold (VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. PIN NAMES Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Symbol A0–A10 I/O0–I/O7 WE CE OE NE AS VCC VSS NC Data In/Data Out (I/O0–I/O7) Data is written to or read from the X20C16 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable Nonvolatile Enable AUTOSTORE Output +5V Ground No Connect 3826 PGM T01 FUNCTIONAL DIAGRAM VCC SENSE AS E R R HIGH SPEED 2K x 8 SRAM ARRAY ST O ROW SELECT A3–A8 EC AL L EEPROM ARRAY CE OE WE CONTROL LOGIC NE COLUMN SELECT & I/OS A0–A2 A9–A10 I/O0–I/O7 3826 FHD F01 2 X20C16 matically stored from the RAM into the E2PROM array whenever VCC falls below the preset Autostore threshold. This feature is enabled by performing the first two steps for the software store with the command combination being 555[H]/CC[H]. DEVICE OPERATION The CE, OE, WE, and NE inputs control the X20C16 operation. The X20C16 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. The AUTOSTORE feature is disabled by issuing the three step command sequence with the command combination being 555[H]/CD[H]. The AUTOSTORE feature will also be reset if VCC falls below the power-up reset threshold (approximately 3.5V) and is then raised back into the operation range. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C16. Write Protection The X20C16 supports two methods of protecting the nonvolatile data. Memory Transfer Operations —If after power-up the AUTOSTORE feature is not enabled, no AUTOSTORE can occur. There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array. —VCC Sense – All functions are inhibited when VCC is ≤ 3.0V typical. SYMBOL TABLE The following symbol table provides a key to understanding the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user’s application. Recall operations are performed automatically upon power-up and under host system control when NE, OE and CE are LOW and WE is HIGH. The recall operation takes a maximum of 5µs. SDP (Software Data Protection) There are two methods of initiating a store operation. The first is the software store command. This command takes the place of the hardware store employed on the X20C04. This command is issued by entering into the special command mode: NE, CE, and WE strobe LOW while at the same time a specific address and data combination is sent to the device. This is a three step operation: the first address/data combination is 555[H]/ AA[H]; the second combination is 2AA[H]/55[H]; and the final command combination is 555[H]/33[H]. This sequence of pseudo write operations will immediately initiate a store operation. Refer to the software command timing diagrams for details on set and hold times for the various signals. WAVEFORM The second method of storing data is with the AUTOSTORE command. When enabled, data is auto- 3 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X20C16 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ........................................... 10mA Lead Temperature (Soldering, 10 seconds)...... 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Commercial Industrial Military 0°C –40°C –55°C Max. +70°C +85°C +125°C Supply Voltage Limits X20C16 5V ±10% 3826 PGM T02.1 3826 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units lCC1 VCC Current (Active) 100 mA ICC2 ICC3(2) VCC Current During Store VCC Current During AUTOSTORE VCC Standby Current (TTL Input) VCC Standby Current (CMOS Input) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage AUTOSTORE Output Output HIGH Voltage 5 2.5 mA mA 10 mA 250 µA 10 10 0.8 VCC + 0.5 0.4 0.4 µA µA V V V V V ISB1 ISB2 ILI ILO VIL(1) VIH(1) VOL VOLAS VOH –1 2 2.4 Test Conditions NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V Levels @ f = 20MHz All I/Os = Open All Inputs = VIH All I/Os = Open CE = VIH, All Other Inputs = VIH All I/Os = Open All Inputs = VCC – 0.3V All I/Os = Open VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH IOL = 4mA IOLAS = 1mA IOH = –4mA 3826 PGM T04.3 POWER-UP TIMING Symbol tPUR(2) tPUW(2) Parameter Power-Up to RAM Operation Power-Up to Nonvolatile Operation Max. Units 100 5 µs ms 3826 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions CI/O(2) CIN(2) Input/Output Capacitance Input Capacitance 10 6 pF pF VI/O = 0V VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 4 3826 PGM T06.1 X20C16 ENDURANCE AND DATA RETENTION Parameter Min. Units Endurance Store Cycles Data Retention 100,000 1,000,000 100 Data Changes Per Bit Store Cycles Years 3826 PGM T07.1 MODE SELECTION CE WE NE OE H L L L L L L L L X H L L H L H L H X H H H L L H L L X L H H L H H L H Mode Not Selected Read RAM Write “1” RAM Write “0” RAM Array Recall Software Command Output Disabled Not Allowed No Operation I/O Power Output High Z Output Data Input Data High Input Data Low Output High Z Input Data Output High Z Output High Z Output High Z Standby Active Active Active Active Active Active Active Active 3826 PGM T09 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 5V 735Ω OUTPUT 0V to 3V 5ns 1.5V 3826 PGM T08.1 318Ω 30pF 3826 FHD F04 5 X20C16 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C16-35 –40 to +85°C Symbol Parameter Min. tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold From Address Change 35 Max. X20C16-45 Min. 45 35 35 20 0 0 0 0 0 Max. 15 15 X20C16-55 Min. Max. 55 45 45 25 0 0 0 0 0 20 20 55 55 30 0 0 0 0 0 25 25 Units ns ns ns ns ns ns ns ns ns 3826 PGM T10 Read Cycle tRC ADDRESS tCE CE tOE OE WE tOLZ tOHZ tLZ DATA I/O tOH DATA VALID tHZ DATA VALID tAA 3826 FHD F05 Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven. 6 X20C16 Write Cycle Limits X20C16-35 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(4) tOW(4) tOZ(4) Parameter Min. Write Cycle Time Chip Enable to End of Write Input Address Setup Time Write Pulse Width Write Recovery Time Data Setup to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write Output Enable to Output in High Z 35 30 0 30 0 15 3 X20C16-45 Max. Min. Max. 45 35 0 35 0 20 3 15 X20C16-55 Min. 55 40 0 40 0 25 3 20 5 5 15 Max. 25 5 20 25 Units ns ns ns ns ns ns ns ns ns ns 3826 PGM T11 WE Controlled Write Cycle tWC ADDRESS OE tCW CE tWP tAS tWR WE tOZ tOW DATA OUT tDW tDH DATA VALID DATA IN 3826 FHD F06 Note: (4) tWZ, tOW, tOZ are periodically sampled and not 100% tested. 7 X20C16 CE Controlled Write Cycle tWC ADDRESS OE VIH tCW CE tAS tWP tWR WE tWZ tOW DATA OUT tDW DATA IN tDH DATA VALID 3826 FHD F07.2 8 X20C16 ARRAY RECALL CYCLE LIMITS X20C16-35 Symbol Parameter tRCC tRCP(5) Array Recall Cycle Time Recall Pulse Width to InitiateRecall WE Setup Time to NE tRWE X20C16-45 X20C16-55 Min. Max. Min. Max. Min. Max. Units 0.6 10 1000 40 10 1000 50 10 1000 µs ns 0 0 0 ns 3826 PGM T13 Array Recall Cycle tRCC ADDRESS tRCP NE OE tRWE WE CE DATA I/O 3826 FHD F10 Note: (5) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE. 9 X20C16 Software Command Timing Limits X20C16-35 Symbol tSTO tSP(6) tSPH tWC tAS tAH tDS tDH tSOE(7) tOEST(7) tNHZ(7) tNES tNEH Parameter Min. Store Cycle Time Store Pulse Width Store Pulse Hold Time Write Cycle Time Address Setup Time Address Hold time Data Setup Time Data Hold Time OE Disable to Store Function Output Enable from End of Store Nonvolatile Enable to Output in High Z NE Setup Time NE Hold Time Max. X20C16-45 Min. 5 30 35 35 0 0 15 3 20 10 Max. Min. Max. Units 5 ms ns ns ns ns ns ns ns ns ns ns 5 40 45 45 0 0 20 3 20 10 15 5 5 X20C16-55 50 55 55 0 0 25 3 20 10 20 5 5 25 5 5 ns ns 3826 PGM T12.2 CE Controlled Software Command Sequence tWC ADDRESS tSTO 555 555 2AA OE tAS tSP tSPH tOEST CE tAH WE tNEH tNES NE tSOE tNHZ DATA OUT tDS DATA IN tDH AA 55 CMD 3826 FHD F08.2 Note: (6) The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously. (7) tSOE, tOEST and tNHZ are periodically sampled and not 100% tested. 10 X20C16 WE Controlled Software Command Sequence tWC ADDRESS tSTO 555 555 2AA OE tOEST CE tAS tSP tSPH WE tAH tNES tNEH NE tSOE tNHZ DATA OUT tDS DATA IN tDH AA 55 CMD 3826 FHD F09.2 11 X20C16 AUTOSTORE Feature The AUTOSTORE instruction (EAS) to the SDP register sets the AUTOSTORE enable latch, allowing the X20C16 to automatically perform a store operation whenever VCC falls below the AUTOSTORE threshold (VASTH). VCC must remain above the AUTOSTORE Cycle End Voltage (VASEND) for the duration of the store cycle (tASTO). The detailed timing for this feature is illustrated in the AUTOSTORE timing diagram, below. Once the AUTOSTORE cycle is initiated, all other device functions are inhibited. The AUTOSTORE feature automatically saves the contents of the X20C16’s static RAM to the on-board bit-forbit shadow E2PROM at power-down. This circuitry insures that no data is lost during accidental power-downs or general system crashes, and is ideal for microprocessor caching systems, embedded software systems, and general system back-up memory. AUTOSTORE CYCLE Timing Diagrams VCC VOLTS (V) 5 4 AUTOSTORE CYCLE IN PROGRESS 3 2 VASTH VASEND tASTO STORE TIME 1 TIME (ms) VCC VASTH 0V tPUR tASTO tPUR AS 3826 FHD F14 AUTOSTORE CYCLE LIMITS X20C16 Symbol tASTO VASTH VASEND Parameter Min. AUTOSTORE Cycle Time AUTOSTORE Threshold Voltage AUTOSTORE Cycle End Voltage 4.0 3.5 Max. Units 2.5 4.3 ms V V 3826 PGM T15 12 X20C16 SDP (Software Data Protection) Store State Diagram POWER UP POWER UP Power Down S0 RAM Write or Recall NO STORE Software Store Enabled ADDR 555, DATA AA ADDR 555, DATA AA RAS S1 NO STORE ADDR 2AA, DATA 55 WRITE: ADDR 555, DATA=COMMAND 3826 FHD F12.1 SOFTWARE DATA PROTECTION COMMANDS Enable AUTOSTORE Reset AUTOSTORE Software Store EAS EAS SS STORE ON SS OR ENABLE/RESET AUTOSTORE Command SS Software Store & AUTOSTORE Power Down Enabled (AUTOSTORE) ADDR 555, DATA AA S2 NO STORE EAS RAS SS Power On Recall Data CC[H] CD[H] 33[H] 3826 PGM T14.1 13 3826 FHD F13.1 X20C16 NOTES 14 X20C16 PACKAGING INFORMATION 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.490 (37.85) 1.435 (36.45) 0.610 (15.49) 0.500 (12.70) PIN 1 0.100 (2.54) 0.035 (0.89) 1.30 (33.02) REF. 0.225 (5.72) 0.140 (3.56) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 0.070 (1.78) 0.030 (0.76) TYP. 0.055 (1.40) 0.026 (0.66) 0.014 (0.36) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) 0° 15° TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F08 15 X20C16 PACKAGING INFORMATION 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.460 (37.08) 1.400 (35.56) 0.550 (13.97) 0.510 (12.95) PIN 1 INDEX PIN 1 0.085 (2.16) 0.040 (1.02) 1.300 (33.02) REF. 0.160 (4.06) 0.125 (3.17) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.150 (3.81) 0.125 (3.17) 0.110 (2.79) 0.090 (2.29) 0.062 (1.57) 0.050 (1.27) 0.020 (0.51) 0.016 (0.41) 0.610 (15.49) 0.590 (14.99) 0° 15° TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F04 16 X20C16 PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45° REF. 0.095 (2.41) 0.075 (1.91) PIN 1 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. 0.200 (5.08) BSC 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.050 (1.27) BSC 0.040 (1.02) x 45° REF. TYP. (3) PLCS. 0.458 (11.63) 0.442 (11.22) 0.088 (2.24) 0.050 (1.27) 0.458 (11.63) –– 0.300 (7.62) BSC 0.120 (3.05) 0.060 (1.52) 0.560 (14.22) 0.540 (13.71) 0.400 (10.16) BSC 32 1 0.558 (14.17) –– PIN 1 INDEX CORDER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NTL ±0.005 (0.127) 3926 FHD F14 17 X20C16 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.420 (10.67) 0.050 (1.27) TYP. 0.045 (1.14) x 45° 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) PIN 1 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3° TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F13 18 X20C16 PACKAGING INFORMATION 28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.2980 (7.5692) 0.2920 (7.4168) 0.4160 (10.5664) 0.3980 (10.1092) 0.0192 (0.4877) 0.0138 (0.3505) 0.7080 (17.9832) 0.7020 (17.8308) 0.1040 (2.6416) 0.0940 (2.3876) BASE PLANE SEATING PLANE 0.0110 (0.2794) 0.0040 (0.1016) 0.050 (1.270) BSC 0.0160 (0.4064) X 45° 0.0100 (0.2540) 0.0125 (0.3175) 0.0090 (0.2311) 0° – 8° 0.0350 (0.8890) 0.0160 (0.4064) NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES 3. BACK EJECTOR PIN MARKED “KOREA” 4. CONTROLLING DIMENSION: INCHES (MM) 3926 FHD F17 19 X20C16 PACKAGING INFORMATION 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T SEE NOTE 2 12.50 (0.492) 12.30 (0.484) PIN #1 IDENT. O 0.76 (0.03) 0.50 (0.0197) BSC SEE NOTE 2 8.02 (0.315) 7.98 (0.314) 0.26 (0.010) 0.14 (0.006) 1.18 (0.046) 1.02 (0.040) 0.17 (0.007) 0.03 (0.001) SEATING PLANE 0.58 (0.023) 0.42 (0.017) 14.15 (0.557) 13.83 (0.544) 14.80 ± 0.05 (0.583 ± 0.002) SOLDER PADS 0.30 ± 0.05 (0.012 ± 0.002) TYPICAL 32 PLACES 15 EQ. SPC. 0.50 ± 0.04 0.0197 ± 0.016 = 7.50 ± 0.06 (0.295 ± 0.0024) OVERALL TOL. NON-CUMULATIVE 0.17 (0.007) 0.03 (0.001) 1.30 ± 0.05 (0.051 ± 0.002) 0.50 ± 0.04 (0.0197 ± 0.0016) FOOTPRINT NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 20 3926 ILL F38.1 X20C16 ORDERING INFORMATION X20C16 X X -X Access Time –35 = 35ns –45 = 45ns –55 = 55ns Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MB = Mil. STD 883 Package D = 28-Lead Cerdip P = 28 Lead Plastic Dip E = 32-Pad Ceramic LCC J = 32-Lead PLCC S = 28-Lead SOIC T = 32-Lead TSOP LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 21