TECHNICAL DATA IW4027B Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance. • • • Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4027BN Plastic IW4027BD SOIC IZ4027B Chip TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set Reset Clock PIN 16 =VCC PIN 8 = GND INTEGRAL Outputs J K Qn+1 Qn+1 L H X X X L H H L X X X H L H H X X X H H L L L L L L H L H L L L L H L H L L H H Qn Qn No change X = don’t care Qn+1 = State After Clock Positive Transition 1 IW4027B MAXIMUM RATINGS * Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) IIN DC Input Current, per Pin PD Power Dissipation in Still Air, Plastic DIP, SOIC Package Ptot Power Dissipation per Output Transistor Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value Unit -0.5 to +20 V -0.5 to VCC +0.5 V ±10 mA 500** mW 100 mW -65 to +150 °C 260 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating: - Plastic DIP from -55 to +100°C - SOIC Package from -55 to +65°C - Plastic DIP: - 10 mW/°C from +100 to +125°C - SOIC Package: : - 7 mW/°C from +65 to +125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) TA Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation VIN should be constrained to the range GND≤VIN ≤VCC. Unused inputs mu st always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IW4027B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Guaranteed Limit Test Conditions V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 5.0 10 15 4.95 9.95 14.95 4.5 9.0 13.5 4.95 9.95 14.95 4.5 9.0 13.5 4.95 9.95 14.95 4.5 9.0 13.5 V 0.05 0.05 0.05 0.5 1.0 1.5 0.05 0.05 0.05 0.5 1.0 1.5 0.05 0.05 0.05 0.5 1.0 1.5 V VIL=1.5V, VIH=3.5V, IO=1µA VIL=3.0V, VIH=7.0V, IO=1µA VIL=4.0V, VIH=11V, IO=1µA 5.0 10 15 5.0 10 15 VIL=1.5V, VIH=3.5V, IO=-1µA VIL=3.0V, VIH=7.0V, IO=-1µA VIL=4.0V, VIH=11V, IO=-1µA VOL Maximum Low-Level Output Voltage VIN=GND or VCC IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 1.0 2.0 4.0 20 1.0 2.0 4.0 20 30 60 120 600 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High VIN= GND or VCC (Source) Current VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V 5.0 5.0 10 15 -0.64 –2.0 –1.6 –4.2 -0.51 –1.6 –1.3 –3.4 -0.36 –1.15 –0.9 –2.4 IOH INTEGRAL mA mA 3 IW4027B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200 kΩ, Input t r=t f=20 ns) VCC Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit Maximum Clock Frequency 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4 6 MHz Maximum Propagation Delay, Clock to Q or Q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns tPLH Maximum Propagation Delay, Set to Q or Reset to Q 5.0 10 15 300 130 90 300 130 90 600 260 180 ns tPHL Maximum Propagation Delay, Set to Q or Reset to Q 5.0 10 15 400 170 120 400 170 120 800 340 240 ns tTLH, t THL Maximum Output Transition Time, Any Output 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Symbol fmax tPLH, t PHL CIN Parameter Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input tr=t f=20 ns) VCC Guaranteed Limit Parameter V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock 5.0 10 15 140 60 40 140 60 40 280 120 80 ns tw Minimum Pulse Width, Set or Reset 5.0 10 15 180 80 50 180 80 50 360 160 100 ns tsu Minimum Data Setup Time 5.0 10 15 200 75 50 200 75 50 400 150 100 ns Maximum Input Rise or Fall Time, Clock 5.0 10 15 45 5 2 45 5 2 90 10 4 µs Symbol tr, t f INTEGRAL 4 IW4027B VCC K(J) 0.5 tSU 0V 0.9 CLOCK 0.9 0.5 VCC 0.5 0.1 0.1 tLH tHL 0V tW VOHCC Q(Q) 0.5VCC VOL tREM tPHL(t PLH) VCC SET (RESET) 0.5 0V VCC Auoia SET nQ(nQ) (RESET) 0V VCC RESET (SET) 0.5 tW2 0V 0.9 Q(Q) UOL UV OHCC DD 0.5VCC 0.1 0V tTHL(t TLH) tPHL(t PLH) Figure 1. Switching Waveforms INTEGRAL 5 IW4027B 1.34 ± 0.03 Chip marking 402720 (x=0.093, y=0.5825) 13 12 11 10 15 09 16 08 01 07 02 03 04 05 1.44 ±0.03 14 06 CHIP PAD DIAGRAM IZ4027B Pad size 0.100 x 0.100 mm (Pad size is given as per passivation layer) Thickness of chip 0.46 ± 0.02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 INTEGRAL Symbol Q2 Q2 Clock 2 Reset 2 K2 J2 Set 2 GND Set 1 J1 K1 Reset 1 Clock 1 Q1 Q1 Vcc X 0.116 0.111 0.474 0.6555 0.8335 1.124 1.124 1.1245 1.124 1.124 0.8335 0.6555 0.474 0.111 0.116 0.116 Y 0.4215 0.126 0.1755 0.1755 0.174 0.1235 0.4065 0.6855 0.9335 1.2165 1.166 1.1645 1.1645 1.214 0.9185 0.7365 6