IW4020B Description The IW4020B is ripple-carry binary counter.All counter stages are master-slave flip-flops.The state of a counteradvances one count on the negative transition of each input pulse,a high level on the R E SE T line resets thecounter to its all zeros state.Schmitt trigger action on the input-pulse line permits unlimited rise and fall times Features Operating Voltage Range: 3.0 to 18 V Maximum input current of 1uA at 18 V over full packagetemperature range ;100 nA at 18 V and 25 C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 16 16 SOP - 16 DIP - 16 2.5 V min @ 15.0 V supply Package Logic Diagram Pin Assignment 9 7 5 CLOCK 10 4 Q1 14 15 1 16 2 15 Q11 Q14 3 14 Q10 Q6 4 13 Q8 Q5 Q5 5 12 Q9 Q7 6 11 RESET Q4 7 10 CLOCK GND 8 9 Q6 Q7 12 1 Q13 Q4 6 13 Q12 Q1 Q8 Function Table Q9 Q10 Inputs Q11 Clock Q12 2 Output Reset Output state L No change Q13 RESET 11 3 Q14 L X PIN16 = VCC PIN 8 = GND H Advance to next state All Outputs are low X = don ' t care BEIJING ESTEK ELECTRONICS CO.,LTD 1 IW4020B Absolute Maximum Ratings Symbol VCC VIN VOUT Parameter DC Supply Voltage(Referencedto GND) DC Input Voltage(Referencedto GND) DC Output Voltage (Referencedto GND) IIN DC Input Current, per Pin PD Power Dissipa tion in Still Air, Plastic PD SO IC Package+ Power Dissipation per Output Transistor Tstg Value -0.5 to +20 -0.5 to V CC + 0. 5 -0.5 to V CC + 0. 5 DI P+ Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Unit V V V +- 10 mA 750 500 mW 100 mW -65 to +150 ! C 260 ! C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating - Plastic DIP: - 10 mW/ °C from 65°to 125 °C SOIC Package °C from 65°to 125 °C Recommended Operating Conditions Symbol VCC VIN , VOUT T Parameter DC Supply Voltage(Referenced to GND) DC Input Vo ltage, Output Voltage(Referenced to GND) Operating Temperature, All PackageTypes in Max UnitM 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND (VIN or VOUT)ﾣ VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC Unused outputs must be left open. BEIJING ESTEK ELECTRONICS CO.,LTD 2 IW4020B DC Electrical Characteristics (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V -55°C 25°C 125 °C Unit VIH Minimum High-Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low Level Input Voltage 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level VIN=GND or VCC Output Voltage 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V VIN=GND or VCC IIN Maximum Input Leakage Current VIN= GND or VCC 18 +- 0.1 +- 0.1 +- 1.0 uA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 IOL Minimum Output Low (Sink) Current VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High (Source) Current VIN= GND or VCC VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V 5.0 5.0 10 15 -0.64 –2.0 –1.6 –4.2 -0.51 –1.6 –1.3 –3.4 -0.36 –1.15 –0.9 –2.4 IOH VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V uA mA mA BEIJING ESTEK ELECTRONICS CO.,LTD 3 IW4020B AC Electrical Characteristics Symbol f max (CL=50pF, RL=200 k ns) Parameter Guaranteed Li mit VCC V 5.0 10 15 Maximum Clock Frequency(Figure 1) , Input t r =t f =20 ≥-55°C 3.5 8 12 25°C ≤125°C Unit 3.5 1.75 MHz 8 4 12 6 tPLH , tPHL Maximum Propagation Delay, Clock to Q1 (Figure 1) 5.0 10 15 360 160 130 360 160 130 720 320 260 tPLH , tPHL Maximum Propagation Delay, Qn to Qn+1 (Figure 3) 5.0 10 15 330 80 60 330 80 60 660 160 120 Maximum Propagation Delay, Reset to Any Q (Figure 2) 5.0 10 15 280 120 100 280 120 100 560 240 200 Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 tPHL tTLH , t THL CIN Maximum Input Capacitance - Timing Requirements Symbol Unit tw V V Parameter pF 7.5 (CL=50pF, RL=200 k ns) , Input t r =t f =20 Guaranteed Limit ≥-55°C 25°C ≤125°C Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 140 60 40 140 60 40 280 120 80 tw Minimum PulseWidth, Reset 5.0 10 15 200 80 60 200 80 60 400 160 120 trem Minimum Removal Time, Reset(Figure 2) 5.0 10 15 350 150 100 350 150 100 700 300 200 tr, tf Maximum Input Rise and Fall Tim es, Clock (Figure 1) 5.0 10 15 ( Figure 2) ns ns ns ns ns ns ns µs Unli mited BEIJING ESTEK ELECTRONICS CO.,LTD 4 IW4020B CLOCK 90% 50% 10% GND max tp tp 90% 50% 10% Q 90% 50% 10% GND Figure 1. Switching W avefor ms 50% CLOCK GND e 50% GND RESET tp 50% ANY Q GND Figure 2. Switching W avefor ms QN 50% 50% GND tp 50% Q N+1 GND Figure 3. Switching W avefor ms BEIJING ESTEK ELECTRONICS CO.,LTD 5 IW4020B Timing Diagram Clock 1 2 4 8 16 32 64 128 256 2048 4096 8192 16384 512 1024 Reset Q1 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Expanded Logic Diagram Q Q Q 14 Q14 Q Q Q 14 Q14 4 Clock Reset R Q Q Address : R R Q4 Q Q14 6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793 Http://www.estek.com.cn Email:[email protected] REV No:01-060834 BEIJING ESTEK ELECTRONICS CO.,LTD 6