AKM AK4204ET

[AK4204]
=Preliminary =
AK4204
Stereo Cap-less LINE-Amp and Video-Amp
GENERAL DESCRIPTION
The AK4204 is an audio stereo cap-less line driver with 1-channel video driver. It eliminates the need for
large DC-blocking capacitors with a built-in Charge-pump circuit. The AK4204 achieves 2Vrms outputs
with excellent linearity by single 3.3V power supply. It is well suitable for Blu-ray player and set-top box
systems. The AK4204 is available in small 16-pin TSSOP, saving the system space and cost.
FEATURE
1. Audio Line-Amp
† Single-ended Input
† Stereo Cap-less Amplifier (No DC-blocking capacitors required)
† Line-Out level: 2.0Vrms
† THD+N: -90dB
† S/N: 102dB
† Output gain: 6dB
† Low-pass Filter: fc= 130kHz
† Pop Noise Free Ground-referenced Output
† Audio Mute Function
2. Video Amp
† 1ch Stereo Cap-less Amplifier (No DC-blocking capacitors required)
† Integrated Video Amplifier (+6dB)
† Input Level: 1.5Vpp (max)
† SN: 75dB(typ), Bandwidth: 100kHz ∼ 6MHz
† LPF: -0.5dB@ 6.75MHz (typ), [email protected] (typ)
† Video Mute Function
† Power Supply: 3.0V ~ 3.6V
† Ta: −20 ∼ 85°C
† Package: 16pinTSSOP
Rev. 0.1
2012/02
-1-
[AK4204]
■
Block Diagram
R1
R2
LOUT
SGND
LINP
+
R1
R2
R3
SGND
Charge
Pump
R1
R2
VDD1
VSS1
VDD2
VSS2
VEE
CP
CN
+
RINP
ROUT
R1
SGND
VIN
-
R2
R3
Clamp
+
LPF
VOUT
-
VPDN
APDN
Figure 1. AK4204 Block Diagram
Rev. 0.1
2012/02
-2-
[AK4204]
■
Ordering Guide
AK4204ET
AKD4204
■
−20 ∼ +85°C
16 pin TSSOP (0.65mm pitch)
Evaluation board for AK4204
Pin Layout
VIN
1
16
VDD2
VPDN
2
15
VSS2
CN
3
14
VOUT
CP
4
13
VEE
APDN
5
12
VSS1
LINP
6
11
VDD1
RINP
7
10
LOUT
SGND
8
9
ROUT
AK4204
Top
View
Rev. 0.1
2012/02
-3-
[AK4204]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
Pin Name
VIN
VPDN
CN
CP
APDN
LINP
RINP
SGND
I/O
I
I
I
O
I
I
I
I
Function
9
ROUT
O
Audio Output pin (R channel)
10
LOUT
O
11
VDD1
-
12
VSS1
-
13
VEE
O
14
15
VOUT
VSS2
O
-
Audio Output pin (L channel)
Power Supply 1 pin; 3.0V∼3.6V
Connect a 0.1μF ceramic capacitor in parallel with a 10μF 3.3V electrolytic
capacitor between this pin and VSS1.
Ground 1 pin
Negative Voltage Output pin
Connect to VSS1 via a 10μF 3.3V electrolytic capacitor.
Video Signal Output pin
Ground 2 pin
16
VDD2
-
Video Signal Input pin
Video Block Power Down pin
Negative Charge Pump Capacitor Terminal pin
Positive Charge Pump Capacitor Terminal pin
Audio Block Power Down pin
Lch Audio Positive Input pin
Rch Audio Positive Input pin
Reference Voltage Input pin for Audio Signal (0V)
Power Supply 2 pin; 3.0V∼3.6V
Connect a 0.1μF ceramic capacitor in parallel with a 10μF 3.3V electrolytic
capacitor between this pin and VSS2.
Rev. 0.1
2012/02
-4-
[AK4204]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2 = 0V; Note 1, Note 2)
Parameter
Power Supply
Symbol
VDD1
VDD2
IIN
VINA
VINV
Ta
Tstg
Input Current (any pins except for supplies)
Audio Input Voltage
Video Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages are respect to ground.
Note 2. VSS1 and VSS2 must be connected to the same analog plane.
Note 3. VDD1 and VDD2 must have the same voltage.
min
max
Unit
-0.3
4.0
V
VEE-0.3
-0.3
-20
-65
±10
VDD1 +0.3
VDD2+0.3
85
150
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS
(VSS1 = VSS2 = 0V)
Parameter
Power Supply
Symbol
VDD1
VDD2
Note 3. VDD1 and VDD2 must have the same voltage.
min
3.0
3.0
typ
3.3
3.3
max
3.6
3.6
Unit
V
V
typ
max
Unit
18
TBD
mA
Note: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTICAL CHARACTERISTICS
(Ta=25°C; VDD1= VDD2 = 3.3V; VSS1= VSS2 = 0V)
Power Supplies
Parameter
min
Power Supply (VDD1+VDD2)
Normal Operation (Note 4)
Note 4. No input and no load.
Rev. 0.1
2012/02
-5-
[AK4204]
ANALOG CHARACTERISTICS (Audio)
(Ta=25°C; VDD1=VDD2= 3.3V; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼
20kHz; RL =5kΩ, unless otherwise specified)
Parameter
Output Level (Note 5)
Gain
THD+N (at 2Vrms output, VDD1≥3.135V)
Dynamic Range (-60dBFS with A-weighted)
S/N (A-weighted)
Inter channel Isolation
Output Offset Voltage
LPF Frequency Response
-3dB
Note 5. VDD1= ≥3.135V, THD+N=-90dB.
min
typ
max
Unit
-
2
6
-90
102
102
100
±0
130
-
Vrms
dB
dB
dB
dB
dB
mV
kHz
-
ANALOG CHARACTERISTICS (Video)
(Ta=25°C; VDD1=VDD2= 3.3V; VSS1=VSS2=0V; unless otherwise specified, Note 6, Note 7)
Parameter
Conditions
min
typ
Input Signal
Output Gain
Input=0.2Vp-p, 100kHz
6
Output Signal
f=100kHz, THD=-30dB.
2.52
Frequency Response
Response at 6.75MHz
-0.5
Input=0.2Vpp, Sin Wave
Response at 27MHz
-43
(0dB at 100kHz)
±5
-
max
1.5
-
Unit
Vpp
dB
Vpp
dB
dB
Group Delay Distortion
S/N(※)
Load Resistance
Load Capacitance
|GD3MHz-GD6MHz|
10
nsec
BW= 100kHz to 6MHz.
75
dB
R1+R2 (Note 8)
140
150
Ω
C1
(Note 8)
400
pF
C2
(Note 8)
15
pF
Note 6. The analog characteristics are specified at the pin of each output.
Note 7. Input Sync Tip Level=-0.43V∼-0.14V(the sync chip level based on the pedestal level)
Horizontal Line Sync Pulse=4.0μs ∼5.4μs, Equalizing Pulse=2.0μs ∼2.7μs, Serration Pulse=4.0μs ∼5.4μs
Note 8. Refer to Figure 2.
*CCIR 567 weighting.
R1
75 Ω
VOUT
R2
75 Ω
C1
C2
max: 15pF
(C2)
max: 400pF
(C1)
Figure 2. Load Resistance R1+R2 and Load Capacitance C1/C2.
Rev. 0.1
2012/02
-6-
[AK4204]
OPERATION OVERVIEW
■
Charge Pump Circuit
Internal negative power supply circuit (Figure 3) supplies the negative voltage to the video amp, and the video amp 0V
output is used for a pedestal level (Figure 4 and Figure 5). Therefore, the output coupling capacitor can be removed.
AK4204
VDD1
Charge
Pump
CP
CN
Negative Power
VSS1
(+)
1uF
C1
VEE
C2
10uF
(+)
Figure 3. Charge Pump Circuit
Note 9. C1 and C2 should be low ESR (Equivalent Series Resistance) capacitors. When these capacitors are polarized,
the positive polarity pins should be connected to the CP or VSS1 pin.
AK4204
2 Vrms
0V
ROUT
(LOUT)
Figure 4. Audio Signal Output
AK4204
75Ω
VOUT
75Ω
0V
Figure 5. Video Signal Output
Rev. 0.1
2012/02
-7-
[AK4204]
■
Audio Circuit Power-Up Sequence
The audio circuit of the AK4204 is powered-up when the APDN pin becomes “H”.
(Note) The charge pump starts operation when the APDN pin or VPDN pin is “H”.
The figure below shows an example of when the VPDN pin becoes “H” before the APDN pin.
Power Supply
VDD1, VDD2
3.0V
VPDN: “L” ⇒“H” (Note)
(a)
APDN
(b)
(1)
Charge Pump
VEE
Power down VEE=0V
Power up
VEE=Negative voltage
-1.85V
Audio Timer
Circuit
(2)
time A
Hi-Z
LINP/RINP
LOUT/ROUT
Audio Input Signal
Mute=0V
Mute=0V
Figure 6. System Reset Diagram
(1) When VDD1 and VDD2 are powered-up, audio analog output is connected to VSS internally via a mute switch.
The charge pump is powered-up in slow start mode, and the VEE voltage reachs -1.85V in 0.4ms.
(2) When the VEE reachs -1.85V, the audio timer circuit starts counting the “timeA” period (max. 15ms). If the APDN
pin becomes “H” before the “timeA” period starts (a), the mute switch is released after the “timeA” period and the
audio output is enabled. If the APDN pin becomes “H” after the “timeA” period (b), mute is released immediately.
(3) No audible click noise occurs by inputting 0V to the LINP/RINP pin until the end of “timeA” period.
Rev. 0.1
2012/02
-8-
[AK4204]
■
Video Circuit Power-Up Sequence
The video circuit of the AK4204 is powered-up when the VPDN pin becomes “H”.
(Note) The charge pump starts operation when the VPDN pin or APDN pin is “H”.
The figure below shows an example of when the APDN pin becoes “H” before the VPDN pin.
Power Supply
VDD1,VDD2
3.0V
APDN: “L” → “H” (Note)
VPDN
Charge Pump
VEE
Power down VEE=0V
Power up VEE = Negative voltage
Video Circuit
Power up
Power down
Video Timer
Circuit
(1)
time B
VIN
VOUT
Video Input Signal
(2)
VSS2=0V
Video Output Signal
VSS2=0V
Figure 7. System Reset Diagram
(1) When the VPDN pin goes to “H”, the video timer circuit starts counting “timeB” period (max. 100ms).
(2) After the “timeB” period, the video output becomes ebable exiting 0V state.
Rev. 0.1
2012/02
-9-
[AK4204]
SYSTEM DESIGN (TBD)
Figure 8 shows the system connection diagram for the AK4204. An evaluation board [AKD4204] demonstrates the
optimum layout, power supply arrangements and measurement results.
Analog
3.3V
0.1u
Video In
75
μP
Audio In L
Audio In R
1 u (1)
1u
1u
+
1
VIN
VDD2 16
2
VPDN
VSS2 15
3
CN
VOUT 14
4
CP
VEE 13
5
APDN
VSS1 12
6
LINP
VDD1 11
7
RINP
AOUTL 10
8
SGND
AOUTR
0.1μ + 10μ
75
AK4204
Video Out
+
0.1μ
220
220
10μF
+
10μ
220
220
Lch Out
9
Rch Out
Figure 8. Typical Connection Diagram
Rev. 0.1
2012/02
- 10 -
[AK4204]
1. Grounding and Power Supply Decoupling
The AK4204 requires careful attention to power supply and grounding arrangements. VDD1 and VDD2 are usually
supplied from the analog supply in the system. If VDD1 and VDD2 are supplied separately, they must be powered-up at
the same time. VSS1 and VSS2 pins must be connected to the analog ground plane. System analog ground and digital
ground should be wired separately and connected together as close as possible to where the supplies are brought onto
the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible to the supply
pin.
2. Notes for Drawing a Board
Analog input and output pins should be as near as possible in order to avoid unwanted coupling into the AK4204.
Unused pins should be open.
3. Analog Input
3-1. Audio Signal Input
The audio signal inputs are single-ended input. Connect a capacitor about 1uF to each input pin for AC coupling.
3-2. Video Signal Input
Tip Sync level is fixed by an internal clamp circuit. Connect a capacitor about 0.1uF to the VIN pin for AC
coupling.
4. Analog Output
4-1. Audio Signal Output
The audio signal outputs are single-ended output. The output rages to 2.0Vrms (typ) centered VSS (0V, typ) via
LPF. The DC offset is less than ±5mV.
4-2. Video Signal Output
The integrated 1-channel video amplifier has drivability for a load resistance of 150Ω. The output gain is +6dB
(typ) via LPF. DC offset is less than ±100mV.
Rev. 0.1
2012/02
- 11 -
[AK4204]
PACKAGE (TBD)
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
■
0-10°
Package & Lead Frame Material
Package molding compound: Epoxy Resign, Halogen (Br, Cl) Free
Lead frame material: Cu Alloy
Lead frame surface treatment: Solder (Pb free) Plate
Rev. 0.1
2012/02
- 12 -
[AK4204]
MARKING
4204ET
XXXYY
1)
2)
3)
Pin #1 indication
Date Code: XXXYY (5 digits)
XXX:
Lot#
YY:
Date Code
Marketing Code: 4204ET
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products.
You are fully responsible for the incorporation of these external circuits, application circuits, software and other
related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by
you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of
any patent, intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from
any and all claims arising from the use of said product in the absence of such notification.
Rev. 0.1
2012/02
- 13 -