SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs D D D D Supports LVCMOS Switching Levels on the Control and RESET Inputs RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 5000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level. The two VREF pins (A3 and T3), are connected together internally by approximately 150 Ω. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C LFBGA – GKE Tape and reel SN74SSTU32864GKER SU864 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 description/ordering information (continued) The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case, the setup-time requirement for DCS is the same as for the other D data inputs. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. terminal assignments for 1:1 register (C0 = 0, C1 = 0) GKE PACKAGE (TOP VIEW) 1 A B C 2 3 4 5 6 1 2 3 4 5 6 A D1 (DCKE) NC DNU D2 D15 VCC GND Q1 (QCKE) B VREF GND Q2 Q15 C D3 D16 D D4 (DODT) NC VCC GND VCC GND VCC GND E D5 D17 D F D6 D18 E G NC RESET F H CLK D7 (DCS) G J CLK CSR H K D8 D19 J L D9 D20 K M D10 D21 L N D11 D22 P D12 D23 R D13 D24 T D14 D25 M N P R T 2 Q3 Q16 Q4 (QODT) DNU VCC GND Q5 Q17 Q6 Q18 VCC GND VCC GND C1 C0 Q7 (QCS) DNU VCC GND VCC GND NC NC Q8 Q19 VCC GND VCC GND Q9 Q20 Q10 Q21 VCC GND VCC GND Q11 Q22 Q12 Q23 VCC VREF VCC VCC Q13 Q24 Q14 Q25 Each pin name in parentheses indicates the DDR-II DIMM signal name. NC – No internal connection DNU – Do not use POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 logic diagram for 1:1 register configuration (positive logic) RESET CLK CLK VREF D1 (DCKE) G2 H1 J1 A3, T3 A1 D CLK A5 Q1 (QCKE) R D4 (DODT) D1 D CLK D5 Q4 (QODT) R D7 (DCS) H2 D CLK H5 Q7 (QCS) R CSR J2 One of 22 Channels D2 B1 D CE CLK B5 Q2 R To 21 Other Channels (D3, D5, D6, D8–D25) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments for 1:2 register A (C0 = 0, C1 = 1) 1 6 2 3 4 5 6 Q1B (QCKEB) A D1 (DCKE) NC VREF VCC Q1A (QCKEA) B D2 DNU GND GND Q2A Q2B C D3 DNU VCC VCC Q3A Q3B D D D4 (DODT) NC GND GND Q4A (QODTA) Q4B (QODTB) E E D5 DNU VCC GND Q5A Q5B A B C F F D6 DNU VCC GND Q6A Q6B G G NC RESET VCC VCC C1 C0 H H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR DNU VCC GND NC D8 VCC GND NC K Q8A Q8B VCC GND VCC GND Q9A Q9B Q10A Q10B VCC GND VCC GND Q11A Q11B Q12A Q12B VCC VREF VCC VCC Q13A Q13B Q14A Q14B J K L L D9 DNU M M D10 DNU N N D11 DNU P P D12 DNU R R D13 DNU T T D14 DNU Each pin name in parentheses indicates the DDR-II DIMM signal name. NC – No internal connection DNU – Do not use 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 logic diagram 1:2 register-A configuration (positive logic) RESET CLK CLK VREF D1 (DCKE) G2 H1 J1 A3, T3 A1 A5 D Q1A (QCKEA) CLK A6 R D4 (DODT) D1 D5 D Q1B (QCKEB) Q4A (QODTA) CLK D6 R D7 (DCS) H2 H5 D Q4B (QODTB) Q7A (QCSA) CLK H6 R CSR Q7B (QCSB) J2 One of Eleven Channels D2 B1 D CE B5 Q2A CLK B6 R Q2B To 10 Other Channels (D3, D5, D6, D8–D14) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 GKE PACKAGE (TOP VIEW) 1 A B C D 2 3 4 5 terminal assignments for 1:2 register B (C0 = 1, C1 = 1) 6 1 2 3 4 5 6 A D1 NC Q1B D2 DNU VCC GND Q1A B VREF GND Q2A Q2B C D3 DNU NC VCC GND Q3B D4 VCC GND Q3A D Q4A Q4B E D5 DNU D6 DNU VCC GND Q5B F VCC GND Q5A E Q6A Q6B F G NC RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR NC D8 DNU VCC GND NC K VCC GND Q8A Q8B L D9 DNU Q9B D10 DNU VCC GND Q9A M VCC GND Q10A Q10B N D11 (DODT) DNU VCC VCC Q11A (QODTA) Q11B (QODTB) P P D12 DNU GND GND Q12A Q12B R R D13 DNU VCC VCC Q13A Q13B T D14 (DCKE) VCC Q14A (QCKEA) Q14B (QCKEB) G H J K L M N T DNU VREF Each pin name in parentheses indicates the DDR-II DIMM signal name. NC – No internal connection DNU – Do not use 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 logic diagram 1:2 register-B configuration (positive logic) RESET CLK CLK VREF D14 (DCKE) G2 H1 J1 A3, T3 T1 T5 D Q14A (QCKEA) CLK T6 R D11 (DODT) N1 N5 D Q14B (QCKEB) Q11A (QODTA) CLK N6 R D7 (DCS) H2 H5 D Q11B (QODTB) Q7A (QCSA) CLK H6 R CSR Q7B (QCSB) J2 One of Eleven Channels D1 A1 D CE A5 Q1A CLK A6 R Q1B To 10 Other Channels (D2–D6, D8–D10, D12–D13) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION GND Ground Ground input VCC Power-supply voltage 1.8 V nominal VREF Input reference voltage 0.9 V nominal CLK Positive master clock input Differential input CLK Negative master clock input Differential input C0, C1 Configuration control inputs – Register A, Register B, 1:1, 1:2 select LVCMOS inputs RESET Asynchronous reset input – resets registers and disables VREF data and clock differential-input receivers LVCMOS input D1–D25 Data inputs – clocked in on the crossing of the rising edge of CLK and the falling edge of CLK SSTL_18 inputs CSR, DCS Chip select inputs – disables D1-D25† outputs switching when both inputs are high SSTL_18 inputs DODT The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input DCKE The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input Q1–Q25‡ Data outputs that are suspended by the DCS and CSR control 1.8 V CMOS outputs QCS Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QODT Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QCKE Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output NC No internal connection Do not use – inputs are in standby-equivalent mode, and outputs are driven low. DNU † Data inputs = D2, D3, D5, D6, D8–D25 when C0 = 0 and C1 = 0 Data inputs = D2, D3 D5, D6, D8–D14 when C0 = 0 and C1 = 1 Data inputs = D1–D6, D8–D10, D12, D13 when C0 = 1 and C1 = 1. ‡ Data outputs = Q2, Q3, Q5, Q6, Q8–Q25 when C0 = 0 and C1 = 0 Data outputs = Q2, Q3 Q5, Q6, Q8–Q14 when C0 = 0 and C1 = 1 Data outputs = Q1–Q6, Q8–Q10, Q12, Q13 when C0 = 1 and C1 = 1. 8 ELECTRICAL CHARACTERISTICS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 FUNCTION TABLES INPUTS RESET DCS H H CLK OUTPUT Qn CSR CLK Dn L X ↑ ↓ L L L X ↑ ↓ H H H X L ↑ ↓ L L H X L ↑ ↓ H H H H H ↑ ↓ X Q0 H X X L or H L or H X Q0 L X or floating X or floating X or floating X or floating X or floating L INPUTS OUTPUTS RESET CLK CLK DCKE, DCS, DODT H ↑ ↓ H QCKE, QCS, QODT H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.5 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 2.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 recommended operating conditions (see Note 4) MIN NOM 1.7 MAX VCC VREF Supply voltage VI VIH Input voltage AC high-level input voltage Data inputs, CSR VIL VIH AC low-level input voltage Data inputs, CSR DC high-level input voltage Data inputs, CSR VIL VIH DC low-level input voltage Data inputs, CSR High-level input voltage RESET, Cn VIL VICR Low-level input voltage RESET, Cn Common-mode input voltage range CLK, CLK 0.675 VI(PP) IOH Peak-to-peak input voltage CLK, CLK 600 High-level output current –8 IOL TA Low-level output current 8 0.49 × VCC Reference voltage 0 0.5 × VCC V 0.51 × VCC V VCC VREF+250 mV VREF+125 mV V V VREF–125 mV 0.65 × VCC V V 0.35 × VCC 0 V V VREF–250 mV Operating free-air temperature UNIT 1.9 1.125 V V mV 70 mA _C NOTE 4: The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH IOH = –100 µA IOH = –6 mA VOL IOL = 100 µA IOL = 6 mA II ICC ICCD All inputs‡ VI = VCC or GND RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input, 1:2 configuration Chip-select-enabled low-power active mode – clock only ICCDLP Chip-select-enabled low-power active mode – 1:1 configuration Chip-select-enabled low-power active mode – 1:2 configuration Data inputs, CSR Ci 1.7 V Static standby Dynamic operating – per each data input, 1:1 configuration CLK, CLK VCC 1.7 V to 1.9 V MIN TYP† 1.7 V to 1.9 V 0.2 1.7 V 0.5 IO = 0 ±5 19V 1.9 RESET = VCC, VI = VIH(AC) or VIL(AC), CLK a and CLK switching C dC s c g 50% duty du y cycle, cyc e, One data input switching at one-half clock frequency, 50% duty cycle µA mA µA/ MHz µA/ clock MHz/ D input 36 RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle µA/ MHz 27 IO = 0 VI = VREF ± 250 mV VICR = 0.9 V, VI(PP) = 600 mV 2 1.8 V µA/ clock MHz/ D input 2 2.5 1.8 V RESET VI = VCC or GND † All typical values are at VCC = 1.8 V, TA = 25°C. ‡ Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. 3 2 µA 40 18 1.8 V V 100 28 IO = 0 UNIT V 1.9 V RESET = VCC, VI = VIH(AC) or VIL(AC), CLK a and CLK switching C dC s c g 50% duty du y cycle, cyc e, One data input switching at one-half clock frequency, 50% duty cycle MAX VCC–0.2 1.2 3.5 3 pF 2.5 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Note 5) MIN fclock tw Clock frequency tact tinact Differential inputs active time (see Note 6) tsu th Pulse duration, CLK, CLK high or low Hold time UNIT 500 MHz 1 Differential inputs inactive time (see Note 7) Setup time MAX DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high 0.7 DCS before CLK↑, CLK↓, CSR low 0.5 DODT, DCKE, and Data before CLK↑, CLK↓ 0.5 DCS, DODT, DCKE, and Data after CLK↑, CLK↓ 0.5 ns 10 ns 15 ns ns ns NOTES: 5. All input slew rates are 1 V/ns ±20%. 6. VREF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER fmax tpdm† tpdmss† tRPHL† TO (OUTPUT) VCC = 1.8 V ± 0.1 V MIN 500 1.4 UNIT MAX MHz CLK and CLK Q 2.5 ns CLK and CLK Q 2.7 ns RESET Q 3 ns † Includes 350-ps test-load transmission-line delay output slew rates over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM TO MIN MAX UNIT dV/dt_r 20% 80% 1.9 4.9 V/ns dV/dt_f 80% 20% 1.9 4.9 V/ns 1 V/ns dV/dt_∆§ 20% or 80% § Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate) 12 VCC = 1.8 V ± 0.1 V POST OFFICE BOX 655303 80% or 20% • DALLAS, TEXAS 75265 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC ZO = 50 Ω, tD = 350 ps Test Point DUT RL = 1 kΩ CLK RL = 100 Ω Clock Inputs CL = 30 pF (see Note A) ZO = 50 Ω, tD = 350 ps CLK ZO = 50 Ω, tD = 350 ps Output Test Point Out Test Point RL = 1 kΩ LOAD CIRCUIT tw VIH VREF Input VIL VCC LVCMOS RESET Input VCC/2 VCC/2 VOLTAGE WAVEFORMS PULSE DURATION 0V tinact ICC (see Note B) VREF VI(PP) tact 90% 10% ICC (operating) Timing Inputs ICC (standby) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR VICR tPLH tPHL VOH Output VTT VTT VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VI(PP) Timing Inputs tsu VIH LVCMOS RESET Input VICR VCC/2 VIL tPHL th VOH VIH Input VREF Output VREF VTT VOL VIL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time with one transition per measurement. E. VREF = VCC/2 F. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. VIL = VREF – 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. VI(PP) = 600 mV I. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC DUT RL = 50 Ω Test Point Out VOH 80% CL = 5 pF (see Note A) Output 20% VOL dV_f dt_f LOAD CIRCUIT HIGH-TO-LOW SLEW-RATE MEASUREMENT VOLTAGE WAVEFORMS HIGH-TO-LOW SLEW-RATE MEASUREMENT DUT dt_r dV_r Test Point Out CL = 5 pF (see Note A) RL = 50 Ω LOAD CIRCUIT LOW-TO-HIGH SLEW-RATE MEASUREMENT 20% Figure 2. Output Slew-Rate Measurement Information POST OFFICE BOX 655303 VOH VOL VOLTAGE WAVEFORMS LOW-TO-HIGH SLEW-RATE MEASUREMENT NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified). 14 80% Output • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74SSTU32864GKER ACTIVE LFBGA GKE 96 1000 SN74SSTU32864ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) TBD Lead/Ball Finish MSL Peak Temp (3) / Level-3-220C-168 HR / Level-3-250C-1WEEK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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