DS1073 3V EconOscillator/Divider www.maxim-ic.com FEATURES § § § § § § § § § § § Dual fixed-frequency outputs (30kHz to 100MHz) User-programmable on-chip dividers (from 1 to 513) User-programmable on-chip prescaler (1, 2, 4) No external components ±0.5% initial tolerance (commercial) ±1% variation over commercial temperature and voltage Internal clock, external clock or crystal reference options 2.7 to 3.6V supply Power-down mode Synchronous output gating Industrial temp operation with relaxed specifications PIN ASSIGNMENT I/O 1 8 OSCIN OUT0 2 7 XTAL VCC 3 6 OE GND 4 5 PDN/SELX DS1073Z-XXX 150-mil SOIC DS1073M-XXX 300-mil DIP XXX = Frequency option FREQUENCY OPTIONS Part No. DS1073M/Z-100 DS1073M/Z-80 DS1073M/Z-66 DS1073M/Z-60 Max O/P Freq. 100.000MHz 80.000MHz 66.667MHz 60.000MHz DESCRIPTION The DS1073 is a fixed-frequency oscillator requiring no external components for operation. Numerous operating frequencies are possible in the range of approximately 27.3kHz to 100MHz through the use of an on-chip programmable prescaler and divider. The DS1073 features a master oscillator followed by a prescaler and then a programmable divider. The prescaler and programmable divider are user-programmable with the desired values being stored in nonvolatile memory. This allows the user to buy an off the shelf component and program it on site prior to board production. Design changes can be accommodated on the fly by simply programming different values into the device (or reprogramming previously programmed devices). The DS1073 is shipped from the factory configured for half the maximum operating frequency. Contact the factory for specially programmed devices. As alternatives to the onboard oscillator an external clock signal or a crystal may be used as a reference. The choice of reference source (internal or external) is user-selectable at the time of programming (or on the fly if the SEL mode is chosen). The DS1073 features a dual-purpose I/O pin. If the device is powered up in Program mode this pin can be used to input serial data to the on chip registers. After a Write command this data is stored in non-volatile memory. When the chip is subsequently powered up in operating mode these values are automatically restored to the on-chip registers and the I/O pin becomes the oscillator output. The DS1073 may be operated over either the commercial (TA = 0C to 70C) or industrial (TA = -40C to + 85C) temperature ranges. AC and DC Electrical Characteristics Tables for operation in both these temperature ranges are given at the end of the data sheet. 1 of 18 090503 DS1073 The DS1073 is available in 8-pin DIP or SOIC packages, allowing the generation of a clock signal easily, economically and using minimal board area. BLOCK DIAGRAM Figure 1 PART NO. SUFFIX -100 -80 -66 -60 INTOSC FREQUENCY 100.000 MHz 80.000 MHz 66.667 MHz 60.000 MHz 2 of 18 DS1073 PIN DESCRIPTIONS IN/OUT Pin (I/O): This pin is the main oscillator output, with a frequency determined by clock reference, M and N dividers. Except in programming mode this pin is always an output. In programming mode this pin is an input and output. External Oscillator Input (OSCIN): This pin can be used to supply an external reference frequency to the device. Crystal Oscillator Connection (XTAL): A crystal can be connected between this pin and OSCIN to provide an alternative frequency reference. The crystal must be used in fundamental mode. If a crystal is not used this pin should be left open. Output Enable Function (OE pin): The DS1073 also features a “synchronous” output enable. When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low, immediately if OUT is already low, or at its next high-to-low transition if OUT is high. This prevents any possible truncation of the output pulse width when the enable is used. While the output is disabled the master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level and the resulting OUT signal. When the enable is released OUT will make its first transition within one to two clock periods of the master clock. Power-Down/Select Function ( PDN / SELX pin): The Power-Down/Select ( PDN / SELX ) pin has a userselectable function determined by one bit (PDN bit) of the user-programmable memory. According to which function is selected, this pin will be referred to as PDN or SELX . If the Power-Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make the device stop oscillating (active low) and go into a reduced power consumption state. The “Enabling Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs will go into a high-impedance state. The power consumption in the power-down state is much less than if OE is used because the internal oscillator (if used) is completely powered down. Even if an external reference or a crystal is used all of the on-chip buffers are powered down to minimize current drain. Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the OE is used. If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/ I select bit is overridden, a high logic level on SELX will select the internal oscillator, a low logic level will select the external reference (or crystal oscillator). Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the reference select mux. This output is especially useful as a buffered output of a crystal defined master frequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is powered down. If this output is not required it can be permanently disabled by setting the EN0 bit to 1, and there will be a corresponding reduction in overall power consumption. 3 of 18 DS1073 USER-PROGRAMMABLE REGISTERS The following registers can be programmed by the user to determine operating frequency and mode of operation. Details of how these registers are programmed can be found in a later section, in this section the function of the registers are described. The register settings are non-volatile, the values being stored automatically in EEPROM when the registers are programmed. Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only be made by powering the device up in “Programming” mode. For them to be become effective the device must then be powered down and powered up again in “Operation” mode. For programming purposes the register bits are divided into two 9-bit words: the MUX word determines mode of operation and prescaler values; the DIV word sets the value of the programmable divider. MUX WORD Figure 2 (MSB) 0* 0* 0* *These bits must be set to 0 EN0 PDN M MSEL DIV1 (LSB) E/ I E/ I This bit selects either the internal oscillator or the external/ crystal reference. 1 = External/Crystal 0 = Internal Oscillator however, if the PDN bit is set to 0 the E/ I bit will be overridden by the logic level on the PDN / SELX pin. Table 1 PDN BIT 0 0 1 1 1 ( PDN / SELX E/ I X X X 0 1 PIN 0 1 0 1 1 OSCILLATOR MODE EXTERNAL/CRYSTAL INTERNAL POWER-DOWN INTERNAL EXTERNAL/CRYSTAL DIV1 This bit allows the master clock to be routed directly to the output (DIV1 = 1). The N programmable divider is bypassed so the programmed value of N is ignored. The frequency of the output (fOUT) will be INTCLK or EXTCLK depending on which reference has been selected. If the Internal clock is selected the M prescaler may still be used, so in this case fOUT = INTOSC/M (which also equals MCLK and INTCLK). If DIV1 = 0 the programmable divider functions normally. MSEL This bit determines whether or not the M prescaler is bypassed. MSEL = 1 will bypass the prescaler. MSEL = 0 will switch in the prescaler, with a divide-by number determined by the M bit. M This bit sets the divide-by number for the prescaler. M = 0 results in divide-by-4, M = 1 results in divideby-2. The setting of this bit is irrelevant if MSEL = 1. 4 of 18 DS1073 Table 2 MSEL DIV1 E/ I M BIT BIT* BIT OPERATION BIT 0 0 0 0 INTERNAL OSCILLATOR DIVIDED BY 4*N 0 0 0 1 INTERNAL OSCILLATOR DIVIDED BY 2*N 0 0 1 X INTERNAL OSCILLATOR DIVIDED BY N 0 1 X X EXTERNAL OSCILLATOR DIVIDED BY N 1 0 1 X INTERNAL OSCILLATOR DIVIDED BY 1 1 0 0 0 INTERNAL OSCILLATOR DIVIDED BY 4 1 0 0 1 INTERNAL OSCILLATOR DIVIDED BY 2 1 1 X X EXTERNAL OSCILLATOR DIVIDED BY 1 *Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN / SELX pin. DIV WORD Figure 3 (MSB) (LSB) N (9-BITS) PDN This bit is used to determine the function of the PDN / SELX pin. If PDN = 0, the PDN / SELX pin can be used to determine the timing reference (either the internal oscillator or an external reference/crystal). If PDN = 1, the PDN / SELX pin is used to put the device into power-down mode. EN0 This bit is used to determine whether the OUT0 pin is active or not. If EN0 = 1, OUT0 is disabled (Highimpedance). If EN0 = 0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no effect on OUT0, but OUT0 is disabled as part of the power-down sequence. N These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to 513, and is equal to the programmed value of N plus 2: Table 3 BIT VALUES 000000000 000000001 . . . . . 111111111 DIVISOR (N) VALUE 2 3 . . . . . 513 NOTE: The maximum value of N is constrained by the minimum output frequency. If the internal clock is selected, INTOSC/(M*N) must be greater than fOUTmin; if the external clock is selected, EXTCLK/N must be greater than fOUTmin. (If DIV1 = 1, then INTOSC or EXTCLK, as applicable, must exceed fOUTmin). 5 of 18 DS1073 OPERATION OF OUTPUT ENABLE Since the output enable, internal master oscillator and/or external master oscillator are likely all asynchronous there is the possibility of timing difficulties in the application. To minimize these difficulties the DS1073 features an “enabling sequencer” to produce predictable results when the device is enabled and disabled. In particular the output gating is configured so that truncated output pulses can never be produced. ENABLE TIMING The output enable function is produced by sampling the OE input with the output from the prescaler mux (MCLK) and gating this with the output from the programmable divider. The exact behavior of the device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge of MCLK. If the actual setup time is less than tSUEM, then one more complete cycle of MCLK will be required to complete the enable or disable operation (see diagrams). This is unlikely to be of any consequence in most applications, and then only if the value for N is small. In general, the output will make its first positive transition between approximately one and two clock periods of MCLK after the rising edge of OE. Figure 4 tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK TO OUT MAX VALUE OF ten = tSUEM + 2 tM + td MIN VALUE OF ten = tSUEM + tM + td DISABLE TIMING If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE and the rising edge of MCLK. If tSU < tSUEM the result will be one additional pulse appearing on the output before disabling occurs. If the device is in divide-by-one mode, the disabling occurs slightly differently. In this case if tSU > tSUEM one additional output pulse will appear, if tSU < tSUEM then two additional output pulses will appear. The following diagrams illustrate the timing in each of these cases. Figure 5 tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK TO OUT tOUTH = WIDTH OF OUTPUT PULSE MAX VALUE OF tdis = tSUEM + td + tOUTH MIN VALUE OF tdis = 0 6 of 18 DS1073 Figure 6 tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK TO OUT tOUTH = WIDTH OF OUTPUT PULSE MAX VALUE OF tdis = tSUEM + td + tOUTH + tM MIN VALUE OF tdis = tSUEM + td + tOUTH SELECT TIMING If the PDN bit is set to 0, the PDN / SELX pin can be used to switch between the internal oscillator and an externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior of OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided by N. FROM INTERNAL TO EXTERNAL CLOCK This is accomplished by a high to low transition on the SELX pin. This transition is detected on the falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the switching will not occur until EXTCLK returns to a low level. Figure 7 Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full cycle of tI on the output after the falling edge of SELX . Then, the “low” time (tLOW) between output pulses will be dependent on the relative timing between tI and tE. The time interval between the falling edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and minimum values of these parameters are: tLOW (min) = tI/2 tLOW (max) = tI/2 + tE tSIE (min) = tI/2 tSIE (max) = 3tI/2 + tE NOTE: In each case there will be a small additional delay due to internal propagation delays. 7 of 18 DS1073 FROM EXTERNAL TO INTERNAL CLOCK This is accomplished by a low to high transition on the SELX pin. In this case the switch is level triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if a constant high-level signal is applied to OSCIN it will not be possible to switch over to the internal reference. (Level triggering was not employed for the switch from internal to external reference as this approach is slower and the internal clock may be running at a much higher frequency than the maximum allowed external clock rate). When SELX is high and a low level is sensed on EXTCLK, OUT0 will be held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed through to OUT0. Figure 8 Depending on the relative timing of the SELX signal and the external clock, there may be up to one full tEhigh period on the output after the rising edge of SELX . Then, the “low” time (tLOW) between output pulses will be dependent on the relative timing between tI and tE. The time interval between the falling edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and minimum values of these parameters are: tLOW (min) = tI/2 tLOW (max) = 3tI/2 + tElow tSIE (min) = tI/2 tSIE (max) = 3tI/2 + tEhigh NOTE: In each case there will be a small additional delay due to internal propagation delays. POWER-DOWN CONTROL If the PDN bit is set to 1, the PDN / SELX pin can be used to power-down the device. If PDN is high the device will run normally. POWER-DOWN If PDN is taken low a power-down sequence is initiated. The “Enabling Sequencer” is used to execute events in the following sequence: 1. Disable OUT (same sequence as when OE is used) and reset N counters. 2. When OUT is low, switch OUT to high-impedance state. 3. Disable MCLK (and OUT0 if EN0 bit = 0), switch OUT0 to high impedance state. 4. Disable internal oscillator and OSCIN buffer. 8 of 18 DS1073 POWER-UP When PDN is taken to a high level the following power-up sequence occurs: 1. Enable internal oscillator and/or OSCIN buffer. 2. Set M and N to maximum values. 3. Wait approximately 256 cycles of MCLK for it to stabilize. 4. Reset M and N to programmed values. 5. Enable OUT0 (assuming EN0 bit = 0). 6. Enable OUT. Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs. Figure 9 POWER-ON RESET When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar to that which occurs when the device is restored from a power-down condition. This sequence comprises two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the outputs: 1. Initialize internal circuitry. 2. Enable internal oscillator and/or OSCIN buffer. 3. Set M and N to maximum values. 4. Wait approximately 256 cycles of MCLK for the oscillator to stabilize. 5. Load M and N programmed values from EEPROM. 6. Enable OUT0 (assuming EN0 = 0). 7. Enable OUT. 9 of 18 DS1073 Figure 10 PROGRAMMING Normally when power is applied to the supply voltage pin the device will enter its normal operating mode following the power-on reset sequence. However the device can be made to enter a programming mode if a pullup resistor is connected between I/O and the supply voltage pin, prior to power-up. The method used for programming is a variant of the 1-Wireä protocol used on a number of Dallas Semiconductor products. HARDWARE The hardware configuration is shown in the diagram. A bus master is used to read and write data to the DS1073’s internal registers. The bus master may have either an open drain or TTL-type architecture. Figure 11 Programming mode is entered by simply powering up the DS1073 with a pullup of approximately 5kW. This will pull the I/O pin above VIH on power-up and initiate the programming mode, causing the DS1073 to internally release the I/O pin (after tPOR), and allow the pullup resistor to pull the pin to the supply rail and await the Master Tx Reset pulse (see diagram). 10 of 18 DS1073 NOTE: To ensure normal operation any external pullup applied to I/O must be greater than 20kW in value. This will cause the I/O pin to remain below VIH on power-up, resulting in normal operation at the end of tSTAB. Figure 12 VCC TRANSACTION SEQUENCE The sequence for accessing the DS1073 via the 1-Wire port is as follows: Initialization Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the DS1073. The presence pulse lets the bus master know that the DS1073 is present and is ready to operate. Figure 13 FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four function commands. All function commands are 8 bits long, and are written lsb first. A list of these commands follows: Write DIV Register [01H] This command allows the bus master to write to the DS1073’s DIV register. 11 of 18 DS1073 Read DIV Register [A1H] This command allows the bus master to read the DS1073’s DIV register. Write MUX Register [02H] This command allows the bus master to write to the DS1073’s MUX register. Read MUX Register [A2H] This command allows the bus master to read the DS1073’s MUX register. TRANSACTION/DATA Immediately following the Function Command, the 9 data bits are written to or read from the DS1073. This data is written/read lsb first. The following diagrams illustrate the timing. Once data transfer is complete, a new transaction sequence can be started by re-initializing the device. Therefore to program both the DIV and MUX registers two complete transaction sequences are required. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated below. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1073 to the master by triggering a delay circuit in the DS1073. During write time slots, the delay circuit determines when the DS1073 will sample the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the DS1073 will hold the data line low overriding the 1 generated by the master. If the data bit is a 1, the DS1073 will leave the read data time slot unchanged. WRITE 1 TIME SLOT Figure 14 WRITE 0 TIME SLOT Figure 15 12 of 18 DS1073 READ DATA TIME SLOT Figure 16 RETURN TO NORMAL OPERATION When programming is complete the DS1073 should be powered down. If the pullup resistor on the I/O pin is removed, normal device operation will be restored next time power is applied. DEFAULT REGISTER VALUES Unless ordered from the factory with specific register program values, the DS1073 is shipped with the following default register values: DIV = 0 0000 0000 (Programmable divider will divide by two) MUX = 0 0011 0100 OUT0 Disabled Power-Down Enabled, Select Disabled M = 4 (Ignored, see MSEL ) MSEL = 1 (M prescaler bypassed) DIV1 = 0 (N Dividers enabled) E/I = 0 (Internal oscillator selected) 13 of 18 DS1073 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V 0°C to 70°C -55°C to +125°C See J - STD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C) (VCC =2.7V to 3.6V) PARAMETER Supply Voltage High-level Output Voltage (I/O, OUT0) Low-level Output Voltage (I/O, OUT0) High-level Input Voltage Low-level Input Voltage High-level Input Current ( PDN / SELX , OE) (OSCIN) Low-level Input Current( PDN / SELX , OE) (OSCIN) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down) SYMBOL VCC VOH VOL CONDITION IOH = -2mA, VCC = MIN IOL = 2mA VIH VIL MIN 2.7 2.4 TYP MAX UNITS 3.6 V V 0.4 V 0.8 V V 1 10 uA uA 2 IIH IIH VIH = 2.4V, VCC = 3.6V VIH = VCC =3.6V IIL IIL VIL=0,VCC=3.6V VIL=0,VCC=3.6V ICC CL = 15 pF (both outputs) 25 ICCQ Power-Down Mode 0.8 14 of 18 -1 -10 uA uA 40 mA uA NOTE DS1073 AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C) (VCC =2.7V to 3.6V) PARAMETER Output Frequency Accuracy Combined Frequency Variation Long Term Stability Maximum Input Frequency Minimum Output Frequency Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ I/O Hi-Z from PDN ↓ OUT0 Hi-Z from PDN ↓ Load Capacitance (I/O, OUT0) Output Duty Cycle I/O OUT0 Jitter SYMBOL fO DfO’ DfO” fOSCIN CONDITION VCC = 3.15V, TA = 25°C Over temp and voltage T = 25°C External clock Crystal reference fOUT MIN TYP -0.5 0 MAX UNITS +0.5 % -1 +1 % -0.5 +0.5 50 % MHz 25 MHz 29.3 tPOR + tSTB tSTABb tSTAB tPDN tPDN 0.1 0.1 0.1 CL 15 40 40 J 1 1 1 1 1 NOTES 1 2 kHz 3 ms ms ms ms ms 4, 5 5 5, 6 pF 7 60 60 % % 100 pS 8 NOTES: 1. Additive to DfO’. 2. This is the maximum frequency which can be applied to OSCIN, or, the maximum crystal frequency that can be used. If a crystal is used it must be operated in fundamental mode. 3. The values of M, N and the frequency of OSCIN (if used) must be chosen so that this spec is met. 4. This is the time from when VCC is applied until the output starts oscillating. 5. When the device is initially powered up, or restored from the power-down mode, OE should be asserted (high). Otherwise the start of the tSTAB interval will be delayed until OE goes high. OE can subsequently be returned to a low level during the tSTAB interval to force out low after the tSTAB, interval. If the external mode is selected tSTAB will be a function of the OSCIN period, i.e., external clock frequency. See “Calculated Parameters” to determine the value of tSTAB in this case. 6. Although OE does not normally affect OUT0 operation, if OE is held low during power-up the start of the tSTAB period will be delayed until OE is asserted. If OE remains low, OUT0 will not start. 7. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency. 8. Parameter given is 3 sigma. 15 of 18 DS1073 AC ELECTRICAL CHARACTERISTICS – CALCULATED PARAMETERS The following characteristics are derived from various device-operating parameters (frequency, mode, etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due to internal device setup times and propagation delays. However, the equations in the max column can be used to estimate a more accurate idea of typical device performance than the guaranteed values. PARAMETER I/O ↑ from OE ↑ I/O ↓ from OE ↓ N=1 N≥2 SELX ↓ to OUT0 ↑ -Internal to External -External to Internal Break during SEL switch -Internal to External -External to Internal PDN ↓ to I/O Hi-Z N=1 N≥2 PDN ↓ to OUT0 Hi-Z N=1 N≥2 PDN ↑ to I/O ↑ PDN ↑ to OUT0 ↑ I/O ↑ after Power-up OUT0 ↑ after Power-up SYMBOL tEN tDIS tDIS CONDITION MIN tM tOUTH 0 MAX 2tM tOUTH + tM tOUTH tSIE tSEI tI/2 tI/2 3tI/2 + tE 3tI/2 + tEhigh tLOW tLOW tI/2 tI/2 tI/2 + tE 3tI/2 + tElow tPDN tPDN tOUTH 0 tOUTH + tM tOUTH tPDN tPDN tOUTH 0 tOUTH + tM tOUTH tSTAB tSTAB 256tM 256tM 256tM 256tM 16 of 18 DS1073 DC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C) (VCC = 2.7V to 3.6V) PARAMETER Supply Voltage High-level Output Voltage (I/O, OUT0) Low-level Output Voltage (I/O, OUT0) High-level Input Voltage Low-level Input Voltage High-level Input Current ( PDN / SELX , OE) (OSCIN) Low-level Input Current( PDN / SELX , OE) (OSCIN) Supply Current (Active) DS1073-100 DS1073-80 DS1073-66 DS1073-60 Standby Current (power-down) SYMBOL VCC VOH CONDITION VOL IOL = 2 mA IOH = -2 mA, VCC = MIN VIH VIL MIN TYP MAX 2.7 3.6 2.4 0.4 V 0.8 V V 1 10 uA uA 2 IIH IIH VIH =2.4V,VCC = 3.6V VIH =VCC=3.6V IIL IIL VIL=0,VCC=3.6V VIL=0,VCC=3.6V ICC CL = 15 pF (both outputs) 25 ICCQ Power-Down Mode 0.8 17 of 18 UNITS V V -1 -10 uA uA 50 mA uA NOTES DS1073 AC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C) (VCC = 2.7V – 3.6V) PARAMETER Output Frequency Accuracy Combined Frequency Variation Long Term Stability SYMBOL fO DfO’ DfO” Maximum Input Frequency fOSCIN Minimum Output Frequency fOUT Power-Up Time Enable OUT from PDN ↑ Enable OUT0 from PDN ↑ I/O Hi-Z from PDN ↓ OUT0 Hi-Z from PDN ↓ Load Capacitance (I/O, OUT0) Output Duty Cycle I/O OUT0 Jitter CONDITION VCC = 3.15V, TA = 25°C Over temp and voltage MIN -0.5 TYP MAX 0 +0.5 % -2.5% 2.5% % -0.5 +0.5 50 % MHz 25 MHz External clock Crystal reference 29.3 tPOR + tSTAB tSTAB tSTAB tPDN tPDN CL 40 40 NOTES 1 2 kHz 3 0.1 1 ms 4, 5 0.1 0.1 1 1 1 1 ms ms ms ms 5 5, 6 pF 7 15 J UNITS 60 60 % % 100 pS 8 NOTES: 1. Additive to DfO’. 2. This is the maximum frequency which can be applied to OSCIN, or the maximum crystal frequency that can be used. If a crystal is used, it must be operated in fundamental mode. 3. The values of M, N and the frequency of OSCIN (if used) must be chosen so that this spec is met. 4. This is the time from when VCC is applied until the output starts oscillating. 5. When the device is initially powered up or restored from the power-down mode, OE should be asserted (high). Otherwise the start of the tstab interval will be delayed until OE goes high. OE can subsequently be returned to a low level during the tstab interval to force out low after the tstab interval. If the external mode is selected, tstab will be a function of the OSCIN period, i.e., external clock frequency. See “Calculated Parameters” to determine the value of tstab in this case. 6. Although OE does not normally affect OUT0 operation, if OE is held low during power-up, the start of the tstab period will be delayed until OE is asserted. If OE remains low, OUT0 will not start. 7. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency. 8. Parameter given is a typical max. 18 of 18