TI TLC551CDBLE

TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
D
D
D
D
D
D
D
D
D
D, DB, P, OR PW PACKAGE
(TOP VIEW)
Very Low Power Consumption
1 mW Typ at VDD = 5 V
Capable of Operation in Astable Mode
GND
TRIG
OUT
RESET
CMOS Output Capable of Swinging Rail
to Rail
High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
VDD
8
THRES
6
CONT
5
R
7
3
6
4
5
VDD
DISCH
THRES
CONT
RESET
4
R1
R
Single-Supply Operation From 1 V to 15 V
3
1
R
TRIG
2
R
7
description
OUT
S
Functionally Interchangeable With the
NE555; Has Same Pinout
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
8
2
functional block diagram
Output Fully Compatible With CMOS, TTL,
and MOS
Low Supply Current Reduces Spikes
During Output Transitions
1
DISCH
1
GND
The TLC551 is a monolithic timing circuit
RESET can override TRIG, which can override THRES.
fabricated using the TI LinCMOSprocess. The
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared
to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result,
more accurate time delays and oscillations are possible. Power consumption is low across the full range of
power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs
should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC551C is characterized for operation from 0°C to 70°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044A – FEBRUARY 1984 – REVISED MAY 1997
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VDD
RANGE
SMALL
OUTLINE
(D)
0°C to 70°C
1 V to 16 V
TLC551CD
CHIP FORM
(Y)
SSOP
(DB)
PLASTIC DIP
(P)
TSSOP
(PW)
TLC551CDBLE
TLC551CP
TLC551CPWLE
TLC551Y
The D package is available taped and reeled. Add the suffix R (e.g., TLC551CDR). The DB and PW packages are only
available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC551CDBLE). Chips are
tested at 25°C.
FUNCTION TABLE
RESET
VOLTAGE †
TRIGGER
VOLTAGE †
THRESHOLD
VOLTAGE †
OUTPUT
DISCHARGE
SWITCH
<MIN
Irrelevant
Irrelevant
Low
On
>MAX
<MIN
Irrelevant
High
Off
>MAX
>MAX
>MAX
Low
On
>MAX
>MAX
<MIN
As previously established
† For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.
TLC551Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC551. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CONT
(5)
VDD
(8)
THRES
(6)
R
RESET
(4)
R1
R
(3)
OUT
1
S
50
R
TRIG
(2)
R
(7)
DISCH
(1)
GND
64
RESET can override TRIG, which can override THRES.
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
equivalent schematic
COMPONENT COUNT
OUT
DISCH
TLC551, TLC551Y
LinCMOS TM TIMERS
GND
3
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RESET
TRIG
39
5
Transistors
Resistors
THRES
V DD
CONT
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to VDD
Sink current, discharge or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
Source current, output, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
D
DB
P
PW
725 mW
525 mW
1000 mW
525 mW
5.8 mW/°C
4.2 mW/°C
8.0 mW/°C
4.2 mW/°C
464 mW
336 mW
640 mW
336 mW
recommended operating conditions
MIN
MAX
Supply voltage, VDD
1
15
V
Operating free-air temperature range, TA
0
70
°C
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, VDD = 1 V
PARAMETER
VIT
Threshold voltage
IIT
Threshold current
VI(TRIG)
Trigger voltage
II(TRIG)
Trigger current
VI(RESET)
Reset voltage
II(RESET)
Reset current
TEST CONDITIONS
Control voltage (open circuit) as a percentage of
supply voltage
IOL = 100 µA
on stage voltage
Discharge switch on-stage
Discharge switch off-stage
off stage voltage
VOH
High level output voltage
High-level
IOH = – 10 µA
VOL
Low level output voltage
Low-level
IOL = 100 µA
IDD
Supply current
See Note 2
TA†
25°C
MIN
TYP
MAX
0.475
0.67
0.85
Full range
0.45
0.875
25°C
10
70°C
75
25°C
0.15
Full range
0.1
0.33
10
70°C
75
25°C
0.4
Full range
0.3
0.7
10
70°C
75
70°C
66.7%
25°C
0.02
Full range
0.1
70°C
0.5
25°C
0.6
Full range
0.6
25°C
Full range
1
0.03
0.15
V
nA
V
0.2
0.25
15
V
pA
0.98
Full range
V
pA
0.2
25°C
25°C
0.425
1
25°C
V
pA
0.45
25°C
UNIT
100
150
V
µA
† Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, VDD = 2 V
PARAMETER
VIT
Threshold voltage
IIT
Threshold current
VI(TRIG)
Trigger voltage
II(TRIG)
Trigger current
VI(RESET)
Reset voltage
II(RESET)
Reset current
TEST CONDITIONS
Control voltage (open circuit) as a percentage of
supply voltage
on stage voltage
Discharge switch on-stage
IOL = 1 mA
Discharge switch off-stage
off stage voltage
VOH
High level output voltage
High-level
IOH = – 300 µA
VOL
Low level output voltage
Low-level
IOL = 1 mA
IDD
Supply current
See Note 2
TA†
25°C
MIN
TYP
MAX
0.95
1.33
1.65
Full range
0.85
1.75
25°C
10
70°C
75
25°C
0.4
Full range
0.3
0.67
10
70°C
75
25°C
0.4
Full range
0.3
1.1
10
70°C
75
70°C
66.7%
25°C
0.03
Full range
0.1
70°C
0.5
25°C
1.5
Full range
1.5
25°C
Full range
1.5
0.07
0.2
V
0.3
250
400
† Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
nA
0.35
65
V
pA
1.9
Full range
V
pA
0.25
25°C
25°C
0.95
1.8
25°C
V
pA
1.05
25°C
UNIT
V
µA
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
VIT
Threshold voltage
IIT
Threshold current
VI(TRIG)
Trigger voltage
II(TRIG)
Trigger current
VI(RESET)
Reset voltage
II(RESET)
Reset current
TEST CONDITIONS
Control voltage (open circuit) as a percentage of
supply voltage
on stage voltage
Discharge switch on-stage
IOL = 10 mA
Discharge switch off-stage
off stage voltage
VOH
High level output voltage
High-level
IOH = – 1 mA
IOL = 8 mA
VOL
Low level output voltage
Low-level
IOL = 5 mA
2 mA
IOL = 3
3.2
IDD
Supply current
See Note 2
TA†
25°C
MIN
TYP
MAX
2.8
3.3
3.8
Full range
2.7
3.9
25°C
10
70°C
75
25°C
1.36
Full range
1.26
1.66
10
70°C
75
25°C
0.4
Full range
0.3
1.1
10
70°C
75
70°C
66.7%
25°C
0.14
Full range
0.1
70°C
0.5
25°C
4.1
Full range
4.1
25°C
0.21
0.13
Full range
pA
0.5
V
nA
V
0.4
0.3
0.4
0.08
Full range
25°C
V
0.5
Full range
25°C
1.5
4.8
Full range
V
pA
0.6
25°C
25°C
1.96
1.8
25°C
V
pA
2.06
25°C
UNIT
V
0.3
0.35
170
350
500
µA
† Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, VDD = 15 V
PARAMETER
VIT
Threshold voltage
IIT
Threshold current
VI(TRIG)
Trigger voltage
II(TRIG)
Trigger current
VI(RESET)
Reset voltage
II(RESET)
Reset current
TEST CONDITIONS
Control voltage (open circuit) as a percentage of
supply voltage
on stage voltage
Discharge switch on-stage
IOL = 100 mA
Discharge switch off-stage
off stage voltage
IOH = – 10 mA
VOH
High level output voltage
High-level
IOH = – 5 mA
IOH = – 1 mA
IOL = 100 mA
VOL
Low level output voltage
Low-level
IOL = 50 mA
IOL = 10 mA
IDD
Supply current
See Note 2
TA†
25°C
9.45
10.55
Full range
9.35
10.65
MIN
TYP
25°C
10
70°C
75
25°C
4.65
Full range
4.55
5
10
70°C
75
0.4
Full range
0.3
1.1
5.35
10
70°C
75
70°C
66.7%
25°C
0.77
Full range
1.5
0.1
70°C
0.5
25°C
12.5
Full range
12.5
25°C
13.5
Full range
13.5
25°C
14.2
Full range
14.2
25°C
V
V
pA
1.7
1.8
25°C
V
pA
1.8
25°C
UNIT
pA
5.45
25°C
25°C
MAX
V
nA
14.2
14.6
V
14.9
1.28
Full range
3.2
3.6
25°C
0.63
Full range
1
1.3
25°C
0.12
Full range
V
0.3
0.4
25°C
360
Full range
600
800
µA
† Full range is 0°C to 70°C.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Initial error of timing interval‡
Supply voltage sensitivity of timing interval
tr
tf
Rise time, output pulse
fmax
Maximum frequency in astable mode
Fall time, output pulse
VDD = 5 V to 15 V,,
CT = 0.1 µF,
RA = RB = 1 kΩ to 100 kΩ,,
See Note 3
RL = 10 MΩ,
MΩ
CL = 10 pF
RA = 470 Ω,
CT = 200 pF
RB = 200 Ω,
See Note 3
MIN
1.2
TYP
MAX
1%
3%
0.1
0.5
20
75
15
60
1.8
UNIT
%/ V
ns
MHz
‡ Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
NOTE 3: RA, RB, and CT are as defined in Figure 3.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at VDD = 5 V, TA = 25°C
PARAMETER
VIT
IIT
Threshold voltage
VI(TRIG)
Trigger voltage
II(TRIG)
Trigger current
VI(RESET)
II(RESET)
Reset voltage
TEST CONDITIONS
MIN
TYP
MAX
2.8
3.3
3.8
1.36
1.66
Threshold current
10
0.4
IOL = 10 mA
pA
1.1
1.5
V
pA
0.14
Discharge switch off-state current
0.5
0.1
High-level output voltage
VOL
V
66.7%
Discharge switch on-state voltage
VOH
pA
10
Control voltage (open circuit) as a percentage of supply voltage
V
1.96
10
Reset current
UNIT
IOH = – 1 mA
IOL = 8 mA
Low-level output voltage
4.1
IOL = 5 mA
IOL = 3.2 mA
V
nA
4.8
V
0.21
0.4
0.13
0.3
0.08
0.3
IDD
Supply current
See Note 2
170
350
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
V
µA
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES (TO DISCHARGE
OUTPUT FROM TRIGGER AND THRESHOLD
SHORTED TOGETHER)
vs
SUPPLY VOLTAGE
DISCHARGE SWITCH ON-STATE RESISTANCE
vs
FREE-AIR TEMPERATURE
Discharge Switch On-State Resistance – Ω
70
VDD = 2 V, IO = 1 mA
40
VDD = 5 V, IO = 10 mA
20
10
7
600
t PHL , t PLH – Propagation Delay Times – ns
100
VDD = 15 V, IO = 100 mA
4
2
IO(on) ≥ 1 mA
CL ≈ 0
TA = 25°C
500
400
300
tPHL
200
tPLH‡
100
0
1
0
25
50
75
100
0
2
4
6
8
10
12
14 16
18 20
VDD – Supply Voltage – V
TA – Free-Air Temperature – °C
‡ The effects of the load resistance on these values must be
taken into account separately.
Figure 1
Figure 2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
VDD
0.1 µF
RA
tc(H)
VDD
0.1 µF
4
7
6
RB
2
tc(L)
5
8
VDD
CONT
RESET
TLC551
DISCH
tPHL
RL
3
2/3 VDD
Output
OUT
THRES
CL
1/3 VDD
TRIG
GND
CT
GND
1
tPLH
CIRCUIT
TRIGGER AND THRESHOLD VOLTAGE WAVEFORM
Figure 3. Astable Operation
Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT
charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB
only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle
(tc(H)) and low during the discharge cycle (tc(L) ). The duty cycle is controlled by the values of RA, and RB, and CT, as
shown in the equations below.
[ CT (RA ) RB) In 2 (In 2 + 0.693)
[ CT RB In 2
+ tc(H) ) tc(L) [ CT (RA ) 2RB) In 2
t
R
c(L)
B
Output driver duty cycle +
[
1 –
t
)
t
R
)
2R
c(H)
c(L)
A
B
t
c(H)
t
c(L)
Period
Output waveform duty cycle
+t
t
c(H)
c(H)
t
)
c(L)
[ R )RB2R
A
B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from TRIG and THRES to DISCH. These
delay times add directly to the period and create differences between calculated and actual values that increase with
frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of
timing error in the calculation when RB is very low or ron is very high.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
ƪ ǒ
ƪ ǒ
Ǔƫ
Ǔƫ
APPLICATION INFORMATION
The equations below provide better agreement with measured values.
t
t
+ CT (RA ) RB) In
3 – exp
+ CT (RB ) ron) In
c(L)
3 – exp
c(H)
–t
C
C
T
(R
B
–t
T
(R
) ron) ) tPHL
PLH
) RB) ) tPLH
PHL
A
These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number
or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely
high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted
t
t
c(H)
with good results. Duty cycles less than 50%
require that c(H) <1 and possibly RA ≤ ron. These
t
t
t
c(H)
c(L)
c(L)
conditions can be difficult to obtain.
)
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input voltage
between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC551, TLC551Y
LinCMOS TIMERS
SLFS044B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
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