iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 1/22
FEATURES
APPLICATIONS
♦ Hall sensor array with automatic signal control
♦ Differential scanning for excellent magnetic stray field
tolerance
♦ Real-time tracking interpolation of up to 256 angle steps,
permitting up to 12,000 rpm
♦ Ratiometric output with 0.5 V to 4.5 V or 0 V to 5 V and
selectable full-scale angle of 90, 180, 270 or 360 degrees
♦ Programmable zero position
♦ Fast, serial absolute angle data output
♦ Easy daisy chaining of multiple sensors: all analog/digital
outputs can be used in buses
♦ Loss-of-magnet and excessive frequency indication via error
output
♦ Non-volatile setup provided by 3x reconfigurable Zener zap
ROM
♦ 5 V single-supply operation
♦ Power-saving standby function
♦ Operational temperature range of -40 to +125 °C
♦ Space-saving 10-pin DFN package measuring 4 mm x 4 mm
♦ Contactless potentiometer
♦ Absolute 360° angle sensor
♦ Magnetic rotary encoders
PACKAGES
DFN10 4 x 4 mm
BLOCK DIAGRAM
VDD
B
PSIN
VZAP
MA
8 BIT
B
NCOS
SLO
B
PCOS
B
NSIN
HALL SENSORS
AMP
SIN / DIG
SLI
ZAPPING
SERIAL INTERFACE
NERR
2
2
SIN + COS
SIGNAL
CONTROL
CONVERSION
LOGIC
PSMO
I/O INTERFACE
iC-MP
PSMI
POWER SAVE MODE
BIAS / VREF
LAO
D/A CONVERTER
GND
C090715
Copyright © 2010 iC-Haus
http://www.ichaus.com
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 2/22
DESCRIPTION
iC-MP consists of a quadruple Hall sensor array
which has been optimized for the magnetic measurement of an axis angle. The array permits errortolerant adjustment of the magnet, reducing the time
and effort required assembly. The integrated signal
conditioning unit provides a differential sine/cosine
signal at its outputs. The sensor generates one sine
cycle per full rotation of the magnet, enabling the
angle to be clearly determined. At the same time
the internal amplitude control unit produces a regulated output amplitude of 2 Vpp, regardless of variations in the magnetic field strength, supply voltage
and temperature. Furthermore, error signals are provided which report any magnet loss and an excessively high RPM speed.
With the aid of the integrated 8-bit sine-to-digital
converter the axis angle is determined from the
sine/cosine signals. The absolute position angle is
output via the serial interface together with a bit indicating an error. The maximum resolution of 8 bits is
maintained up to revolutions of 12,000 rpm.
The absolute angle is converted back to a linear analog output voltage using the internal D/A converter.
The analog output voltage range can be programmed
to be either rail to rail or 10 % to 90 % of the supply
voltage. The angular range of the analog signal is
configurable to 90°, 180°, 270° or 360°.
iC-MP can be easily cascaded, enabling scanning of
multiple axes. In Fast Scanning Mode all devices
connected in a queue are read consecutively. In Slow
Scanning Mode (Power Save Mode) each individual
device is booted up before the serial data or analog
output voltage is put on the common bus.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 3/22
CONTENTS
PACKAGES
4
OPERATING MODES
11
ABSOLUTE MAXIMUM RATINGS
5
THERMAL DATA
5
PROGRAMMING MODE
ENERR . . . . . . . . . . . . . . . . . . . . .
Calculating the position offset . . . . . . . . .
CRCID . . . . . . . . . . . . . . . . . . . . . .
12
14
14
15
ELECTRICAL CHARACTERISTICS
6
FAST SCANNING MODE
16
SLOW SCANNING MODE
18
SENSOR PRINCIPLE
8
HALL SENSOR POSITION AND INTERNAL
ANALOG SIGNALS
8
APPLICATION CIRCUITS
Stand-alone example . . . . . . . . . . . . .
20
20
LINEAR ANALOG OUTPUT (LAO)
9
TEST MODES
21
DESIGN REVIEW: Notes On Chip Functions
21
SERIAL OUTPUT (SLO)
10
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 4/22
PACKAGES
PIN CONFIGURATION DFN10
PIN FUNCTIONS
No. Name Function
1
10
2
9
3
4
5
iC-MP
...
...yyww
8
7
6
1
2
3
4
5
6
7
8
9
10
PSMI
GND
PSMO
LAO
MA
SLO
SLI
VZAP
VDD
NERR
TP
The thermal pad must be connected to ground potential on the PCB.
Orientation of the logo ( MP CODE ...) is subject to alteration.
Power Save Mode Input
Ground
Power Save Mode Output
Linear Analog Output
Serial Clock Input
Serial Data Output
Serial Data Input
Zapping Voltage Input
+5 V Supply Voltage
Error Message Output (low active)
/ Serial ROM Data Output
Thermal Pad
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 5/22
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Supply Voltage at VDD
-0.3
6
V
G002 I()
Current in VDD
-20
20
mA
G003 V()
Voltage at pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR
-0.3
VDD +
0.3
V
G004 V()
Voltage at pin VZAP
-0.3
8
V
G005 I()
Current in pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR, VZAP
-10
10
mA
G006 I()
Current in pins PSMI, PSMO, LAO,
MA, SLO, SLI, NERR, VZAP
Pulse width < 10µs
-100
100
mA
G007 Vd()
ESD Susceptibility at all pins
HBM, 100 pF discharged through 1.5 kΩ
2
kV
G008 Tj
Junction Temperature
-40
125
°C
G009 Ts
Storage Temperature Range
-40
125
°C
THERMAL DATA
Operating conditions: VDD = 5 V ±10 %
Item
No.
T01
T02
Symbol
Parameter
Conditions
Unit
Min.
Ta
Rthja
Operation Ambient Temperature Range
Thermal Resistance, Chip to Ambient
Typ.
-40
Package mounted on PCB, thermal pad at
approx. 2 cm² cooling area
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
Max.
125
40
°C
K/W
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 6/22
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
4.5
5
5.5
V
8
12
mA
200
µA
V
General
001
VDD
Supply Voltage
002
I(VDD)
Supply Current in VDD
PSMI = lo, other pins open
003
I(VDD)sb
Standby Supply Current
PSMI = hi
004
VDDon
Power-On Threshold
Increasing voltage VDD
3.0
4.1
005
VDDoff
Power-Down Threshold
Decreasing voltage VDD
2.6
3.9
006
007
VDDhys
Hysteresis
VDDhys = VDDon - VDDoff
200
ton()1
Turn-On Delay Following
Power-On
Time to data valid after enabling,
VDD: VDDoff → VDDon
008
ton()2
Turn-On Delay Following Standby Time to data valid after standby,
PSMI: hi → lo
009
Vc()hi
Clamp Voltage hi at
PSMI, MA, SLI, NERR
VDD = 0 V; I() = 1 mA
010
Vc()hi
Clamp Voltage hi at
PSMO, LAO, SLO
011
Vc()lo
V
mV
1
ms
900
µs
0.3
1.6
V
VDD = 0 V; I() = 4 mA
0.3
1.6
V
Clamp Voltage lo at
PSMI, PSMO, LAO, MA, SLO,
SLI, NERR, VDD, VZAP
I() = -4 mA
-1.5
-0.3
V
At surface of chip
100
kA/m
12 000
rpm
Hall Sensor Array
101
Hext
Operating Magnetic Field
Strength
20
102
RPM
Permissible RPM Speed
103
ferr()
Excessive Frequency Alarm
104
fmag()
Magnetic Field Frequency
105
dsens
Diameter of Hall Sensor Array
106
xpac
Chip Placement Tolerance
Versus DFN10 package outlines
-0.2
0.2
mm
107
φpac
Chip Tilt Angle
Versus DFN10 package outlines
-3
3
DEG
108
hpac
Distance Surface of Package to
Surface of Chip
DFN10 package
ENERR(1) = 1; NERR: hi → lo
50
1
kHz
200
2
Hz
mm
400
µm
Sine-To-Digital Converter
301
RES
Converter Resolution
302
HYS
Converter Hysteresis
303
AAabs
Absolute Angle Accuracy
D/A Converter And Ratiometric Output LAO
401 RES()
D/A Converter Resolution
402
403
404
Iload()
Permissible Output Current
dV0()hi
Output Voltage hi, Rail-To-Rail
dV0()lo
Output Voltage lo, Rail-To-Rail
Per 360 degree
Magnet with 4 mm in diameter, axis centered to
chip
8
bit
1.4
DEG
-3
MODE(1:0) = 00 (range 360°)
MODE(1:0) = 01 (range 270°)
MODE(1:0) = 10 (range 180°)
MODE(1:0) = 11 (range 90°)
3
8
7.5
7
6
-1
DEG
bit
bit
bit
bit
1
mA
dV0()hi = V(VDD) - V(LAO), MODE(3) = 0;
I() = -1 mA
I() = 0 mA
170
85
mV
mV
MODE(3) = 0;
I() = 1 mA
I() = 0 mA
170
85
mV
mV
405
dV1()hi
Output Voltage hi, 10/90% Range MODE(3) = 1; I() = -1...+1 mA
85
95
%VDD
406
dV1()lo
Output Voltage lo, 10/90% Range MODE(3) = 1; I() = -1...+1 mA
5
15
%VDD
407
Ilk()
Leakage Current
V(LAO) = 0...VDD, PSMI = hi
-5
5
408
SR()hi
Slew Rate hi
V(LAO): 20% → 80% of range
2
V/µs
409
SR()lo
Slew Rate lo
V(LAO): 80% → 20% of range
2
V/µs
µA
Zapping Input VZAP
501
Vt1()hi
Voltage Threshold hi vs. GND
502
Vt1()lo
Voltage Threshold lo vs. GND
2
0.8
V
V
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 7/22
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
503
Vt1()hys
Threshold Hysteresis
Vt1()hys = Vt1()hi − Vt1()lo
504
Vt2()hi
Voltage Threshold hi vs. VDD
Vt2()hi = V() - VDD,
VDD = 5 V ±5%, Tj = 10 ... 40 °C
505
Vt2()lo
Voltage Threshold lo vs. VDD
Vt2()lo = V() - VDD;
VDD = 5 V ±5%, Tj = 10 ... 40 °C
506
Vt2()hys
Threshold Hysteresis
Vt2()hys = Vt2()hi − Vt2()lo
20
507
Vzap()
Permissible Zapping Voltage
VDD = 5 V ±5%, Tj = 10 ... 40 °C
7.3
508
Izap()
Required Zapping Current
VDD = 5 V ±5%, Tj = 10 ... 40 °C
Typ.
230
Max.
400
mV
1.3
V
0.7
V
150
7.4
mV
7.5
V
90
mA
2
V
Serial Interface and Power Save Mode Inputs: MA, SLI, PSMI
601
Vt()hi
Input Threshold Voltage hi
602
Vt()lo
Input Threshold Voltage lo
603
Vt()hys
Input Hysteresis
Vt()hys = Vt()hi − Vt()lo
604
Ipu()
Input Pull-up Current
V() = 0...VDD − 1 V
-240
605
fclk(MA)
Permissible Clock Frequency at
MA
Normal mode
0.080
606
tzap(MA)
Permissible Zapping Cycle at MA Programming mode,
VDD = 5 V ±5%, Tj = 10 ... 40 °C
607
tout(MA)
Interface Timeout
0.8
V
230
mV
4.5
-120
5
Time from MA last edge to SLO lo → hi
-10
µA
10
MHz
5.5
µs
15
µs
V
Serial Interface and Power Save Mode Outputs: SLO, PSMO
701
Vs()hi
Saturation Voltage hi
Vs()hi = VDD − V(), I() = -4 mA
0.4
702
Vs()lo
Saturation Voltage lo
I() = 4 mA
0.4
V
703
Isc()hi
Short-Circuit Current hi
V() = 0 V
-90
-10
mA
704
Isc()lo
Short-Circuit Current lo
V() = VDD
10
90
mA
705
tr()
Rise Time
CL() = 50 pF, V(): 20 → 80%
60
ns
706
tf()
Fall Time
CL() = 50 pF, V(): 80 → 20%
60
ns
I/O Interface NERR
801
Vs()lo
Saturation Voltage lo
I() = 4 mA
0.4
V
802
Ilk()
Leakage Current
V() = 0...VDD, PSMI = hi
-5
5
µA
803
Isc()lo
Short-Circuit Current lo
V() = VDD
4.5
90
mA
55
%VDD
Test Signals at NERR, LAO, PSMO (iC-Haus device test only)
902
VREF
904
Vpp(PSIN) Pos. Sine Sensor AC Signal
at NERR
Reference Voltage at LAO
Op. mode: Test 2
Op. mode: Test 0
45
50
2
Vpp
905
Vdc(PSIN) Pos. Sine Sensor DC Signal
at NERR
Op. mode: Test 0
VREF
V
906
Vpp(PCOS) Pos. Cosine Sensor AC Signal
at LAO
Op. mode: Test 0
2
Vpp
907
Vdc(PCOS) Pos. Cosine Sensor DC Signal
at LAO
Op. mode: Test 0
VREF
V
908
Vpp(NSIN) Neg. Sine Sensor AC Signal
at NERR
Op. mode: Test 1
2
Vpp
909
Vdc(NSIN) Neg. Sine Sensor DC Signal
at NERR
Op. mode: Test 1
VREF
V
910
Vpp(NCOS) Neg. Cosine Sensor AC Signal
at LAO
Op. mode: Test 1
2
Vpp
911
Vdc(NCOS) Neg. Cosine Sensor DC Signal
at LAO
Op. mode: Test 1
VREF
V
912
dVoff()
Diff. Sine and Cosine Signal
Offsets
dVoff() = V(PSIN) − V(NSIN),
dVoff() = V(PCOS) − V(NCOS)
-50
50
913
VR()
Sine/Cosine AC Signal Ratio
VR() = V(PSIN) / V(PCOS),
VR() = V(NSIN) / V(NCOS)
0.95
1.05
mV
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 8/22
SENSOR PRINCIPLE
S
coder system or a contactless potentiometer. A diametrically magnetized, cylindrical permanent magnet
made of neodymium iron boron (NdFeB) or samarium
cobalt (SmCo) generates optimum sensor signals. The
diameter of the magnet should be in the range of 3 mm
to 6 mm.
N
z
y
+Bz
B
x
-Bz
C151107-1
Figure 1: Sensor principle
In conjunction with a rotating permanent magnet, the
iC-MP module can be used to create a complete en-
The iC-MP has four Hall sensors adapted for angle
determination and to convert the magnetic field into
a measurable Hall voltage. Only the z-component of
the magnetic field is evaluated, whereby the field lines
pass through two opposing Hall sensors in the opposite direction. Figure 1 shows an example of field vectors.
The arrangement of the Hall sensors is selected so
that the mounting of the magnets relative to iC-MP is
extremely tolerant. Two Hall sensors combined provide
a differential Hall signal. When the magnet is rotated
around the longitudinal axis, sine and cosine output
voltages are produced which can be used to determine
angles.
HALL SENSOR POSITION AND INTERNAL ANALOG SIGNALS
The Hall sensors are placed in the center of the DFN10
package at 90° to one another and arranged in a circle
with a diameter of 2 mm as shown in Figure 2.
Pin 1 Mark
1
PSIN
10
PCOS
2
9
3
8
4
7
5
NCOS
In order to calculate the angle position of a diametrically polarized magnet placed above the device a difference in signal is formed between opposite pairs of
Hall sensors, resulting in the sine being VSIN = VPSIN VNSIN and the cosine VCOS = VPCOS - VNCOS . The zero
angle position of the magnet is marked by the resulting
cosine voltage value being at a maximum and the sine
voltage value at zero.
NSIN
6
(top view)
This is the case when the south pole of the magnet is
exactly above the PCOS sensor and the north pole is
above sensor NCOS, as shown in Figure 3. Sensors
PSIN and NSIN are placed along the pole boundary so
that neither generate a Hall signal.
C040110-1
Figure 2: Position of the Hall sensors
When a magnetic south pole comes close to the surface of the package the resulting magnetic field has a
positive component in the +z direction (i.e. from the top
of the package) and the individual Hall sensors each
generate their own positive signal voltage.
When the magnet is rotated counterclockwise the
poles then also cover the PSIN and NSIN sensors, resulting in the sine and cosine signals shown in Figure
4 being produced. The signals are internal but can be
made externally available for test purposes (see chapter ’TEST MODES’).
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 9/22
1
10
S
2
9
2
4
7
N
5
10
2
9
8
3
8
4
7
4
6
5
(top view)
7
N
α>0
6
α=0
0
VSIN= VPSIN- VNSIN VCOS= VPCOS- VNCOS
6
+2V
(Top view)
S
9
N
8
1
3
5
3
S
1
10
C0260809-1
Figure 3: Zero position of the magnet
-90°
90°
180°
270°
360°
α
-2V
C0260809-1
Figure 4: Pattern of the internal analog sensor signals with the angle of rotation
LINEAR ANALOG OUTPUT (LAO)
The LAO pin provides a linear analog output voltage
representing the actual position. The output voltage
can be either rail to rail or within a range of 10% to
90% of the supply voltage VDD, depending on the programmed configuration. In 10%-to-90% mode a shortcircuit with VDD or GND is recognizable.
The zero position therefore begins at the minimum voltage (either GND or 10% of VDD) and reaches its maximum (either VDD or 90% of VDD) at the selected angular range limit (90°, 180°, 270° or 360°), depending
on the chosen configuration.
LAO is tristate when the device is disabled.
Figure 5: Linear analog output voltage
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 10/22
SERIAL OUTPUT (SLO)
T1
T2
T3
T4
T5
tout
MA
SLO
ACK START
D1
D7
NERR CRC3
D0
CRC0
STOP
Figure 6: Serial data timing
D0 to D7 make up the absolute position data with respect to the programmed position offset (OFFSET1 xor
OFFSET2 xor OFFSET3).
The absolute position is latched by a low to high transition at MA (see T1).
After an acknowledge (T2) at SLO iC-MP requests processing time until the start condition (T3) is sent. Processing time must be provided in Slow Scanning Mode
during startup.
With rising edge T4 at the clock pin the most significant
bit (D7) is placed on the serial data line SLO. After T5
has elapsed the controller can stop clocking at MA and
the device is ready to latch a new position after a timeout (tout ). If the controller continues to clock in a daisy
chain in Fast Scanning Mode after T5 has elapsed, the
second device (slave 2) outputs the position latched at
T1 at pin SLO.
The absolute position data (D0-D7) is binary coded.
The position data and the error bit (NERR) are CRC
protected. The CRC polynomial is X4 +X+1 = 0x13.
//CRC start value,
//Parameter CRCID D(45:42)
//CRC Polynoma
CRC_Poly = 0x13;
Sens_Data = D + NERR; //Protected Sensor Data 9bit
CRC_Value = CRCID;
for (i=0; i<8; i++)
{
if ((CRC_Value & 0x100) != (Sens_Data & 0x100))
CRC_Value = (CRC_Value << 1) ^ CRC_Poly;
else
CRC_Value = (CRC_Value << 1);
Sens_Data = Sens_Data << 1;
}
Figure 7: Example CRC calculation
Fast Scanning Mode
PSMI
tout
MA
SLO
ACK START
D7
CRC0
STOP
Figure 8: Timing in Fast Scanning Mode
PSMI
t > 50µs
Slow Scanning Mode
tout
MA
SLO
ACK
START
D7
t £ tON()2
Figure 9: Timing in Slow Scanning Mode
CRC0
STOP
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 11/22
OPERATING MODES
V(VDD) > VDDon
Startup
Power-On Reset
V(VZAP) < V1t()lo
V(VZAP) > V1t()hi
Enter
Normal Mode
Enter
Programming Mode
SLI=0; PSMI=0
SLI=1; PSMI=0
V(VZAP) = VDD
V(VZAP) = Vzap()
V(VZAP) = VDD
PSMI=1
PSMI=0; SLI=1
Slow Mode
(Operate)
PSMI=1
PSMI=0; SLI=0
PSMI=1
Fast Mode
(Operate)
Write RAM
Read ROM
Write ROM
tout(MA)
Slow Mode
Sleep
PSMI=1
PSMI=1
Sleep
Figure 10: Operation Modes
Figure 10 shows the different modes of iC-MP. There
are two major modes of operation:
• Normal Mode:
Readout position data and error bit. Normal mode is
subdivided into two minor modes of operation:
– Fast Scanning Mode:
iC-MP is always activated.
– Slow Scanning Mode (Power Save Mode):
iC-MP goes into Slow Mode Sleep following the
first transmission of sensor data via the serial
interface.
• Programming Mode:
iC-MP can be configured in programming mode. See
the chapter on ’PROGRAMMING MODE’ for further
details. There are three minor modes:
– Read ROM:
iC-MP’s Zener zap ROM structure is read.
– Write RAM:
iC-MP’s internal registers can be temporarily
programmed for test purposes.
– Write ROM:
iC-MP’s zapping structure is programmed.
A Power-On Reset is required after a Read ROM and
Write ROM instruction. Each state is quit by a PowerOn Reset.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 12/22
PROGRAMMING MODE
When pulling the VZAP pin to high during startup,
the programming mode is entered (see ’OPERATING
MODES’). In this mode there are three different categories of operation:
• Write ROM Mode (V(VZAP) = Vzap (), according to
ELEC.CHAR., no. 507):
In Write ROM Mode each Zener zap diode is burned
(= zapped) immediately on the rising edge of MA.
See Figure 13 for details. For the conditions of operation of Write ROM Mode, see ELEC.CHAR., ’Zapping Input VZAP’.
PSMI
VZAP=Vtl()hi
• Write RAM Mode (V(VZAP) = VDD):
In Write RAM Mode the iC-MP reacts as in Write
ROM Mode but there is no zapping of the Zener zap
diodes. This mode can be used to temporarily program iC-MP (non-permanent) for test purpose.
• Read ROM (V(VZAP) = VDD):
In Read ROM Mode the content of the Zener zap
diodes is read out. A Read ROM operation overwrites iC-MP’s RAM content.
tpr > 1
fclk()
th > 0ms
t > 50µs
tpr
th
VDD
tpr
MA
START
SLI
D0
X
NERR
D1
X
D50
D51
X
X
Figure 11: Serial timing of Read ROM Mode
PSMI
VZAP=Vtl()hi
VDD
t > 40µs
tpr > 1
fclk()
th > 0ms
t > 50µs
tpr
t > 40µs
th
tpr
MA
SLI
NERR
START
X
D0
X
X
D1
D50
X
X
D51
X
Figure 12: Serial timing of Write RAM Mode
X
X
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 13/22
th > 0ms
t > 50µs
PSMI
VZAP=Vt()zap
tzap()
th
VDD
tzap()
MA
D0
START
SLI
X
X
NERR
X
D1
D50
X
X
D51
X
X
X
Figure 13: Serial timing of Write ROM Mode
Figure 13 shows the serial timing of a Write ROM operation (burning the Zener zap diodes). The bit stream
is described in Table 4. Each Zener zap diode can be
programmed once with a logic of ’1’. The default value
of the Zener zap diodes is a logic ’0’ (with the exception of ZTEST(1:0)). The resulting parameter (OFFSET, MODE and ENERR) are generated by an xor operation of the three sets of bits (see Figure 15).
Zapping Diodes
OFFSET1
OFFSET2
=1
OFFSET
=1
MODE
=1
ENERR
OFFSET3
MODE2
VDD
+5 V
+7 V
VZAP
100nF
+ 10µF
Programming
Board
MODE3
MA
SLI
Serial
Interface
NERR
PSMI
GND
RAM
MODE1
100nF
iC-MP
ROM
0V
ENERR1
ENERR2
ENERR3
Figure 14: In-circuit programming
A 100 nF ceramic block capacitor must be placed on
the board directly between iC-MP’s VZAP and GND
pins. A 10 µF capacitor must also be present at the
end of the programming line as close to the connector as possible (see Figure 14). During programming,
up to 90 mA flow from pin VZAP to pin GND, making
it necessary to ensure proper PCB layout to minimize
voltage drops.
CRCID
ZTEST
CRCID
ZTEST
TEST
Figure 15: ROM construction
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 14/22
D(51:0)
Parameter
Description
7:0
11:8
OFFSET1(7:0)
MODE1(3:0)
Offset of the first set
Mode of the first set,
see Table 5 and 6
13:12
ENERR1(1:0)
Error mask of the first
set, see Table 8
21:14
25:22
OFFSET2(7:0)
MODE2(3:0)
Offset of the second set
Mode of the second set,
see Table 5 and 6
27:26
ENERR2(1:0)
Error mask of the
second set, see Table 8
35:28
39:36
OFFSET3(7:0)
MODE3(3:0)
Offset of the third set
Mode of the third set,
see Table 5 and 6
41:40
ENERR3(1:0)
45:42
47:46
51:48
D(13:12)
D(27:26)
D(41:40)
Error
Error mask of the third
set, see table 8
00
01
10
11
No Error
Loss of Magnet*
Excessive Frequency Alarm
Excessive Frequency Alarm or Loss of Magnet*
CRCID(3:0)
CRC ID
*) see ’DESIGN REVIEW’
ZTEST(1:0)
Zener zap diodes, for
iC-Haus test purposes
only
See ’TEST MODES’
Table 4: Programming Datastream
MODE1(1:0)
MODE2(1:0)
MODE3(1:0)
D(9:8)
D(23:22)
D(37:36)
Code
Full Scale Angle
00
01
360°
270°
10
11
180°
90°
Table 5: Linear Analog Output - Mode Bit 1:0
MODE1(2)
MODE2(2)
MODE3(2)
D(10)
D(24)
D(38)
Code
Rotation
0
CW*
1
CCW*
*) CW = clockwise, CCW = counter-clockwise
Table 6: Mode Bit 2
MODE3(3)
ENERR1(1:0)
ENERR2(1:0)
ENERR3(1:0)
Code
TEST(3:0)
MODE1(3)
MODE2(3)
ENERR
The parameter ENERR indicates two kind of errors. If
the magnetic field strength is at low a ’Loss of Magnet’ is generated. An ’Excessive Frequency Alarm’ is
generated when the revolution per minute is to high.
Parameter ENERR handles the various error types.
D(11)
D(25)
D(39)
Code
Range
0
1
(0 % - 100 %) * VDD
(10 % - 90 %) * VDD
Table 7: Linear Analog Output - Mode Bit 3
Table 8: Error masks
Calculating the position offset
Before iC-MP outputs the actual position via the serial
interface or the linear analog output (LAO), an offset is
added internally. This offset consists of the following
parameters:
OFFSET = OFFSET1 xor OFFSET2 xor OFFSET3
The offset is programmed in several stages (see Figure 16). It is important that the direction of rotation is
programmed prior to this (MODE Bit 2). To determine
the actual configured offset, all three offset parameters
must be read out. After these parameters have been
xored the actual offset is determined:
Actual Offset = OFFSET1 xor OFFSET2 xor OFFSET3
To calculate the new offset the actual position at the
required offset is required. The formula used to calculate this new offset is as follows:
New Offset = 256 - Actual Position + Actual Offset
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 15/22
Start
Set: MODEx (bit 2)
finally
OFFSET1
Read out: OFFSET2
OFFSET3
Read out
actual position
Calculate actual
position offset
Calculate new
position offset
OFFSET1
Set param: OFFSET2
OFFSET3
End
Figure 16: Principle of offset calculation
CRCID
The CRCID parameter contains the CRC start value.
Configuring the CRC starting value enables a data
value to be clearly assigned to a slave, as the CRC
check fails with a faulty configuration of the master or
an exchange sequence. For example, the controller
assigns a start value for each slave and writes these
to the CRCID slave parameter.
For CRC calculation, see ’SERIAL OUTPUT (SLO)’.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 16/22
FAST SCANNING MODE
VZAP
PSMI
FAST SCANNING
MP0
VDD
VZAP
MP0
Hall Angle Encoder
XFS3
SLI
R1
2.2k
VZAP
MP0
B
MA
SLAVE 3
GND
SLI
SLO
B
SLAVE 2
LAO
PSMI
PSMO
MA
NERR
VZAP
XFS1
PSMI
PSMO
VDD
Hall Angle Encoder
XFS2
PSMI
SLI
VDD
Hall Angle Encoder
GND
SLI
SLO
PSMO
B
MA
NERR
SLAVE 1
LAO
GND
SLO
NERR
LAO
MA
NERR
LAO(2:0)
0
1
LAO(2:0)
2
SLO
Figure 17: Fast Scanning Mode
In Fast Scanning Mode all devices are active at the
same time. With a start condition at MA the absolute position of all devices is latched and all absolute
positions are transferred as one long data word (see
page 17). Parameter CRCID can be used for improved
differentiation of the individual data words. See ’PROGRAMMING MODE’.
T1
NERR
SLI
MA
VDD
VZAP=Vt()zap
PSMI
NERR
SLI
MA
VDD
VZAP=Vtl()hi
PSMI
NERR
SLI
MA
VDD
VZAP=Vtl()hi
PSMI
SLO
MA
t > 50µs
th
t > 50µs
th
t > 50µs
th
T3
X
START
tzap()
X
START
tpr
X
START
tpr
ACK START
T2
D50
D50
X
D1
X
D0
X
X
X
X
Slave 1
D50
D1
Slave 1
D1
X
X
X
X
D51
X
D51
D51
NERR CRC3
X
X
X
D0
Slave 1
D1
D0
D0
D7
Slave 1
X
X
X
X
X
X
CRC0
X
D0
X
D0
D0
NERR CRC3
D1
D50
Slave 2
X
D50
X
D1
X
X
X
D50
X
D1
X
Slave 2
X
Write RAM Mode
X
Slave 2
Read ROM Mode
X
D0
X
D51
X
D51
D51
Read Position Data
D1
Write ROM Mode (Zapping)
D7
Slave 2
X
X
X
CRC0
D7
X
X
X
X
D0
X
D0
D0
D1
X
X
X
NERR CRC3
X
X
X
X
X
X
X
th > 0ms
D50
D1
Slave 3
D50
D1
Slave 3
D50
Slave 3
D1
D0
Slave 3
fclk()
1
X
X
X
STOP
tpr >
X
D51
X
D51
D51
CRC0
tout
tpr
tpr
tzap()
t > 40µs
t > 40µs
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 17/22
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 18/22
SLOW SCANNING MODE
VZAP
PSMI
SLOW SCANNING
MP0
VDD
VZAP
Hall Angle Encoder
XSS3
R1
2.2k
SLI
VDD
VZAP
PSMO
B
MA
SLAVE 3
GND
SLO
NERR
PSMO
B
MA
SLAVE 2
LAO
VDD
VZAP
XSS1
PSMI
SLI
MP0
Hall Angle Encoder
XSS2
PSMI
SLI
MP0
Hall Angle Encoder
GND
SLO
NERR
LAO
PSMI
SLI
PSMO
B
MA
SLAVE 1
GND
SLO
NERR
LAO
MA
NERR
LAO
SLO
Figure 18: Slow Scanning Mode
In Slow Scanning Mode only one device is activated in
a chain. This device transmits its absolute position on
the SLO bus and the analog output voltage to the LAO
bus. After an timeout at SLI, the next device is enabled
(PSMO hi → lo). The devices needs some time after
activation to find the actual position.
Parameter CRCID can be used for improved differen-
tiation of the individual data words. See ’PROGRAMMING MODE’.
The chain is reset by a logic high at the PSMI pin (see
page 19).
Application hints:
See ’DESIGN REWIEW’.
NERR
SLI
MA
VDD
VZAP=Vt()zap
PSMI
NERR
SLI
MA
VDD
VZAP=Vtl()hi
PSMI
NERR
SLI
MA
VDD
VZAP=Vtl()hi
PSMI
SLO
MA
th
t > 50µs
th
t > 50µs
th
t > 50µs
T1
X
START
tzap()
X
START
tpr
X
START
tpr
T3
D50
X
D0
X
X
X
X
D50
X
D1
X
Slave 3
D50
Slave 3
D1
Slave 3
CRC0
D1
X
X
D7
Slave 3
D0
D0
ACK START
T2
X
X
X
STOP
tout
X
D51
X
D51
D51
ton()2
X
X
X
T1
t > 50µs
t > 50µs
t > 50µs
T3
X
X
X
START
ACK START
T2
STOP
D1
D50
X
X
X
X
X
D50
X
D1
X
Slave 2
X
Write RAM Mode
X
D50
D1
Slave 2
Read ROM Mode
X
Slave 2
X
D51
X
D51
D51
ton()2
Write ROM Mode (Zapping)
X
D0
X
D0
D0
CRC0
tout
Read Position Data
D7
Slave 2
T1
X
X
X
T3
t > 50µs
t > 50µs
t > 50µs
X
X
X
START
ACK START
T2
X
D0
X
D0
D0
X
X
X
D7
CRC0
STOP
tout
D50
X
X
X
X
X
X
X
th > 0ms
D50
D1
Slave 1
D50
D1
Slave 1
D1
Slave 1
Slave 1
tpr >
X
D51
X
D51
D51
fclk()
1
X
X
X
tpr
tpr
tzap()
t > 40µs
t > 40µs
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 19/22
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 20/22
APPLICATION CIRCUITS
Stand-alone example
VDD
PSMI
iC-MP
GND
PSMO
NERR
VDD
B
LAO
VZAP
SLI
MA
SLO
Hall Angle Encoder
Linear
Analog Output
Figure 19: Circuit for stand-alone operation
1µF
Figure 19 shows an example circuit for stand-alone operation of iC-MP. The device is in Fast Scanning Mode.
If the device is also to be programmed, pins PSMI, SLI
and VZAP should be connected to GND by a pull-down
resistor (e.g. 2.2 kΩ).
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 21/22
TEST MODES
iC-MP has several test settings which make internal
reference quantities and the amplified, differential Hall
voltages of the sensor pairs accessible at external pins
for measurement purposes. This signals enables a
chip/package to be adjusted in relation to the magnet.
Op. Mode
Normal
Test 0
Test 1
Test 2
Notes
TEST(3:0)
0ddd
1000
1001
1010
d = don’t care
Pin NERR
analog
PSIN
NSIN
GAIN
digital
NERR
-
Test modes can be triggered by programming the parameter TEST (D(51:48)). The individual test modes
are listed in the following table.
See ’ELECTRICAL CHARACTERISTICS’.
Pin LAO
Pin PSMO
LAO
PCOS
NCOS
VREF
PSMO
PSMO
PSMO
PSMO
Comments
Table 9: Test modes
DESIGN REVIEW: Notes On Chip Functions
iC-MP Y
No.
1
Function, Parameter/Code
Description and Application Notes
Slow Scanning Mode
(without a magnet):
Serial Interface Mode is discontinued without a magnet
- The start bit is not available
- The daisy chain is stopped
Table 10: Notes on chip functions regarding iC-MP chip releas Y
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relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions
in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of
merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MP 8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 22/22
ORDERING INFORMATION
Type
Package
Order Designation
iC-MP
Evaluation Board
DFN10
iC-MP DFN10
iC-MP EVAL MP1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
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