ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-111 is a general purpose, dual output Differential-to-3.3V LVPECL High Frequency HiPerClockS™ Synthesizer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS. The ICS8432-111 has a selectable differential CLK, nCLK pair or LVCMOS/LVTTL TEST_CLK. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The CLK, nCLK pair can accept most standard differential input levels.The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. Output frequencies up to 700MHz for FOUT and 350MHz for FOUT/2 can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics and the multiple frequency outputs of the ICS8432-111 makes it an ideal clock source for Fibre Channel 1 and 2, and Infiniband applications. • Dual differential 3.3V LVPECL outputs ICS • Selectable differential CLK, nCLK pair or LVCMOS TEST_CLK • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • TEST_CLK can accept the following input types: LVCMOS or LVTTL • Maximum FOUT frequency: 700MHz Maximum FOUT/2 frequency: 350MHz • CLK, nCLK or TEST_CLK input frequency: 40MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and VCO frequency multiplier and dividers • RMS period jitter: 5ps (maximum) • Cycle-to-cycle jitter: 40ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT PHASE DETECTOR MR VCO ÷M 0 1 ÷1 ÷2 ÷4 ÷8 24 CLK M6 2 23 TEST_CLK M7 3 22 CLK_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR ICS8432-111 9 10 11 12 13 14 15 16 VEE nFOUT FOUT VCCO nFOUT/2 TEST FOUT/2 CONFIGURATION INTERFACE LOGIC 1 VCC ÷2 M5 TEST FOUT nFOUT FOUT/2 nFOUT/2 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 8432CY-111 nCLK 32 31 30 29 28 27 26 25 PLL S_LOAD S_DATA S_CLOCK nP_LOAD nP_LOAD 1 M0 CLK nCLK M1 0 M2 TEST_CLK M3 M4 CLK_SEL VCO_SEL VCO_SEL www.icst.com/products/hiperclocks.html 1 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION rial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fIN x M NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8432-111 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the ICS8432-111. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. When the input clock is at 25MHz, the valid M values for which the PLL will achieve lock are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: fOUT = fVCO = fIN x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-111 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a se- T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout/2 SERIAL LOADING S_CLOCK T1 S_DATA T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S_LOAD nP_LOAD PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: 8432CY-111 The NULL timing slot must be observed. www.icst.com/products/hiperclocks.html 2 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 2, 3, 4, 28, 29, 30, 31, 32 M5 M6, M7, M8, M0, M1, M2, M3, M4 Input Type Description Input M counter/divider inputs. Data latched on LOW-to-HIGH transistion Pulldown of nP_LOAD input. LVCMOS/LVTTL interface levels. 5, 6 N0, N1 Input Pulldown Pullup Determines output divider value as defined in Table 3C Function Table. LVCMOS/LVTTL interface levels. No connect. 7 nc Unused 8, 16 VEE Power 9 TEST Output 10 11, 12 13 VCC FOUT/2, nFOUT/2 VCCO Power Output 14, 15 FOUT, nFOUT Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power 22 CLK_SEL Input Pullup 23 TEST_CLK Input Pulldown Pulldown Non-inver ting differential clock input. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Half frequency differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Power 24 CLK Input 25 nCLK Input 26 nP_LOAD Input 27 VCO_SEL Input Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers are the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin. Selects between differential clock input or test input as the PLL reference source. LVCMOS/LVTTL interface levels. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS/LVTTL interface levels. Pullup Inver ting differential clock input. Parallel load input. Determines when data present at M8:M0 is loaded Pulldown into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8432CY-111 www.icst.com/products/hiperclocks.html 3 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X L H X X H ↑ Data Parallel or serial input do not affect shift registers. S_DATA passed directly to ripple counter as it is clocked. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 1 0 1 0 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • • • • • • • • • • 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 VCO Frequency (MHz) M Count 250 10 275 • • 700 28 0 0 0 0 1 1 1 0 0 NOTE 1: These M count values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of 25MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Output Frequency (MHz) Inputs N Divider Value N1 N0 FOUT Minimum Maximum Minimum FOUT/2 Maximum 0 0 1 250 700 125 350 0 1 2 125 350 62.5 175 1 0 4 62.5 175 31.25 87.5 1 1 8 31.25 87.5 15.625 43.75 8432CY-111 www.icst.com/products/hiperclocks.html 4 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCO Output Supply Voltage 3.465 V I EE Power Supply Current 140 mA ICCA Analog Supply Current 15 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Test Conditions Minimum Typical VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, MR 2 VCC + 0.3 V TEST_CLK 2 VCC + 0.3 V -0.3 0.8 V 1.3 V VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, MR TEST_CLK IIH IIL Input High Current Input Low Current M0-M4, M6-M8, N0, N1, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, MR VCC = VIN = 3.465V 150 µA M5, CLK_SEL, VCO_SEL VCC = VIN = 3.465V 5 µA M0-M4, M6-M8, N0, N1, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, MR VCC = 3.465V, VIN = 0V -5 µA M5, CLK_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2.6 V VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Information, 3.3V Output Load Test Circuit. 8432CY-111 www.icst.com/products/hiperclocks.html 5 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions CLK Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA 5 µA nCLK VCC = VIN = 3.465V CLK VCC = 3.465V, VIN = 0V -5 µA nCLK VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. 1.3 V VCC - 0.85 V TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 1.0 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C Symbol Parameter fIN Input Frequency Test Conditions TO 70°C Minimum Typical TEST_CLK; NOTE 1 10 40 MHz CLK, nCLK; NOTE 1 10 40 MHz S_CLOCK 50 MHz NOTE 1: For the input frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 ≤ M ≤ 70. Using the maximum frequency of 40MHz, valid values of M are 7 ≤ M ≤ 17. 8432CY-111 www.icst.com/products/hiperclocks.html 6 REV. B MARCH 3, 2004 Integrated Circuit Systems, Inc. ICS8432-111 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions FOUT Output Frequency F OUT/ 2 Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tjit(per) Period Jitter, RMS; NOTE 2 tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time tS Setup Time tH Hold Time Minimum Typical Maximum Units 31.25 700 MHz 15.625 350 MHz 40 ps 5 ps 60 ps 700 ps fOUT > 100 20% to 80% 200 M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns 47 53 % tPeriod/2 - 150 tPeriod/2 + 150 odc Output Duty Cycle tPW Output Pulse Width fOUT/2; fOUT, N > 1 PLL Lock Time tLOCK NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 8432CY-111 www.icst.com/products/hiperclocks.html 7 1 ps ms REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V V CC , VCCA, VCCO Qx VCC SCOPE nCLK LVPECL V V Cross Points PP nQx VEE CMR CLK -1.3V ± 0.165V VEE DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT nFOUT nFOUT, nFOUT/2 FOUT, FOUT/2 ➤ nFOUT/2 tcycle n ➤ FOUT ➤ tcycle n+1 ➤ FOUT/2 t jit(cc) = tcycle n –tcycle n+1 t sk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER VOH 80% 80% VREF VSW I N G Clock Outputs VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements 20% 20% tR tF Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) PERIOD JITTER OUTPUT RISE/FALL TIME nFOUT, nFOUT/2 FOUT, FOUT/2 Pulse Width t odc = PERIOD t PW t PERIOD OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD 8432CY-111 www.icst.com/products/hiperclocks.html 8 REV. B MARCH 3, 2004 Integrated Circuit Systems, Inc. ICS8432-111 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-111 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. Vcc, VccA, and VccO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VccA pin. 3.3V V cc .01µF 10Ω V ccA .01µF 10µF FIGURE 2. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8432CY-111 www.icst.com/products/hiperclocks.html 9 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. TERMINATION FOR 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 8432CY-111 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 5E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8432CY-111 BY www.icst.com/products/hiperclocks.html 11 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8432-111. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8432-111 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 60.4mW = 545.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.546W * 42.1°C/W = 93°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8432CY-111 www.icst.com/products/hiperclocks.html 12 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V – (V OH_MAX Pd_L = [(V OL_MAX • CCO_MAX – (V CCO_MAX - 2V))/R ] * (V OL_MAX =V =V CCO_MAX ) ) – 1.0V CCO_MAX OH_MAX OL_MAX CCO_MAX OH_MAX = 3.465, this results in V For logic low, VOUT = V Using V -V -V CCO_MAX L OH_MAX CCO_MAX CCO_MAX L For logic high, VOUT = V Using V • - 2V))/R ] * (V = 2.465V – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H =[(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L =[(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8432CY-111 www.icst.com/products/hiperclocks.html 13 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8432-111 is: 3765 8432CY-111 www.icst.com/products/hiperclocks.html 14 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8432CY-111 www.icst.com/products/hiperclocks.html 15 REV. B MARCH 3, 2004 ICS8432-111 Integrated Circuit Systems, Inc. 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8432CY-111 ICS8432CY111 32 Lead LQFP 250 per tray 0°C to 70°C ICS8432CY-111T ICS8432CY111 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432CY-111 www.icst.com/products/hiperclocks.html 16 REV. B MARCH 3, 2004 Integrated Circuit Systems, Inc. ICS8432-111 700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev B 8432CY-111 Table T4A Page 5 12 Description of Change Power Supply table - adjusted the IEE limit from 120mA max. to 140mA max. Adjusted Power Dissipation to comply with IEE. www.icst.com/products/hiperclocks.html 17 Date 3/3/04 REV. B MARCH 3, 2004