Integrated Circuit Systems, Inc. ICS8516 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP GENERAL DESCRIPTION FEATURES The ICS8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS. The ICS8516 CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516 provides a low power, low noise, pointto-point solution for distributing clock signals over controlled impedances of 100Ω. • Sixteen differential LVDS outputs Dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode. • Multiple output enable inputs for disabling unused outputs in reduced fanout applications Guaranteed output and part-to-part skew specifications make the ICS8516 ideal for those applications demanding well defined performance and repeatability. • LVDS compatible ICS • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLK input • Output skew: 90ps (maximum) • Part-to-part skew: 500ps (maximum) • Propagation delay: 2.4ns (maximum) • Additive phase jitter, RMS: 148fs (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q9 nQ9 Q8 nQ8 GND OE2 OE1 GND nQ7 Q7 nQ6 Q6 CLK nCLK Q15 nQ15 Q1 nQ1 Q14 nQ14 Q2 nQ2 Q13 nQ13 Q3 nQ3 Q12 nQ12 Q4 nQ4 Q11 nQ11 Q5 nQ5 Q10 nQ10 Q6 nQ6 Q9 nQ9 Q7 nQ7 Q8 nQ8 VDD nQ5 Q5 nQ4 Q4 VDD GND nQ3 Q3 nQ2 Q2 VDD 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8516 VDD nQ10 Q10 nQ11 Q11 VDD GND nQ12 Q12 nQ13 Q13 VDD nQ14 Q14 nQ15 Q15 GND CLK nCLK GND Q0 nQ0 Q1 nQ1 Q0 nQ0 48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View OE1 OE2 8516FY www.icst.com/products/hiperclocks.html 1 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 1. PIN DESCRIPTIONS Number 1, 6, 12, 25, 31, 36 2, 3 Name Type Description VDD Power Positive supply pins. nQ5, Q5 Output Differential output pair. LVDS interface levels. 4, 5 7, 17, 20, 30, 41, 44 8, 9 nQ4, Q4 Output Differential output pair. LVDS interface levels. GND Power Power supply ground. nQ3, Q3 Output Differential output pair. LVDS interface levels. 10, 11 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. 18 nCLK Input Pullup 19 CLK Input Pulldown 21, 22 Q15, nQ15 Output 23, 24 Q14, nQ14 Output Differential output pair. LVDS interface levels. 26, 27 Q13, nQ13 Output Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Differential output pair. LVDS interface levels. 28, 29 Q12, nQ12 Output Differential output pair. LVDS interface levels. 32, 33 Q11, nQ11 Output Differential output pair. LVDS interface levels. 34, 35 Q10, nQ10 Output Differential output pair. LVDS interface levels. 37, 38 Q9, nQ9 Output Differential output pair. LVDS interface levels. 39, 40 Q8, nQ8 Output Differential output pair. LVDS interface levels. Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15; OE1 controls outputs Q0, nQ0 thru Q7, nQ7. 42, 43 OE2, OE1 Input Pullup LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. 45, 46 nQ7, Q7 Output 47, 48 nQ6, Q6 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 8516FY www.icst.com/products/hiperclocks.html 2 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) 51 kΩ 4 pF CPD Test Conditions Minimum Typical Maximum Units TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs OE1 Outputs OE2 Q0:Q7 nQ0:nQ7 Q8:Q15 nQ8:nQ15 0 0 Hi Z Hi Z Hi Z Hi Z 1 0 ACTIVE ACTIVE Hi Z Hi Z 0 1 Hi Z Hi Z ACTIVE ACTIVE 1 1 ACTIVE ACTIVE ACTIVE ACTIVE In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B. TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK 0 nCLK 1 Q0:Q15 LOW Outputs nQ0:nQ15 HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8516FY www.icst.com/products/hiperclocks.html 3 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Static Power Supply Current Minimum Typical Maximum Units 3.135 3. 3 3.465 V RL = 100Ω 135 16 5 mA No Load 60 75 mA Typical Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage OE1, OE2 2 VDD + 0.3 V VIL Input Low Voltage OE1, OE2 -0.3 0.8 V IIH Input High Current OE1, OE2 VDD = VIN = 3.465V 5 µA IIL Input Low Current OE1, OE2 VDD = 3.465V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units CLK VIN = VDD = 3.465V 150 µA nCLK VIN = VDD = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 nCLK VDD = 3.465V, VIN = 0V -150 VPP Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined ast VIH. 8516FY Maximum www.icst.com/products/hiperclocks.html 4 µA µA 1.3 V VDD - 0.85 V REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum 250 400 600 mV 50 mV 1.125 1.4 Units 1.6 V 50 mV -10 +10 µA -1 +1 µA IOZ High Impedance Leakage Current IOFF Power Off Leakage IOSD Differential Output Shor t Circuit Current -5.5 mA IOS/IOSB Output Shor t Circuit Current -12 mA Maximum Units 700 MH z TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time t jit tR/tF Minimum 1.6 Integration Range: 12kHz - 20MHz 20% to 80% Typical 2.0 2. 4 ns 90 ps 500 ps 148 100 45 fs 55 0 50 ps odc Output Duty Cycle 55 % tPZL, tPZH Output Enable Time; NOTE 5 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 5 ns NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. 8516FY www.icst.com/products/hiperclocks.html 5 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ADDITIVE PHASE JITTER ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a -50 Additive Phase Jitter @ 155.52MHz -60 (12kHz to 20MHz) = 148fs typical -70 SSB PHASE NOISE dBc/HZ -80 -90 -100 -100 -120 -130 -140 -150 -160 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated 8516FY www.icst.com/products/hiperclocks.html 6 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP PARAMETER MEASUREMENT INFORMATION VDD 3.3V ± 5% SCOPE nCLK Qx Power Supply + Float GND V LVDS - V Cross Points PP CMR CLK nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 nQx nQ Qx nQy PART 2 nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK 80% 80% VOD CLK Clock Outputs nQ0:nQ15 20% 20% tR tF Q0:Q15 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY 8516FY www.icst.com/products/hiperclocks.html 7 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP VDD nQ0:nQ15 out Q0:Q15 t odc = DC Input LVDS ➤ t PW PERIOD t PW ➤ out VOS/Δ VOS x 100% t PERIOD ➤ OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OFFSET VOLTAGE SETUP VDD VDD out ➤ out ➤ LVDS 100 VOD/Δ VOD out DC Input ➤ LVDS IOSD ➤ DC Input out DIFFERENTIAL OUTPUT SHORT DIFFERENTIAL OUTPUT VOLTAGE SETUP CIRCUIT CURRENT SETUP VDD ➤ out DC Input IOS LVDS LVDS ➤ ➤ IOSB out IOFF OUTPUT SHORT CIRCUIT CURRENT SETUP 8516FY VDD POWER OFF LEAKAGE SETUP www.icst.com/products/hiperclocks.html 8 REV. B FEBRUARY 21, 2006 Integrated Circuit Systems, Inc. ICS8516 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 8516FY LVDS – Like OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. www.icst.com/products/hiperclocks.html 9 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 8516FY www.icst.com/products/hiperclocks.html 10 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V Zo = 50 Ohm LVDS_Driver CLK R1 100 nCLK HiPerClockS Zo = 50 Ohm FIGURE 3. TYPICAL LVDS DRIVER TERMINATION SCHEMATIC EXAMPLE Figure 4 shows a schematic example of ICS8516. In this example, the input is driven by an LVDS driver. For LVDS buffer, it is recommended to terminate the unused outputs for better signal integrity. The decoupling capacitors should be physically located near the power pin. Zo = 50 Ohm + R16 100 VDD=3.3V - Zo = 50 Ohm LVDS_input VDD Q2 nQ2 Q3 nQ3 GND VDD Q4 nQ4 Q5 nQ5 VDD 12 11 10 9 8 7 6 5 4 3 2 1 U1 8516 13 14 15 16 17 18 19 20 21 22 23 24 LVDS_Driver Zo = 50 Ohm R17 100 Zo = 50 Ohm Q6 nQ6 Q7 nQ7 GND OE1 OE2 GND nQ8 Q8 nQ9 Q9 48 47 46 45 44 43 42 41 40 39 38 37 + R10 100 - Zo = 50 Ohm LVDS_input 25 26 27 28 29 30 31 32 33 34 35 36 VDD Q13 nQ13 Q12 nQ12 GND VDD Q11 nQ11 Q10 nQ10 VDD Zo = 50 Ohm nQ1 Q1 nQ0 Q0 GND nCLK CLK GND Q15 nQ15 Q14 nQ14 Zo = 50 Ohm + R1 100 - Zo = 50 Ohm LVDS_input (U1-1) VDD=3.3V C1 0.1u (U1-6) C2 0.1u (U1-12) (U1-25) C3 0.1u (U1-31) C4 0.1u (U1-36) C5 0.1u C6 0.1u Decoupling capacitors located near the power pins FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE 8516FY www.icst.com/products/hiperclocks.html 11 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 67.8°C/W 47.9°C/W Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8516 is: 1821 8516FY www.icst.com/products/hiperclocks.html 12 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FOR 48 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL 48 N 8516FY MAXIMUM A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html 13 REV. B FEBRUARY 21, 2006 ICS8516 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8516FY ICS8516FY 48 Lead LQFP tray 0°C to 70°C ICS8516FYT ICS8516FY 48 Lead LQFP 1000 tape & reel 0°C to 70°C ICS8516FYLF ICS8516FYLF 48 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS8516FYLFT ICS8516FYLF 48 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8516FY www.icst.com/products/hiperclocks.html 14 REV. B FEBRUARY 21, 2006 Integrated Circuit Systems, Inc. ICS8516 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP REVISION HISTORY SHEET Rev A A Table T1 T1 T2 A T8 B 8516FY T5 Page 2 8 2 3 9 12 1 5 6 9 Description of Change Pin Description table - added pins 47 thru 48. Added LVDS Driver Termination in the Application Information section. Pin Description Table - switched pin names for 45, 46 & 47,48 Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Updated Differential Clock Input Interface section. Ordering Information Table - added Lead-Free par t numbers. Feature Section - added Additive Phase Jitter bullet. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter section. Added Recommendations for Unused Input and Output Pins www.icst.com/products/hiperclocks.html 15 Date 3/31/03 5/6/03 7/30/04 2/21/06 REV. B FEBRUARY 21, 2006