TPS54628 www.ti.com SLVSBW5 – APRIL 2013 4.5V to 18V Input, 6-A Synchronous Step-Down Converter with Eco-mode™ Check for Samples: TPS54628 FEATURES DESCRIPTION • The TPS54628 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54628 enables system designers to complete the suite of various end-equipment power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54628 uses the D-CAP2™ mode control that provides a fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and Eco-mode™ operation at light loads. Eco-mode™ allows the TPS54628 to maintain high efficiency during lighter load conditions. The TPS54628 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable soft start time. The TPS54628 is available in the 8-pin DDA package, and designed to operate from –40°C to 85°C. 1 23 • • • • • • • • • • • D-CAP2™ Mode Enables Fast Transient Response Low Output Ripple and Allows Ceramic Output Capacitor Wide VIN Input Voltage Range: 4.5 V to 18 V Output Voltage Range: 0.76 V to 5.5 V Highly Efficient Integrated FETs Optimized for Lower Duty Cycle Applications – 36 mΩ (High Side) and 28 mΩ (Low Side) High Efficiency, less than 10 μA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start Pre-Biased Soft Start 650-kHz Switching Frequency (fSW) Cycle By Cycle Over Current Limit Auto-Skip Eco-mode™ for High Efficiency at Light Load APPLICATIONS • Wide Range of Applications for Low Voltage System – Digital TV Power Supply – High Definition Blu-ray Disc™ Players – Networking Home Terminal – Digital Set Top Box (STB) Vout( 50mV/div) TPS54628 Iout( 2A/div) 100us/div 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2, Eco-mode are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS54628 SLVSBW5 – APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) (3) (3) ORDERABLE PART NUMBER TPS54628DDA DDA TRANSPORT MEDIA PIN Tube 8 TPS54628DDAR Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. All package options have Cu NIPDAU lead/ball finish. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range Output voltage range MAX VIN, EN –0.3 20 VBST –0.3 26 VBST (10 ns transient) –0.3 28 VBST (vs SW) –0.3 6.5 VFB, SS –0.3 6.5 SW –2 20 SW (10 ns transient) –3 22 VREG5 –0.3 6.5 GND –0.3 0.3 –0.2 0.2 V 2 kV 500 V Voltage from GND to thermal pad, Vdiff Electrostatic discharge Human Body Model (HBM) Charged Device Model (CDM) Operating junction temperature, TJ –40 150 Storage temperature, Tstg –55 150 (1) UNIT MIN V V °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) TPS54628 DDA (8 PINS) θJA Junction-to-ambient thermal resistance 43.5 θJCtop Junction-to-case (top) thermal resistance 49.4 θJB Junction-to-board thermal resistance 25.6 ψJT Junction-to-top characterization parameter 7.4 ψJB Junction-to-board characterization parameter 25.5 θJCbot Junction-to-case (bottom) thermal resistance 5.2 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range, (unless otherwise noted) VIN Supply input voltage range VI Input voltage range MIN MAX 4.5 18 VBST –0.1 24 VBST (10 ns transient) –0.1 27 VBST(vs SW) –0.1 6.0 SS –0.1 5.7 EN –0.1 18 VFB –0.1 5.5 SW –1.8 18 SW (10 ns transient) UNIT V V –3 21 GND –0.1 0.1 –0.1 5.7 0 5 mA VO Output voltage range VREG5 IO Output Current range IVREG5 V TA Operating free-air temperature –40 85 °C TJ Operating junction temperature –40 150 °C ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IVIN Operating - non-switching supply current VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V 950 1400 μA IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 3 10 μA LOGIC THRESHOLD VEN REN EN high-level input voltage EN EN low-level input voltage EN EN pin resistance to GND VEN = 12 V 1.6 200 V 400 0.6 V 800 kΩ VFB VOLTAGE AND DISCHARGE RESISTANCE TA = 25°C, VO = 1.05 V, IO = 10 mA, Ecomode™ operation VFBTH IVFB VFB threshold voltage 772 mV TA = 25°C, VO = 1.05 V, continuous mode operation 757 765 773 mV TA = -40 to 85°C, VO = 1.05 V, continuous mode operation (1) 751 765 779 mV 0 ±0.15 μA 5.5 5.7 V VFB input current VFB = 0.8 V, TA = 25°C VVREG5 VREG5 output voltage TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA 5.2 IVREG5 Output current VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 20 VREG5 OUTPUT mA VOUT DISCHARGE RDISCHG 500 800 Ω VOUT discharge resistance EN = 0 V, SW = 0.5 V, TA = 25°C High side switch resistance 25°C, VBST - SW = 5.5 V 36 mΩ Low side switch resistance 25°C 28 mΩ Current limit L out = 1.5 μH (1) MOSFET RDS(on) CURRENT LIMIT IOCL (1) 6.7 7.3 8.9 A Not production tested. 3 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN TSDN Thermal shutdown threshold Shutdown temperature Hysteresis (2) 165 (2) °C 35 ON-TIME TIMER CONTROL tON On time VIN = 12 V, VO = 1.05 V 150 tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns SS charge current VSS = 1 V 4.2 6 7.8 SS discharge current VSS = 0.5 V 1.5 3.3 ns SOFT START ISS μA mA HICCUP AND OVER-VOLTAGE PROTECTION VOVP Output OVP threshold OVP Detect (L > H) VHICCUP Output Hiccup threshold Hiccup detect (H > L) 125% THICCUPDELAY Output Hiccup delay To hiccup state 250 THICCUPENDELAY Output Hiccup Enable delay Relative to soft-start time x1.7 65% µsec UVLO UVLO (2) UVLO threshold Wake up VREG5 voltage 3.45 3.75 4.05 Hysteresis VREG5 voltage 0.13 0.32 0.48 V Not production tested. 4 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 DEVICE INFORMATION DDA PACKAGE (TOP VIEW) 1 EN VIN 8 EXPOSED THERMAL PAD 2 VFB VBST 7 SW 6 GND 5 TPS54628 DDA 3 VREG5 4 SS HSOP8 PIN FUNCTIONS PIN NAME NO. DESCRIPTION EN 1 Enable input control. EN is active high and must be pulled up to enable the device. VFB 2 Converter feedback input. Connect to output voltage with feedback resistor divider. VREG5 3 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low. SS 4 Soft-start control. An external capacitor should be connected to GND. GND 5 Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. SW 6 Switch node connection between high-side NFET and low-side NFET. VBST 7 Supply input for the high-side FET gate drive circuit. Connect 0.1 µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. VIN 8 Input voltage supply pin. Exposed Thermal Pad Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. 5 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM EN EN 1 Logic VIN -35% VIN + 8 HICCUP - VREG5 Control Logic + 7 VBST OV +25% 1 shot SW VO 6 Ref + SS + PWM XCON ON VFB VREG5 Ceramic Capacitor - 2 5 + ZC - SGND SW GND PGND VREG5 3 + OCP PGND SS SS 4 Softstart SW PGND VIN HICCUP VREG5 SGND OV UVLO UVLO Protection Logic TSD REF Ref 6 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 OVERVIEW The TPS54628 is a 6-A Eco-mode™ synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS54628 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control. PWM Frequency and Adaptive On-Time Control TPS54628 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54628 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant. Auto-Skip Eco-Mode™ Control The TPS54628 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light load operation IOUT(LL) current can be calculated in Equation 1 (VIN - VOUT )×VOUT 1 × I OUT ( LL ) = 2 × L × fsw VIN (1) Soft Start and Pre-Biased Soft Start The soft start function is adjustable. When the EN pin becomes high, 6μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is 6 μA. C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1 t SS (ms) = = ISS (μA) 6 (2) The TPS54628 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. 7 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com Output Discharge Control TPS54628 discharges the output when EN is low, or the controller is turned off by the UVLO protection. The internal low-side MOSFET is not turned on for the output discharge operation to avoid the possibility of causing negative voltage at the output. Current Protection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. The TPS54628 constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the higher value. There are some important considerations for this type of over-current protection. The peak current is the average load current plus one half of the peak-to-peak inductor current. The valley current is the average load current minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the over-current threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the output voltage tends to fall. When the VFB voltage becomes lower than 65% of the target voltage, the UVP comparator detects it. If the under-voltage condition persists for 250 µs, the device will shut down and re-start in hiccup mode after 7 times the SS period. When the over current condition is removed, the output voltage will return to the regulated value. This protection is non-latching. Over Voltage Protection TPS54628 detects over and under voltage conditions by monitoring the feedback voltage (VFB). This function is enabled after approximately 1.7 x times the soft start time. When the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes high and both the high-side MOSFET driver and the low-side MOSFET driver turn off. This function is non-latch operation. UVLO Protection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54628 is shut off. This protection is non-latching. Thermal Shutdown TPS54628 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), the device is shut off. This is non-latch protection. 8 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 TYPICAL CHARACTERISTICS VIN = 12 V, TA = 25°C (unless otherwise noted). 10 Ivccsdn - Shutdown Current (µA) 1,400 ICC - Supply Current (µA) 1,200 1,000 800 600 400 200 0 9 8 7 6 5 4 3 2 1 0 ±50 0 50 100 ±50 150 TJ Junction Temperature (ƒC) 0 50 100 150 TJ Junction Temperature (ƒC) C001 Figure 1. SUPPLY CURRENT vs JUNCTION TEMPERATURE C002 Figure 2. VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1.100 50 VIN = 18 V VOUT - Output Voltage (V) EN Input Current (µA) 40 30 20 10 1.075 1.050 1.025 VVin=5V IN = 5 V VVin=12V IN = 12 V 0 VVin=18V IN = 18 V 1.000 0 5 10 15 20 EN Input Voltage (V) 0.0 2.0 3.0 4.0 5.0 IOUT - Output Current (A) C003 Figure 3. EN CURRENT vs EN VOLTAGE 1.0 6.0 C004 Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT - Output Voltage (V) 1.080 Vout( 50mV/div) 1.070 1.060 Iout( 2A/div) 1.050 1.040 1.030 IOUT = 10 mA Io=10mA Io=1A IOUT = 1 A 1.020 0 5 10 VIN - Input Voltage (V) 15 100us/div 20 C005 Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE 9 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA = 25°C (unless otherwise noted). 100 VIN = 12 V 90 Efficiency (%) EN(10V/div) VREG5(5V/div) 80 70 60 Vout(0.5V/div) Vo=1.8V 50 1ms/div Vo=3.3V Vo=5V 40 0.0 1.0 2.0 3.0 4.0 5.0 IOUT - Output Current (A) Figure 7. START-UP WAVE FORM 900 fsw - Switching Frequency (kHz) VIN = 12 V 90 80 70 Efficiency (%) C008 Figure 8. EFFICIENCY vs OUTPUT CURRENT 100 60 50 40 30 Vo=1.8V 20 Vo=3.3V 10 Vo=5V 0 0.001 IOUT = 1 A 850 800 750 700 650 Vo=1.05V V O = 1.05 V Vo=1.2V V O = 1.2 V V Vo=1.5V O = 1.5 V V Vo=1.8V O = 1.8 V V Vo=2.5V O = 2.5 V V Vo=3.3V O = 3.3 V V Vo=5V O= 5 V 600 550 500 450 400 0.01 0.1 IOUT - Output Current (A) 0 5 10 15 VIN - Input Voltage (V) C009 Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT 20 C010 Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE 0.780 900 800 0.775 700 VFB Voltage (V) fsw - Switching Frequency (kHz) 6.0 600 500 400 300 200 VVo=1.05V O = 1.05 V 100 VVo=1.8V O = 1.8 V 0.0 0.1 1.0 IO - Output Current (A) 0.765 0.760 0.755 VVo=3.3V O = 3.3 V 0 0.770 IO = 10 mA Io=10mA Io=1A IO = 1 A 0.750 10.0 ±50 Figure 11. SWITCHING FREQUENCY vs OUTPUT CURRENT 0 50 100 TJ Junction Temperature (ƒC) C011 150 C012 Figure 12. VFB VOLTAGE vs JUNCTION TEMPERATURE 10 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA = 25°C (unless otherwise noted). Vo=1.05V Vo(10mV/div) VO = 50 mV / div (-950 mV dc offset) SW = 10 V / div SW( 5V/div) 400ns/div Time = 1 µsec / div Figure 13. VOLTAGE RIPPLE AT OUTPUT (IO = 6 A) Figure 14. DCM VOLTAGE RIPPLE AT OUTPUT (IO = 30 mA) 7.00 VIN(50mV/div) 6.00 Output Current (A) Vo=1.05V SW( 5V/div) 5.00 4.00 3.00 VO=1.05V 2.00 VO=1.8V 1.00 VO=3.3V VO=5V 0.00 400ns/div -50 0 50 Ta Ambient Temperature (ºC) Figure 15. VOLTAGE RIPPLE AT INPUT (IO = 6 A) 100 C013 Figure 16. OUTPUT CURRENT vs AMBIENT TEMPERATURE 11 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com DESIGN GUIDE Step-By-Step Design Procedure To • • • • • begin the design process, the user must know a few application parameters: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple U1 TPS54628DDA Figure 17. Shows the schematic diagram for this design example. Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT. To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to noise, and the voltage errors from the VFB input current are more noticeable. æ ö R1÷ V = 0.765 x çç1 + ÷ OUT çè R2 ÷ø (3) Output Filter Selection The output filter used with the TPS54628 is an LC circuit. This LC filter has double pole at: F = P 2p L 1 OUT x COUT (4) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54628. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 1 12 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 Table 1. Recommended Component Values (1) C4 (pF) (1) Output Voltage (V) R1 (kΩ) R2 (kΩ) L1 (µH) C8 + C9 (µF) MIN TYP MAX MIN TYP MAX MIN MAX 1 6.81 22.1 5 150 220 1.0 1.5 4.7 22 68 1.05 8.25 22.1 5 150 220 1.0 1.5 4.7 22 68 1.2 12.7 22.1 5 100 1.0 1.5 4.7 22 68 1.5 21.5 22.1 5 68 1.0 1.5 4.7 22 68 1.8 30.1 22.1 5 22 1.2 1.5 4.7 22 68 2.5 49.9 22.1 5 22 1.5 2.2 4.7 22 68 3.3 73.2 22.1 2 22 1.8 2.2 4.7 22 68 5 124 22.1 2 22 2.2 3.3 4.7 22 68 Optional Since the DC gain is dependent on the output voltage, the required inductor value increases as the output voltage increases. Additional phase boost can be achieved by adding a feed forward capacitor (C4) in parallel with R1. The feed forward capacitor is most effective for output voltages at or above 1.8 V. The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for fSW. Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7. - VOUT V V OUT x IN(max) I = IPP V L x f IN(max) O SW I =I + Ipeak O = I Lo(RMS) (5) I lpp 2 I 2 O (6) + 1 2 I 12 IPP (7) For this design example, the calculated peak current is 6.51 A and the calculated RMS current is 6.01 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.6 A and an RMS current rating of 11 A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54628 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to determine the required RMS current rating for the output capacitor. I Co(RMS) = VOUT x (VIN - VOUT ) 12 x VIN x LO x fSW (8) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.284 A and each output capacitor is rated for 4A. Input Capacitor Selection The TPS54628 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage. Bootstrap Capacitor Selection A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommended to use a ceramic capacitor. 13 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 SLVSBW5 – APRIL 2013 www.ti.com VREG5 Capacitor Selection A 1-µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommended to use a ceramic capacitor. THERMAL INFORMATION This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004. The exposed thermal pad dimensions for this package are shown in the following illustration. Figure 18. Thermal Pad Dimensions 14 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 TPS54628 www.ti.com SLVSBW5 – APRIL 2013 LAYOUT CONSIDERATIONS 1. The TPS54628 can supply large load currents up to 6 A, so heat dissipation may be a concern. The top side area adjacent to the TPS54628 should be filled with ground as much as possible to dissipate heat. 2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected to the thermal pad of the device using vias as shown. The ground area should be as large as practical. Additional internal layers can be dedicated as ground planes and connected to the vias as well. 3. Keep the input switching current loop as small as possible. 4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 5. Keep analog and non-switching components away from switching components. 6. Make a single point connection from the signal ground to power ground. 7. Do not allow switching current to flow under the device. 8. Keep the pattern lines for VIN and PGND broad. 9. Exposed pad of device must be connected to PGND with solder. 10. VREG5 capacitor should be placed near the device, and connected PGND. 11. Output capacitor should be connected to a broad pattern of the PGND. 12. Voltage feedback loop should be as short as possible, and preferably with ground shield. 13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND. 14. Providing sufficient via is preferable for VIN, SW and PGND connection. 15. PCB pattern for VIN, SW, and PGND should be as broad as possible. 16. VIN Capacitor should be placed as near as possible to the device. VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQENCY BYPASS CAPACITOR TO ENABLE CONTROL FEEDBACK RESISTORS BIAS CAP EN VIN VFB VBST VREG5 SW SS GND SLOW START CAP Connection to POWER GROUND on internal or bottom layer ANALOG GROUND TRACE BOOST CAPACITOR EXPOSED THERMAL PAD AREA OUTPUT INDUCTOR VOUT OUTPUT FILTER CAPACITOR POWER GROUND VIA to Ground Plane Figure 19. PCB Layout 15 Copyright © 2013, Texas Instruments Incorporated Product Folder Links :TPS54628 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS54628DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 125 54628 TPS54628DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 125 54628 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 18-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54628DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54628DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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