TI SN75FC1000PJD

SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
D
D
D
D
1.0625 Gigabits Per Second (Gbps) Fibre
Channel Transceiver Compatible With ANSI
X3T11 (FC-PH-0)
Designed to Support X3T11 10-Bit I/F
Specification
Transmits Serial Data Up to 1.0625 Gbps
(100 Megabytes Per Second [MBps] of Data
Bandwidth)
Operates With 3.3-V Supply Voltage
D
D
D
D
D
Interfaces to Electrical Cables/Backplane or
with Optical Modules
PECL Voltage Differential Signaling Load,
1 V Typ with 50 Ω – 75 Ω
Receiver Differential Input Voltage
200 mV Minimum
64-Pin Quad Flat Pack With Thermally
Enhanced Package
5-V Tolerant I/O Terminals
description
The SN75FC1000 fibre channel transceiver provides for ultra high-speed bidirectional point-to-point data
transmission. This device supports the ANSI X3T11 Fibre Channel standard and the functional and timing
requirements of the proposed 10-bit interface specification generated by ANSI X3T11.
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RC0
SYNC
GND_TTL
RD0
RD1
RD2
VCC_TTL
RD3
RD4
RD5
RD6
VCC_TTL
RD7
RD8
RD9
GND_TTL
TC0
VCC _TX
LOOPEN
VCC _A
GND_A
REFCLK
VCC _CMOS
SYNCEN
GND_CMOS
RESERVED
LCKREFN
VCC _A
VCC _A
RBC1
RBC0
GND_A
GND_CMOS
TD0
TD1
TD2
VCC_CMOS
TD3
TD4
TD5
TD6
VCC_CMOS
TD7
TD8
TD9
GND_CMOS
GND_TX
TC1
VCC _RX
RC1
GND_A
VCC _A
DOUT_TXP
DOUT_TXN
VCC _A
VCC _A
GND_CMOS
VCC _A
GND_A
VCC _A
DIN_RXP
VCC _A
DIN_RXN
GND_RX
PHD OR PJD PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
description (continued)
The intended application of this device is to provide building blocks for developing point-to-point baseband data
transmission over controlled-impedance media of approximately 50 Ω to 75 Ω. The transmission media can be
printed circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75FC1000 performs the data serialization and deserialization (SERDES) functions for the fibre channel
physical layer interface. The transceiver operates at 1.0625 Gbps (typical), providing up to 100 MBps of
bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded
data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at
pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial
stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with
respect to two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel bytes in RBC
clock rising edges.
The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver
can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.
The SN75FC1000 provides an internal loopback capability for self-test purposes. Serial data from the serializer
is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.
The SN75FC1000 is characterized for operation from 0°C to 70°C.
2
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• DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
functional block diagram
LOOPEN
TX+
TX–
TD0 – TD9
10
/
10-Bit
Register
10
/
Clock
Multiplier
REFCLK
106.25 MHz
SYNCEN
Synchronous
Detect
SYNC
RD0 – RD9
Shift
Register
10
/
10-Bit
Register
10
/
Shift
Register
53 MHz
RBC0
÷2
RBC1
53 MHz
106.25 MHz
PLL Clock
Recovery and
Data Retiming
2:1
MUX
RX+
RX–
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3
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
I/O structures
PECL inputs (DIN_RXP, DIN_RXN)
PECL outputs (DIN_TXP, DIN_TXN)
VDD
VDD
100 Ω
DIN_RXP
DOUT_TXP
4 kΩ
VCM
VDD
+
_
VDD
4 kΩ
DIN_RXN
DOUT_TXN
CMOS inputs (TD0 – TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)
VDD
VDD
TERMINALS
P
R1
120 Ω
Input
Open Circuit Open Circuit
LOOPEN
Open Circuit
400 kΩ
400 kΩ
Open Circuit
N
CMOS outputs (RD0 – RD9, RBC0, RBC1, SYNC)
VDD
P
Output
N
4
POST OFFICE BOX 655303
R2
REFCLK, TD0 – TD9
SYNCEN, LCKREFN
R2
R1
• DALLAS, TEXAS 75265
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
TYPE
DOUT_TXP
DOUT_TXN
62
61
Output
Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface
to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.0625 Gbps.
DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is
low .
DIN_RXP
DIN_RXN
54
52
Input
Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface
from a copper or an optical I/F module. These terminals receive NRZ data at a rate of 1.0625 Gbps and
are active when LOOPEN is held low.
LCKREFN
27
Input
Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied
REFCLK signal. LCKREFN prelocks or resets the receive PLL.
LOOPEN
19
Input
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted
serial data is directly routed to the inputs of the receiver. This provides a self-test capability in
conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during
the loop-back test. LOOPEN is held low during standard operational state with external serial outputs
and inputs active.
RBC0
RBC1
31
30
Output
Receive byte clock. RBC0 and RBC1 are 53.125-MHz recovered clocks used for synchronizing the
10-bit output data on RD0 – RD9. The 10-bit output data words are valid on the rising edges of RBC0
and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
RC1,
RC0
49
48
Analog
Receive capacitor. RC0 and RC1 are external capacitor connections used for the receiver internal PLL
filter. The recommend value for this external capacitor is 2 nF.
45,44,43,4
140,39,38,
3635,34
Output
Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol layer.
The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the K28.5
character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.
REFCLK
22
Input
Reference clock. REFCLK is an external 106.25 MHz input clock that synchronizes the receiver and
transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for
serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.
SYNC
47
Output
Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data
path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is
activated (asserted high).
SYNCEN
24
Input
Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function
is activated. When this function is enabled, the transceiver detects the K28.5 character (0011111010
negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required.
When SYNCEN is low, serial input data is unframed in RD0 – RD9.
TC1
TC0
16
17
Analog
Transmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal
PLL filter. The recommended value of this external capacitor is 2 nF.
2,3,4,6
7,8,9,11
12,13
Input
Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver
for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising
edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.
I/O and DATA
RD0 – RD9
TD0 – TD9
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5
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
NO.
TYPE
20,28,29,53
55,57,59,60
63
Supply
Analog power. VCC _A provides a supply reference voltage for the high-speed analog circuits.
5,10,23,
Supply
Digital PECL logic power. VCC _CMOS provides an isolated low-noise power supply for the logic
circuits.
VCC _RX
50
Supply
Receiver power. VCC _RX provides a low-noise supply reference voltage for the receiver high-speed
analog circuits.
VCC _TTL
VCC _TX
42,37
Supply
TTL power. VCC _TTL provides a supply reference voltage for the receiver TTL circuits.
18
Supply
Transmitter power. VCC _TX provides a low-noise supply reference voltage for the transmitter
high-speed analog circuits.
21,32,56,64
Ground
Analog ground. GND_A provides a ground reference for the high-speed analog circuits.
1,14,
25,58
Ground
Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits.
GND_ RX
51
Ground
Receiver ground. GND_ RX provides a ground reference for the receiver circuits.
GND_TTL
33,46
Ground
TTL circuit ground. GND_TTL provides a ground for TTL interface circuits.
GND_TX
15
Ground
Transmitter ground. GND_TX provides a ground reference for the transmitter circuits.
RESERVED
26
POWER
VCC _A
VCC _CMOS
GROUND
GND_ A
GND_CMOS
MISCELLANEOUS
Reserved. Internally pulled to GND, leave open or assert low.
detailed description
data transmission
The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0 – TD9) on the rising edge
of REFCLK (106.25 MHz). The reference clock is also used by the serializer, which multiplies the clock by a
factor of 10 providing a 1.0625 Gbaud signal that is fed to the shift register. The data is then transmitted
differentially at PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9.
transmission latency
The data transmission latency of the SN75FC1000 is defined as the delay from the initial 10-bit word load to
the serial transmission of bit 9. The typical transmission latency is 13 ns.
data reception
The receiver of the SN75FC1000 deserializes 1.0625 Gbps differential serial data. The 8b/10b data (or
equivalent) is retimed based on an extracted clock from the serial data. The serial data is then aligned to the
10-bit word boundaries and presented to the protocol controller along with two receive byte clocks (RBC0,
RBC1). RBC0 and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered
1.0625 Gbps (531 MHz) clock by 10 providing for two 53-MHz signals. The receiver presents the protocol device
byte 0 of the received data valid on the rising edge of RBC1.
NOTE:
This allows the option of byte alignment without the use of the synchronous detection
(SYNC) function by the protocol device.
The receiver PLL can lock to the incoming 1.0625 GHz data without the need for a lock-to-reference preset. The
received serial data rate (RX+ and RX–) should be 1.0625 Gbps ± 0.01% (100 ppm) for proper operation.
6
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SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
data reception (continued)
During a bus error condition or word alignment, the receive byte clocks RBC0 and RBC1 are stretched (never
truncated), ensuring that their frequency never exceeds 60 MHz. When the incoming serial data does not meet
its frequency requirements, then the receive byte clock frequency is maintained and never exceeds 60 MHz.
receive PLL operation
The receive PLL provides automatic locking to the incoming data. At power-up, the maximum initial lock time
is 500 µs. The PLL can also be initiated or set to phase lock to the externally supplied reference clock by enabling
lock-to-reference (LCKREFN). The lock-to-reference causes the receive PLL to lock to 10× the reference clock
(REFCLK) input providing a PLL preset and reset capability.
If during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data
and/or a frequency wander of up to 200 ppm, then the PLL recovers lock within 2.4 µs (2500 serial bit times).
Any condition exceeding these values is considered a power-up scenario and the PLL recovers lock within
500 µs.
receiver word alignment
The SN75FC1000 uses a 10-bit K 28.5 character (comma character) word alignment scheme. The following
sections explain how this scheme works and how it realigns itself.
comma character on expected boundary
The SN75FC1000 provides 10-bit K 28.5 character recognition and word alignment. The 10-bit word alignment
is enabled by forcing SYCNEN high. This enables the function that examines and compares ten bits of serial
input data to the K 28.5 synchronization character. The K 28.5 character is defined in the fibre channel standard
as a pattern consisting of 0011111010 (a negative number beginning disparity) with the 7 MSBs (0011111)
referred to as the comma character. The K 28.5 character was implemented specifically for aligning fibre
channel data words. As long as the K 28.5 character falls within the expected 10-bit word boundary, the received
10-bit data is properly aligned and data realignment is not required. Figure 1 shows the timing characteristics
of RBC0, RBC1, SYNC and RD0 – RD9 while synchronized.
NOTE:
The K28.5 character is valid on the rising edge of RBC1.
RBC0
RBC1
SYNC
RD0 – RD9
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
Figure 1. Synchronous Timing Characteristics Waveforms
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7
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
comma character not on expected boundary
When synchronization is enabled and a K 28.5 character straddles the expected 10-bit word boundary, then
word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character
following the misaligned K 28.5, but the following K 28.5 and all subsequent data is aligned properly as shown
in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched
or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra
10 bit times. This occurs during a worst case scenario when the K 28.5 is aligned to the falling edge of RBC1
instead of the rising edge. Fibre channel compliant systems transmit a minimum of three consecutively ordered
K28.5 data sets between frames and ensure that the receiver sees at least two of K 28.5 sets (the fabric is
allowed
to
drop
one).
Figure 2 shows the timing characteristics of the data realignment.
Systems that do not require framed data can disable byte alignment by tying SYNCEN low.
When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K 28.5
character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK
period.
Typical Receive
Path Latency = 21 ns
Serial Rx Data Stream
DIN_RxP – DIN_RxN
K28.5
Dxx.x
Dxx.x
K28.5
10 Bit Times
Dxx.x
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x
20 Bit Times
(MAX)
10 Bit Times
RBC0
RBC1
Corrupted Data
Misalignment
Corrected
Worst Case
Misaligned K 28.5
RD0 – RD9
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x
K28.5
Dxx.x
Dxx.x
Dxx.x
K28.5
SYNC
Figure 2. Word Realignment Timing Characteristics Waveforms
data reception latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The receive latency is typically 21 ns.
loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loop-back path.
Enabling LOOPEN causes serially transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. The external differential output is
held in a static state during loop-back testing.
8
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SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
absolute maximum ratings†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to 4 V
Input voltage, VI (TTL, PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to 4 V
Input voltage, VI (I/O Terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to 5.5 V
Output current IO (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output current IO (PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Voltage range at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to VCC + 0.5 V
Electrostatic discharge, 5-V tolerant terminals (see Note 2) . . . . . . . . . . . . . . . . . . . Class 1, A:1 kV, B:150 V
Electrostatic discharge, all other terminals (see Note 2) . . . . . . . . . . . . . . . . . . . . . . Class 1, A:2 kV, B:200 V
Characterized free-air operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.
2. This parameter is tested in accordance with MIL-PRF-38535.
recommended operating conditions
PARAMETER
TEST CONDITIONS
Supply voltage, VCC
MIN
3.14
NOM
MAX
UNIT
3.3
3.47
V
Supply current, ICC (static)
Static pattern†
160
250
mA
Power dissipation, PD (static)
Outputs open,
(static pattern)†
530
875
mW
Supply current, ICC (dynamic)
K28.5
230
310
mA
Power dissipation, PD (dynamic)
Outputs open,
(K28.5)
760
1085
mW
Operating free-air temperature, TA
† Power (static pattern) = 106.25 MHz to receiver and 5 ones and 5 zeros to transmitter.
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0
70
°C
9
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
reference clock (REFCLK) timing requirements over recommended operating conditions (unless
otherwise noted)†
PARAMETER
TEST CONDITIONS
MIN
Frequency
NOM
MAX
106.25
Accuracy
–100
Duty cycle
40%
MHz
100
50%
UNIT
ppm
60%
Jitter
Random and deterministic
40
ps
† This clock should be crystal referenced to meet the requirements of the this table. The maximum rate of frequency change specified is valid after
10 seconds from power on.
electrical characteristics over recommended operating conditions (unless otherwise noted)
TTL Signals: TD0 – TD9, REFCLK, LOOPEN, SYNCEN, SYNC, RD0 – RD9, RBC0, RBC1, LCKREFN
PARAMETER
VOH
VOL
High-level output voltage
VIH
VIL
High-level input voltage
IIH
VCC = MIN,
VCC = MIN,
Low-level output voltage
IOH = – 400 µA
IOL = 1 mA
MIN
2.4
2
Input High current
Input Low current
ci
Input capacitance
REFCLK
VCC = MAX,
VCC = MAX,
VI = 2.4 V
VI = 2.4 V
REFCLK
VCC = MAX,
VCC = MAX,
VI = 0.4 V
VI = 0.4 V
TYP
MAX
3
0.25
Low-level input voltage
IIL
10
TEST CONDITIONS
V
0.4
V
5.5
V
0.8
V
40
µA
900
µA
– 40
µA
– 900
µA
4
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• DALLAS, TEXAS 75265
UNIT
pF
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
TRANSMITTER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
|VOD|
(peak to peak)
Differential driver output voltage (peak-to-peak)
VOC
Driver common-mode output voltage
MIN
TYP
MAX
RL = 75 Ω,
See Figure 3
1200
2200
RL = 50 Ω,
See Figure 3
1200
2200
RL = 75 Ω
2100
UNIT
mV
mV
differential switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Serial data deterministic jitter (peak-to-peak)
Differential output jitter
75
ps
Serial data total jitter (peak-to-peak)
Differential output jitter
197
ps
tr3
Differential signal rise time (20% to 80%)
ps
tf3
Differential signal fall time (20% to 80%)
RL = 75 Ω,,
See Figure 3
300
300
ps
CL = 5 pF,,
80%
TX+
≈ VCC – 0.7 V
50%
20%
≈ VCC – 1.6 V
80%
≈ VCC – 0.7 V
tf
tr
TX–
50%
20%
≈ VCC – 1.6 V
80%
≈1 V
tr
tf
VOD
50%
20%
≈ –1 V
tf3
tr3
Figure 3. Differential and Common-mode Output Voltage Definitions
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11
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
TRANSMITTER SECTION
transmitter timing requirements over recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS
MIN
t su1
Setup time, TD0 – TD9 valid to REFCLK ↑
See Figure 4
2
t h1
Hold time, REFCLK ↑ to TD0 – TD9 invalid
See Figure 4
1.5
Parallel-to-serial data latency
NOM
MAX
UNIT
ns
ns
13
ns
transmit interface timing
The transmit interface is defined in the 10 b specification as the 10-bit parallel data input to the physical layer
for serial transmission. The timing values are specified from REFCLK midpoint to valid input signal levels or from
valid input signal levels to REFCLK midpoint.
50%
REFCLK
tsu1
th1
ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉ
TD0 – TD9
Valid
Valid
Figure 4. Transmit 10-Bit Interface Timing Waveforms
12
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Valid
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
RECEIVER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
|VID |
TEST CONDITIONS
Differential input voltage
MIN
TYP
200
MAX
UNIT
1300
mV
receiver and phase-locked loop performance characteristics over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Jitter tolerance (input data eye closure)
See FC-PH-0 specification
Data acquisition lock time
From power up
Data relock time
† UI is the unit interval of a single bit (941 ps).
MIN
TYP
From synchronization loss
MAX
UNIT†
70%
UI
500
us
2500
ns
receive clock timing requirements over recommended operating condtions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
Clock frequency, RCLK (0)
53.125
MHz
fclk
Clock frequency, RCLK (1)
(180 deg out of phase with RCLK (0))
53.125
MHz
tr4
Data rise time
See Figure 5
0.7
4
ns
tf4
Data fall time
See Figure 5
0.7
4
ns
tr5
Rise time, single-ended output signal on RCLK
See Figure 5
0.7
2
ns
tf5
Fall time, single-ended output signal on RCLK
See Figure 5
0.7
2
ns
40%
60%
Duty cycle, RCLK
t(skew)
t su2
Skew time, RCLK(1) ↑ to RCLK(0) ↑
See Figure 6
8.9
Setup time, RD0 – RD9 valid to RCLK(0) ↑
See Figure 6
3
ns
t su3
Setup time, RD0 – RD9 valid to RCLK(1) ↑
See Figure 6
3
ns
t su4
Setup time, RCLK(1) ↑ to RD0 – RD9 invalid
See Figure 6
1.5
ns
t su5
Setup time, RCLK(0) ↑ to RD0 – RD9 invalid
See Figure 6
1.5
ns
Serial-to-parallel data latency
9.4
21
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9.9
ns
ns
13
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
RECEIVER SECTION
80%
50%
Data
20%
tf4
tr4
80%
Clock
50%
20%
tf5
tr5
Figure 5. Receiver Data Measurement Levels
t(skew)
50%
50%
RCLK(0)
50%
RCLK(1)
50%
tsu2
tsu3
tsu5
tsu4
RD0 – RD9
ÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ
ÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ
Valid
Valid
Valid
Valid
Figure 6. Receiver Interface Timing Waveforms
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• DALLAS, TEXAS 75265
Valid
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
APPLICATION INFORMATION
Ferrite Bead
Ferrite Bead
3.3 V
50
0.01 µF
VCC_RX
51
5 Ω at 100 MHz
18
VCC_TX
GND_RX
GND_TX
SN75FC1000
DOUT_TXP
15
3.3 V
0.01 µF
62
Controlled Impedance
Transmission Line
R(pd)
(see Note A)
10
/
TD0 – TD9
22
27
19
Host
Protocol
Device
24
47
2
/
10
/
REFCLK
DOUT_TXN
61
Controlled Impedance
Transmission Line
54
Controlled Impedance
Transmission Line
LCKREFN
LOOPEN
SYNCEN
SYNC
DOUT_RXP
RD0 – RD9
31,30
50 Ω – 75 Ω
RBC0,RBC1
Vt
(see Note B)
DOUT_RXN
49
PLL Filter
Capacitor
= 2 nF
48
RC1
RC0
TC1
TC0
52
Controlled Impedance
Transmission Line
16
17
PLL Filter
Capacitor
= 2 nF
NOTES: A. R(pd) – This value is set to match the falling edge to rising edge transistion times, typically 150 Ω.
B. Vt (termination voltage): for termination R = 50 Ω, Vt = VCC – 1.3 V; R = 75 Ω, Vt = GND
Figure 7. Typical Application Circuit
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15
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
The SN75FC1000 incorporates the latest development in TI’s package line. The new patent-pending design,
designated the PWP delivers thermal performance comparative to a heat-spreader design in a true low-profile
package. The PWP, for the SN75FC1000 is designed to maximize heat transfer away from the die through the
top of the chip. As seen in Figures 9 and 10 the bottom of the leadframe is deep downset towards the top of
the chip, providing a thermal path away from the die and board. All this has been accomplished without
exceeding the 1.15 mm height of the TQFP. This package in the 10mm × 10mm TQFP (PJD) provides a thermal
resistance RθJA of 40°C/W and the package in the 14mm × 14mm TQFP (PHD) provides a RθJA of 40°C/W.
Figure 8. Heat-Spreader Design
Figure 9. Leadframe Downset
16
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SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
PHD (S-PQFP-G64)
PowerPAD PLASTIC QUAD FLATPACK (DIE DOWN)
0,40
0,30
0,80
48
0,20 M
33
32
49
Thermal Pad
(see Note D)
0,13 NOM
64
17
Gage Plane
1
16
12,00 TYP
14,05
SQ
13,95
0,25
0,15
0,05
0°– 7°
0,75
0,45
16,15
SQ
15,85
1,05
0,95
Seating Plane
0,10
1,20 MAX
4087742/A 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
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17
SN75FC1000
1-GIGABIT FIBRE CHANNEL TRANSCEIVER
SLLS254E – AUGUST 1996 – REVISED MAY 1998
MECHANICAL INFORMATION
PJD (S-PQFP-G64)
PowerPAD PLASTIC QUAD FLATPACK (DIE DOWN)
0,27
0,17
0,50
48
0,08 M
33
32
49
Thermal Pad
(See Note D)
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,15
0,05
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4147703/A 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
18
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75FC1000PHD
OBSOLETE
HTQFP
PHD
64
TBD
Call TI
Call TI
SN75FC1000PJD
OBSOLETE
HTQFP
PJD
64
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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