Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 Bus-Polarity Correcting RS-485 Transceiver With IEC-ESD Protection FEATURES 1 • • • • • • • Exceeds Requirements of EIA-485 Standard Bus-Polarity Correction within 76 ms (tFS) Data Rate: 300 bps to 250 kbps Works with Two Configurations: – Failsafe Resistors Only – Failsafe and Differential Termination Resistors Up to 256 Nodes on a Bus (1/8 unit load) SOIC-8 Package for Backward Compatibility Bus-Pin Protection: – ±16 kV HBM protection – ±12 kV IEC61000-4-2 Contact Discharge – +4 kV IEC61000-4-4 Fast Transient Burst APPLICATIONS • • • • • • E-Metering Networks Industrial Automation HVAC Systems DMX512-Networks Process Control Battery-Powered Applications • • Motion Control Telecom Equipment DESCRIPTION The SN65HVD888 is a low-power RS-485 transceiver with automatic bus-polarity correction and transient protection. Upon hot plug-in, the device detects and corrects the bus polarity within the first 76 ms of bus idling. On-chip transient protection protects the device against IEC61000 ESD and EFT transients. This device has robust drivers and receivers for demanding industrial applications. The bus pins are robust to electrostatic discharge (ESD) events, with high levels of protection to Human-Body Model (HBM), Air-Gap Discharge, and Contact Discharge specifications. The device combines a differential driver and a differential receiver, which operate together from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. The device features a wide common-mode voltage range making the device suitable for multi-point applications over long cable runs. The SN65HVD888 is available in an SOIC-8 package, and is characterized from –40°C to 85°C. TYPICAL NETWORK APPLICATION WITH POLARITY CORRECTION (POLCOR) Cross-wire fault 0 5V R R DE D D A B B 1k A B A POLCOR RE R R 1k A D B Master SN65HVD82 RE DE D Slave SN65HVD888 R R D D POLCOR R RE DE POLCOR D Slave SN65HVD888 R RE DE D Slave SN65HVD888 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SOIC-8 (TOP VIEW) 1 2 3 4 8 7 6 5 Vcc B A GND R RE DE D Vcc POLCOR R RE DE D Block Diagram B A GND DRIVER PIN FUNCTIONS INPUT ENABLE D DE OUTPUTS A DESCRIPTION B NORMAL MODE H H H L Actively drives bus High L H L H Actively drives bus Low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drives bus High POLARITY-CORRECTING MODE (1) (1) H H L H Actively drives bus Low L H H L Actively drives bus High X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H L H Actively drives bus Low The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when /RE turns from Low to High. RECEIVER PIN FUNCTIONS DIFFERENTIAL INPUT ENABLE OUTPUT VID = VA – VB /RE R VIT+ < VID L H Receive valid bus High VIT– < VID < VIT+ L ? Indeterminate bus state DESCRIPTION NORMAL MODE VID < VIT– L L Receive valid bus Low X H Z Receiver disabled X OPEN Z Receiver disabled Open, short, idle Bus L ? Indeterminate bus state POLARITY-CORRECTING MODE (1) VIT+ < VID L L Receive valid bus Low VIT– < VID < VIT+ L ? Indeterminate bus state VID < VIT– L H Receive polarity corrected bus High X H Z Receiver disabled X OPEN Z Receiver disabled Open, short, idle Bus L ? Indeterminate bus state (1) 2 The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when /RE turns from Low to High. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT MIN VCC MAX Supply voltage –0.5 7 Input voltage range at any logic pin –0.3 5.7 Voltage input range, transient pulse, A and B, through 100 Ω –100 100 Voltage range at A or B inputs –18 18 Receiver output current –24 24 Continuous total-power dissipation ±12 IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND ±4 IEC 60749-26 ESD (HBM), bus terminals and GND ±16 Test Method A114 (HBM), all pins TJ Junction temperature TSTG Storage temperature (1) mA See THERMAL INFORMATION table IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND JEDEC Standard 22 V kV ±4 Test Method C101 (Charged Device Model), all pins ±1.5 Test Method A115 (Machine Model), all pins ±100 V 170 –65 °C 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION SN65HVD888 THERMAL METRIC (1) PACKAGE SOIC (D) θJA Junction-to-ambient thermal resistance 116.1 θJCtop Junction-to-case (top) thermal resistance 60.8 θJB Junction-to-board thermal resistance (2) 57.1 ψJT Junction-to-top characterization parameter 13.9 ψJB Junction-to-board characterization parameter 56.5 θJCbot Junction-to-case (bottom) thermal resistance NA (1) (2) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. POWER DISSIPATION PARAMETER PD TEST CONDITIONS Unterminated Power Dissipation driver and receiver enabled, VCC = 5.5 V, TJ = 150°C RS-422 load 50% duty cycle square-wave signal at 250 kbps signaling rate: RS-485 load VALUE RL = 300 Ω, CL = 50 pF (driver) 164 RL = 100 Ω, CL = 50 pF (driver) 247 RL = 54 Ω, CL = 50 pF (driver), 316 UNITS Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 mW mW mW 3 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 4.5 5 5.5 VID Differential input voltage –12 12 VI Input voltage at any bus terminal (separate or common mode) (1) –7 12 VIH High-level input voltage (driver, driver-enable, and receiver-enable inputs) 2 VCC VIL Low-level input voltage (driver, driver-enable, and receiver-enable inputs) 0 0.8 –60 60 –8 8 Driver UNIT V IO Output current CL Differential load capacitance 50 pF RL Differential load resistance 60 Ω 1/tUI Signaling rate 0.3 250 TJ Junction temperature –40 150 TA (2) Operating free-air temperature (see THERMAL INFORMATION for additional information) –40 85 (1) (2) Receiver mA kbps °C The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER Driver differential-output voltage magnitude │VOD│ TEST CONDITIONS RL = 60 Ω, 375 Ω on each output from –7 to +12 V RL = 54 Ω (RS-485) RL = 100 Ω (RS-422) Δ│VOD│ VOC(SS) Steady-state common-mode output voltage ΔVOC Change in differential driver Center of two 27-Ω load common-mode output voltage resistors VOC(PP) Peak-to-peak driver commonmode output voltage COD Differential output capacitance VIT+ Positive-going receiver differential-input voltage threshold VIT– Negative-going receiver differential-input voltage threshold VHYS (1) Receiver differential-input voltage threshold hysteresis (VIT+ – VIT– ) VOH Receiver high-level output voltage IOH = –8 mA VOL Receiver low-level output voltage IOL = 8 mA II Driver input, driver enable, and receiver enable input current 4 See Figure 2 RL = 54 Ω, CL = 50 pF Change in magnitude of driver differential-output voltage (1) See Figure 1 MIN TYP 1.5 2.5 1.5 2.5 2 3 –0.2 0 MAX V 0.2 See Figure 2 See Figure 2 UNIT V 1 VCC / 2 3 –0.2 0 0.2 mV 850 8 35 V pF 100 mV –100 –35 mV 40 60 mV 2.4 VCC – 0.3 0.2 –2 V 0.4 V 2 µA Under any specific conditions, VIT+ is ensured to be at least VHYS higher than VIT–. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP IOZ Receiver high-impedance output current VO = 0 V or VCC, /RE at VCC │IOS│ Driver short-circuit output current │IOS│ with VA or VB from –7 to +12 V II Bus input current (driver disabled) VCC = 4.5 to 5.5 V or VI = 12 V VCC = 0 V, DE at 0 V VI = –7 V Driver and receiver enabled DE = VCC, /RE = GND, No load Driver enabled, receiver disabled DE = VCC, /RE = VCC, No load 650 Driver disabled, receiver enabled DE = GND, /RE = GND, No load 750 Driver and receiver disabled DE = GND, D = GND /RE = VCC, No load ICC Supply current (quiescent) Supply current (dynamic) –10 MAX 10 150 75 –100 125 –40 750 UNIT µA mA µA 900 0.4 5 MIN TYP MAX 400 700 1200 90 700 1000 25 200 µA See SWITCHING CHARACTERISTICS 3.3 ms > bit time > 4 μs (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT DRIVER tr, tf Driver differential-output rise and fall times tPHL, tPLH Driver propagation delay tSK(P) RL = 54 Ω, CL = 50 pF See Figure 3 Driver pulse skew, |tPHL – tPLH| tPHZ, tPLZ Driver disable time tPHZ, tPLZ Driver enable time Receiver enabled See Figure 4 and Figure 5 Receiver disabled 50 500 500 1000 3 9 18 30 85 195 1 15 ns ns µs RECEIVER tr, tf Receiver output rise and fall times tPHL, tPLH Receiver propagation delay time tSK(P) CL = 15 pF See Figure 6 Receiver pulse skew, |tPHL – tPLH| tPHZ, tPLZ Receiver disable time tPZL(1), tPZH(1) tPZL(2), tPZH(2) tFS ns 50 500 Driver enabled See Figure 7 20 130 ns Receiver enable time Driver disabled See Figure 8 2 8 µs Bus failsafe time Driver disabled See Figure 9 58 76 ms 44 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 5 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION DRIVER 375 Ÿ Vcc DE A D 0V or 5 V VOD -7V < Vtest < 12 V 60 Ÿ B 375 Ÿ Figure 1. Measurement of Driver Differential-Output Voltage With Common-Mode Load A 0V or 5 V RL/2 A D VA B VB VOD RL/2 B VOC(PP) CL VOC ûVOC(SS) VOC Figure 2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load 5V Vcc DE A D Input Generator VI 54 Ÿ VOD 50Ÿ 50% VI B CL= 50 pF 0V tPLH tPHL 90% 50% 10% VOD tr § 2V § -2V tf Figure 3. Measurement of Driver Differential-Output Rise and Fall Times and Propagation Delays A D VI 50% VI B DE Input Generator 5V VO S1 RL= 110 Ÿ CL= 50 pF 50Ÿ 0V tPZH 90% VO VOH 50% § 0V tPHZ Figure 4. Measurement of Driver Enable and Disable Times With Active-High Output and Pull-Down Load 5V 5V D DE Input Generator VI A RL= 110 Ÿ S1 B 50Ÿ CL= 50 pF VO 50% VI 0V tPZL VO tPLZ § 5V 50% 10% VOL Figure 5. Measurement of Driver Enable and Disable Times With Active-Low Output and Pull-up Load 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 PARAMETER MEASUREMENT INFORMATION (continued) RECEIVER 5V A Input Generator VI 50Ÿ 1.5V R VO 0V tPLH B tPHL 90% 50% 10% CL= 15 pF RE 0V 50% VI VOD tr VOH VOL tf Figure 6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays Vcc Vcc DE 0V or 5 V B Input Generator 50% 0V A D 5V VI R VO S1 VO CL= 15 pF RE tPHZ tPZH(1) 1 kŸ § 0V tPZL(1) 50Ÿ VI D at 5V S1 to GND VOH 90% 50% tPLZ VO 50% D at 0V S1 to VCC VCC 10% VOL Figure 7. Measurement of Receiver Enable and Disable Times With Driver Enabled 5V Vcc 1.5 V or 0 V Input Generator B 50% 0V A 0V or 1.5 V VI R VO RE tPZH(2) 1 kŸ VOH S1 VO CL= 15 pF 50% § 0V A at 1.5V B at 0V S1 to GND tPZL(2) VI VCC 50Ÿ VO 50% VOL A at 0V B at 1.5V S1 to VCC Figure 8. Measurement of Receiver Enable Times With Driver Disabled VI A Input Generator VI 50Ÿ 1.5V B RE 0V (DE = Low) R 50% 0V VO tPHL tFS 10 kŸ VCC VO 50% Figure 9. Measurement of Receiver Polarity-Correction Time With Driver Disabled Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 7 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and RE Inputs DE Input Vcc Vcc Vcc R Output 100k 1k 1k D,RE 1k DE 9V R 9V 100k 9V Vcc Receiver Inputs Driver Outputs Vcc 16V 16V R2 R2 R1 A A R R1 B B 16V R3 R3 16V Figure 10. Equivalent Input and Output Schematic Diagrams 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 DEVICE INFORMATION Low-Power Standby Mode When the driver and the receiver are both disabled (DE = Low and RE = High) the device enters standby mode. If the enable inputs are in the disabled state for only a brief time (for example: less than 100 ns), the device does not enter standby mode, preventing the SN65HVD888 from entering standby mode during driver or receiver enabling. Only when the enable inputs are held in the disabled state for a duration of 300 ns or more does the device enter low-power standby mode. In this mode most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. During VCC power-up, when the device is set for both driver and receiver disabled mode, the device may consume more than 5-µA of ICC disabled current because of capacitance charging effects. This condition occurs only during VCC power up. Bus Polarity Correction The SN65HVD888 automatically corrects a wrong bus-signal polarity caused by a cross-wire fault. In order to detect the bus polarity, all three of the following conditions must be met: • A failsafe-biasing network (commonly at the master node) must define the signal polarity of the bus • A slave node must enable the receiver and disable the driver (/RE = DE = Low) • The bus must idle for the failsafe time, tFS-max After the failsafe time has passed, the polarity correction is complete and is applied to both the receive and transmit channels. The status of the bus polarity is latched within the transceiver and is maintained for subsequent data transmissions. NOTE Data string durations of consecutive 0s or 1s exceeding tFS-min can accidently trigger a wrong polarity correction and must be avoided. Figure 11 shows a simple point-to-point data link between a master node and a slave node. Because the master node with the failsafe biasing network determines the signal polarity on the bus, an RS-485 transceiver without polarity correction, such as SN65HVD82, suffices. All other bus nodes, typically performing as slaves, require the SN65HVD888 transceiver with polarity correction. VS-Master Master node Vdd VS-Master VS-Slave VSM Vcc RxD DIR TxD DGND Vdd R RFS A RE DE B D VS-Slave Vcc A RT RT (opt.) (opt.) POLCOR MCU R Slave node B GND GND MCU RE DE D RFS RxD DIR TxD DGND Figure 11. Point-To-Point Data Link With Cross-Wire Fault Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum failsafe time, tFS-max, of a slave transceiver. This idle time is accomplished by driving the direction control line, DIR, low. After a time, t > tFS-max, the master begins transmitting data. Because of the indicated cross-wire fault between master and slave, the slave node receives bus signals with reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is pulled-down during power-up and then is actively driven low by the slave MCU. The polarity correction begins as soon as the slave supply is established and ends after approximately 44 to 76 ms. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 9 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com DIRm Master signals Low due to pull-down or actively driven high Z Dm VAm VFS 0V -Vod +Vod +Vid -Vid VBm VBs VFS 0V VAs VSs Slave signals DIRs Low due to pull-down and then actively driven Rs tFS Uncorrected R output: R is in phase with wrong VID polarity Corrected R output: R is reversed to wrong VID polarity Figure 12. Polarity Correction Timing Prior to a Data Transmission Initially the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, RS, turns low. After tFS has passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic reverses the input signal and RS turns high. At this point all incoming bus data with reversed polarity are polarity corrected within the transceiver. Because polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the POLCOR logic and then fed into the driver. The reversed data from the slave MCU are reversed again by the cross-wire fault in the bus, and the correct bus polarity is reestablished at the master end. This process repeats each time the device powers up and detects an incorrect bus polarity. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 APPLICATION INFORMATION Device Configuration The SN65HVD888 is a half-duplex RS-485 transceiver operating from a single 5-V ±10% supply. The driver and receiver enable pins allow for the configuration of different operating modes. DE D D B RE A DE D GND R D R Vcc B RE A DE D GND Vcc B A D GND c) Receiver always on b) Combined enable signals for use as directional control pin a) Independent driver and receiver enable signals R POLCOR RE R Vcc POLCOR R POLCOR R Figure 13. Transceiver Configurations Using independent enable lines provides the most flexible control as the lines allow for the driver and the receiver to be turned on and turned off individually. While this configuration requires two control lines, it allows for selective listening to the bus traffic, whether the driver is transmitting data or not. Only this configuration allows the SN65HVD888 to enter low-power standby mode because it allows both the driver and receiver to be disabled simultaneously. Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device operates as a receiver. Tying the receiver enable to ground and controlling only the driver-enable input also uses only one control line. In this configuration a node not only receives the data on the bus sent by other nodes but also receives the data sent on the bus, enabling the node to verify the correct data has been transmitted. Bus Design An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over long cable length. Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24. The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and environmental conditions. Table 1. VID with a Failsafe Network and Bus Termination VCC 5V RL Differential Termination 54 Ω RFS Pull up RFS Pull down VID 560 Ω 560 Ω 230 mV 1 KΩ 1 KΩ 131 mV 4.7 KΩ 4.7 KΩ 29 mV 10 KΩ 10 KΩ 13 mV An external failsafe-resistor network must be used to ensure failsafe operation during an idle bus state. When the bus is not actively driven, the differential receiver inputs could float allowing the receiver output to assume a random output. A proper failsafe network forces the receiver inputs to exceed the VIT threshold, thus forcing the SN65HVD888 receiver output into the failsafe (high) state. Table 1 shows the differential input voltage (VID) for various failsafe networks with a 54-Ω differential bus termination. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 11 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com Cable Length Versus Data Rate There is an inverse relationship between data rate and cable length, which means the higher the data rate, the shorter the cable length; and conversely, the lower the data rate the longer the cable length. While most RS-485 systems use data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of up to 250 kbps even at distances of 4000 ft and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%. 10000 CABLE LENGTH - ft 5,10,20 % Jitter 1000 Conservative Characteristics 100 10 100 1k 10k 100k 1M 10M 100M DATA RATE - bps Figure 14. Cable Length vs Data Rate Characteristic Stub Length When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. The reason for the short distance is because a stub presents a nonterminated piece of bus line which can introduce reflections if the distance is too long. As a general guideline, the electrical length or round-trip delay of a stub should be less than one-tenth of the rise time of the driver, thus leading to a maximum physical stub length of as shown in Equation 1. LStub ≤ 0.1 × tr × v × c where • • • tr is the 10/90 rise time of the driver c is the speed of light (3 × 108 m/s or 9.8 × 108 ft/s) v is the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c (1) Based on Equation 1, with a minimum rise time of 400 ns, Equation 2 shows the maximum cable-stub length of the SN65HVD888. LStub ≤ 0.1 × 400 × 10-9 × 3 108 × 0.78 = 9.4 m (or 30.6 ft) (2) LS A B R D R RE DE D Figure 15. Stub Length 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 3- to 5-V Interface Interfacing the SN65HVD888 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept 3-V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must be level-shifted by a Schottky diode and a 10-k resistor to connect to the controller input (see Figure 16). When R is high, the diode is reverse biased and the controller supply potential lies at the controller RxD input. When R is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the controller RxD input. 3.3V 10k 5V BAS70 MCU RxD 1 RCV 2 RE DRV 3 DE TxD 4 D Vcc 8 A 7 B 6 GND 5 R HVD8X 0.1µF Figure 16. 3-V to 5-V Interface Noise Immunity The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, VID, is greater than +200 mV, the receiver output turns high, for VID < –200 mV the receiver outputs low. The SN65HVD888 transceiver implements high receiver noise-immunity by providing a typical positive-going input threshold of 35 mV and a minimum hysteresis of 40 mV. In the case of a noisy input condition therefore, a differential noise voltage of up to 40 mVPP can be present without causing the receiver output to change states from high to low. Transient Protection The bus terminals of the SN65HVD888 transceiver family possess on-chip ESD protection against ±16 kV HBM and ±12 kV IEC61000-4-2 contact discharge. The International Electrotechnical Commision (IEC) ESD test is far more severe than the HBM ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC model produce significantly higher discharge currents than the HBM model. High-Voltage Pulse Generator RC RD 50M (1M) 330Ω (1.5k) CS 150pF (100pF) Device Under Test Current - A As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method. Although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. 40 35 30 25 20 15 10 5 0 10kV IEC 10kV HBM 0 50 100 150 200 250 300 Time - ns Figure 17. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 13 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common discharge events occur because of human contact with connectors and cables. Designers may choose to implement protection against longer duration transients, typically referred to as surge transients. Figure 9 suggests two circuit designs providing protection against short and long duration surge transients, in addition to ESD and Electrical Fast Transients (EFT) transients. Table 2 lists the bill of materials for the external protection devices. EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the switching of power systems, including load changes and short circuits switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems. Figure 18 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD transient. In the diagram on the left of Figure 18, the tiny blue blip in the bottom left corner represents the power of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike, and certainly dwarfs against the 500-V surge transient. This type of transient power is well representative of factory environments in industrial and process automation. The diagram on the fright of Figure 18 compares the enormous power of a 6-kV surge transient, most likely occurring in e-metering applications of power generating and power grid systems, with the aforementioned 500-V surge transient. 22 20 18 16 14 12 10 8 6 4 2 0 Pulse Power - MW Pulse Power - kW NOTE The unit of the pulse-power changes from kW to MW, thus making the power of the 500-V surge transient almost dropping off the scale. 0.5kV Surge 4kV EFT 10kV ESD 0 5 10 15 20 25 30 35 40 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 6kV Surge 0.5kV Surge 0 5 10 15 20 25 30 35 40 Time - μs Time - μs Figure 18. Power Comparison of ESD, EFT, and Surge Transients In the case of surge transients, hgih-energy content is signified by long pulse duration and slow decaying pulse power The electrical energy of a transient that is dumped into the internal protection cells of the transceiver is converted into thermal energy. This thermal energy heats the protection cells and literally destroys them, thus destroying the transceiver. Figure 19 shows the large differences in transient energies for single ESD, EFT, and surge transients as well as for an EFT pulse train, commonly applied during compliance testing. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 1000 100 Surge Pulse Energy - Joule 10 1 EFT Pulse Train 0.1 0.01 EFT 10-3 10-4 ESD 10-5 10-6 0.5 1 2 4 6 8 10 15 Peak Pulse Voltage - kV Figure 19. Comparison of Transient Energies Table 2. Bill of Materials Device Function Order Number Manufacturer XCVR 5-V, 250-kbps RS-485 Transceiver SN65HVD888 R1, R2 10-Ω, Pulse-Proof Thick-Film Resistor CRCW0603010RJNEAHP Vishay TVS Bidirectional 400-W Transient Suppressor CDSOT23-SM712 Bourns TBU1, TBU2 Bidirectional. TBU-CA-065-200-WH Bourns MOV1, MOV2 200mA Transient Blocking Unit 200-V, MetalOxide Varistor MOV-10D201K Bourns Vcc Vcc Vcc 10k 1 R 2 RE DIR 3 DE TxD 4 D RxD MCU TI Vcc 8 A 7 B 6 GND 5 XCVR 0.1μF Vcc 10k R1 1 R 2 RE DIR 3 DE TxD 4 D RxD TVS MCU 8 A 7 B 6 GND 5 XCVR R2 10k Vcc 0.1μF R1 TBU1 MOV1 TVS MOV2 R2 10k TBU2 Figure 20. Transient Protections Against ESD, EFT, and Surge Transients The left circuit shown in Figure 20 provides surge protection of ≥ 500-V transients, while the right protection circuits can withstand surge transients of 5 kV. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 15 SN65HVD888 SLLSEH3 – JULY 2013 www.ti.com Design and Layout Considerations For Transient Protection Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design. In order for PCB design to be successful, begin with the design of the protection circuit in mind. 1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your board. 2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance and not the path of least impedance. 3. Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device. 4. Apply 100- to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, controller ICs on the board. 5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize effective via-inductance. 6. Use 1- to 10-k pullup or pulldown resistors for enable lines to limit noise currents in theses lines during transient events. 7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the transceiver and prevent it from latching up. – While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metaloxide varistors (MOVs) which reduce the transients to a few-hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to some 200 mA. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 SN65HVD888 www.ti.com SLLSEH3 – JULY 2013 Isolated Bus Node Design Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to the bus transceiver through a multi-channel, digital isolator (Figure 21). 0.1μF 2 Vcc D2 3 1:1.33 MBR0520L SN6501 GND D1 N 3 1 10μF IN OUT 1 3.3VISO TLV70733 10μF 0.1μF 4,5 L1 4 EN GND 2 10μF 7 R1 6 R2 MBR0520L ISO-BARRIER 3.3V 0.1μF PSU 0.1μF PE 0.1μF 4.7k PE 2 DVcc 5 6 XOUT XIN UCA0RXD P3.0 MSP430 F2132 DVss P3.1 UCA0TXD 4 16 11 12 15 1 16 Vcc1 Vcc2 7 10 EN1 ISO7241 EN2 6 11 OUTD IND 3 14 INA OUTA 4 13 INB OUTB 5 12 INC OUTC GND1 GND2 2,8 0.1μF 4.7k 1 2 3 4 8 Vcc R RE DE B HVD888 A D GND2 5 TVS 9,15 R HV Short thick Earth wire or Chassis Protective Earth Ground, Equipment Safety Ground Floating RS-485 Common A. C HV PE island R1,R2, TVS: see A. below RHV = 1MΩ, 2kV high-voltage resistor, TT electronics, HVC 2010 1M0 G T3 CHV = 4.7nF, 2kV high-voltage capacitor, NOVACAP, 1812 B 472 K 202 N T See Table 2. Figure 21. Isolated Bus Node With Transient Protection Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733. Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are pulled-up via 4.7-k resistors to limit input currents during transient events. While the transient protection is similar to the one in Figure 20 (left circuit), an additional high-voltage capacitor diverts transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This diversion is necessary as noise transients on the bus are usually referred to Earth potential. RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to prevent charging of the floating ground to dangerous potentials during normal operation. Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if expected that fast transients might charge CHV to high-potentials. Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire connecting this island to PE ground at the entrance of the power supply unit (PSU). In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are connecting to the chassis at the other end. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN65HVD888 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) SN65HVD888D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HVD888 SN65HVD888DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HVD888 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 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