UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 ADVANCED HIGH-POWER FACTOR PREREGULATOR FEATURES 1 • • • • • • • • • • • • Controls Boost PWM to Near-Unity Power Factor Limits Line Current Distortion To <3% World-Wide Operation Without Switches Accurate Power Limiting Fixed-Frequency Average Current-Mode Control High Bandwidth (5 MHz), Low-Offset Current Amplifier Integrated Current- and Voltage-Amplifier Output Clamps Multiplier Improvements: Linearity, 500 mV VAC Offset (Eliminates External Resistor), 0 V to 5 V Multout Common-Mode Range VREF GOOD Comparator Faster and Improved Accuracy ENABLE Comparator UVLO Options (16 V/10 V or 10.5 V/10 V) 300-µA Start-Up Supply Current DESCRIPTION The UC3854A/B products are pin compatible enhanced versions of the UC3854. Like the UC3854, these products provide all of the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the ac input line current waveform to correspond to the ac input line voltage. To do this the UC3854A/B uses average current mode control. Average current mode control maintains stable, low distortion sinusoidal line current without the need for slope compensation, unlike peak current mode control. A 1%, 7.5-V reference, fixed frequency oscillator, PWM, voltage amplifierwith soft-start, line voltage feedforward (VRMS squarer), input supply voltage clamp, and over current comparator round out the lilst of feataures. Available in the 16-pin N (PDIP), DW (SOIC Wide), and J (CDIP) and 20-pin Q (PLCC) package. See Ordering Information table for availability by temperature range. BLOCK DIAGRAM VAO MOUT 7 5 CAO PKLMT 3 REF 2 9 VCC 7.5 V REF (A) 16 V / 10 V (B) 10.5 V / 10 V RUN ENA 10 3V VRMS 15 VCC A VSENSE 11 IAC 6 R R S B X2 8 7.1 V IC POWER 2.65 V / 2.15 V 14 µA SS 13 16 GTDRV Q C RUN I MOUT + A B OSC C 4 ISENSE 14 12 CT RSET 20 V 1 GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2008, Texas Instruments Incorporated UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The UC3854A/B products improve upon the UC3854 by offering a wide bandwidth, low offset current amplifier, a faster responding and improved accuracy enable comparator, a VREF GOOD comparator, UVLO threshold options (16 V/10 V for offline, 10.5 V/10 V for startup from an auxiliary 12-V regulator), lower startup supply current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved amplifier current sinking capability, and low offset VAC pin reduce the external component count while improving performance. Improved common mode input range of the multiplier output/current amplifier input allow the designer greater flexibility in choosing amethod for current sensing. Unlike its predecessor, RSET controls only oscillator charging current and has no effect on clamping the maximum multiplier output current. This current is now clamped to a maximum of 2 × IAC at all times which simplifies the design process and provides foldback power limiting during brownout and extreme low line conditions. ORDERING INFORMATION TA UVLO TURN-ON (V) UVLO TURN-OFF (V) –55°C to 125°C –40°C to 85°C 0°C to 70°C PART NUMBERS CDIP-16 (V) PDIP-16 (N) SOIC-16 (DW) PLCC-20 (Q) – 16 10 – – – 10.5 10 UC1854BJ – – – 16 10 UC2854AJ UC2854AN UC2854ADW UC2854AQ 10.5 10 UC2854BJ UC2854BN UC2854BDW UC2854BQ 16 10 – UC2854AN UC2854ADW – 10.5 10 – UC2854BN UC2854BDW – ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage IGTDRV GTDRV current Input voltage Input current UCX854A, UCX854B UNIT 22 V Continuous 0.5 50% duty cycle 1.5 VSENSE, VRMS, ISENSE MOUT 11 PKLMT 5 RSET, IAC, PKLMT, ENA 10 mA 1 W Power dissipation TJ Junction temperature –55 to 150 Tstg Storage temperature –65 to 150 Tsol Lead temperataure, 1,6 mm (1/16 inch) from case for 10 seconds (1) 2 A V °C 300 Stresses beyond those listed under absolutemaximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periodsmayaffect device reliability. All voltages arewith respect to GND. Currents are positive into and negative out of, the specified terminal. ENA input is internally clamped to approximately 10 V. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC TJ MIN MAX 10 20 UC1854X –55 125 UC2854X –40 85 UC3854X 0 70 Supply voltage Operating junction temperature UNIT V °C THERMAL RESISTANCE PACKAGED DEVICES (1) (2) RESISTANCES CDIP-16 (J) θJC (°C/W) 28 (1) 45 27 34 θJA (°C/W) 80–120 90 (2) 50–130 (2) 43–75 (2) PDIP-16 (N) SOP-16 (DW) PLCC-20 (Q) θJC data values stated are derived from MIL-STD-1835B which states gthe baseline values shown are worst case (mean +2s) for a 60 × 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14,400 square mils. For device die sizes greater than 14,400 square mils use the following values, dual-in-line, 11°C/W; flat pack and pin grid array, 10°C/W.are at the end of each trace. θJA (junction-to-ambient) applies to devices mounted to five square inch FR4 PC board with one ounce copper where noted. When resitance range is given, lower values are for five square inch aluminum PC board. Test PWB is 0.062 inches thick and typically uses 0,635 mm trace widths for power packages and 1,3 mm trace widths for non-power packages with a 100 × 100 mil probe land are at the end of each trace. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B 3 UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V, VVSENSE = 3 V, –40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA < 70°C for the UC3854A and UC3854B, and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250 400 µA mA OVERALL CAO = 0 V, VCC = VUVLO–0.3 V Supply current, off VAO = 0 V, Supply current, on VCC turn-on threshold voltage VCC turn-off threshold voltage VCC hysteresis VCC clamp 12 18 UCx854A 15.0 16.0 17.5 UCx854B 8.0 10.5 11.2 UCx854A 9 10 12 UCx854B 7.8 10.3 11.0 UCx854A 5 6 7 UCx854B 0.10 0.22 0.50 18 20 22 2.9 3.0 3.1 V –500 —25 500 nA 70 100 IVCC = IVCC(on) + 5 mA V VOLTAGE AMPLIFIER Input voltage VSENSE bias current Open loop gain 2 V ≤ VOUT ≤ 5 V VOH High-level output voltage ILOAD = –500 µA VOL Low-level output voltage ILOAD = 500 µA ISC Output short-circuit current VOUT = 0 V Gain bandwidth product (1) fIN = 100 kHz, 10 mVp-p VCM = 0 V, TA = 25°C VCM = 0 V, Overtemperature dB 6 0.3 0.5 1.5 3.5 1 V mA MHz CURRENT AMPLIFIER Input offset voltage ISENSE Input bias current VCM = 0 V Open loop gain 2 V ≤ VOUT = 6 V VOH High-level output voltage ILOAD = –500 µA VOL Low-level output voltage ILOAD = 500 µA ISC Output short-circuit current VOUT = 0 V CMRR Common mode rejection range Gain bandwidth product (1) –4 0 –5.5 0 –500 500 80 110 fIN = 100 kHz, 10 mVp-p IREF = 0 mA, TA = 25°C 3 nA dB 8 0.3 0.5 1.5 3.5 –0.3 mV 5.0 5 V mA V MHz REFERENCE Output voltage ISC (1) 4 IREF = 0 mA 7.4 7.5 7.6 7.35 7.50 7.65 Load regulation 1 mA ≤ IREF ≤ 10 mA 0 8 20 Line regulation 12 V ≤ VCC ≤ 18 V 0 14 25 Short circuit current VREF = 0 V 25 35 60 V mV mA Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (Continued) VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V, VVSENSE = 3 V, –40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA < 70°C for the UC3854A and UC3854B, and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 85 100 115 kHz OSCILLATOR Initial accuracy TA = 25°C Voltage stability 12 V ≤ VCC ≤ 18 V Total variation Line, temperature 1% 80 120 kHz Ramp amplitude (peak-to-peak) 4.9 5.9 V Ramp valley voltage 0.8 1.3 V ENABLE/SOFT-START/CURRENT LIMIT Enable threshold voltage 2.35 Enaable hysteresis VFAULT = 2.5 V Enable input bias current Propagation delay to disable time VENA = 0 V (1) Soft-start charge current Enable overdrive = 100 mV VSS = 2.5 V Peak limit offset current 2.80 V 500 600 mV –2 –5 µA 24 µA 15 mV 300 10 Peak limit offset voltage 2.55 14 –15 VPKLMIT = –0.1 V –200 Peak limit propagation delay time (1) ns –100 µA 150 ns MULTIPLIER Output current, IA limited IAC = 100 µA, RSET = 10 kΩ VRMS = 1 V, –220 –200 –170 µA Output current, zero IAC = 0 µA, RSET = 10 kΩ –2.0 –0.2 2.0 µA Output current, power limited VRMS = 1.5 V Va = 6 V –230 –200 –170 µA VRMS = 1.5 V Va = 2 V –22 VRMS = 1.5 V Va = 5 V –156 VRMS = 5 V Va = 2 V –2 VRMS = 5 V Va = 5 V VRMS = 1.5 V Va = 6 V, TA = 25°C –1.1 –1.0 VCC = 15 V 12.0 12.8 Output current Gain constant (2) µA –14 –0.9 A/A GATE DRIVER VOH High-level output voltage IOUT = –200 mA, VOL Low-level output voltage IOUT = 200 mA 1.0 2.2 V IOUT = 10 mA 300 500 mV 0.9 1.5 (1) Low-level UVLO voltage IOUT = 50 mA, Output rise time (1) CLOAD = 1 nF Output fall time (1) Output peak current (1) V 35 ns CLOAD = 1 nF 35 ns CLOAD = 10 nF 1.0 A Ensured by design. Not production tested. (K ) = (2) VCC = 0 V V Gain constant. I IAC ´ (VVAO - 1.5V ) é(VVRMS )2 ´ I MOUT ù ë û Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B 5 UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 PACKAGE DESCRIPTION Q PACKAGE (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 GTDRV VCC CT SS RSET VSENSE ENA VREF 3 ISENSE CAOUT N/C MOUT IAC 5 2 1 20 19 18 4 17 6 16 7 15 8 14 9 10 11 12 13 CT SS N/C RSET VSENSE VAO VRMS NC VREF ENA GND PKLMT CAO ISENSE MOUT IAC VAO VRMS PKLMT GND N/C GTDRV VCC J, N and DW PACKAGES (TOP VIEW) N/C − No connection 6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 TERMINAL FUNCTIONS TERMINAL NAME PACKAGES I/O DESCRIPTION J/N/DW Q/L CAO 3 4 O Output of the wide bandwidth current amplifier and one of the inputs to the PWM duty-cycle comparator. The output signal generated by this amplifier commands the PWM to force the correct input current. The output can swing from 0.1 V to 7.5 V. CT 14 18 I Capacitor from CT to GND sets the PWM oscillator frequency. ENA 10 13 I A nominal voltage above 2.65 V on this pin allows the device to begin operating. Once operating, the device shuts off if this pin goes below 2.15 V nominal. GND 1 2 – All bypass and timing capacitors connected to GND should have leads as short and direct as possible. All voltages are measured with respect GND. O Output of the PWM is a 1.5-A peak totem-pole MOSFET gate driver on GTDRV. Use a series gate resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the GTDRV output is always expected when driving a capacitive load. GTDRV 16 20 IAC 6 8 I Current input to the multiplier, proportional to the instantaneous line voltage. This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAC) to MOUT, so this is the only multiplier input that should be used for sensing instantaneous line voltage. ISENSE 4 5 I Switch current sensing input. This is the inverting input to the current amplifier. This input and the non-inverting input MOUT remain functional down to and below GND. Care should be taken to avoid taking these inputs below –0.5 V, because they are protected with diodes to GND. MOUT 5 7 I/O Multiplier output and current sense plus. The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at MOUT. The cautions about taking ISENSE below –0.5 V also apply to MOUT. As the multiplier output is a current, this is a high-impedance input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject GND noise. IMOUT ≤ 2 × IAC PKLMT 2 3 I Peak limit. The threshold for PKLMT is 0.0 V. Connect this input to the negative voltage on the current sense resistor. Use a resistor to REF to offset the negative current sense signal up to GND. RSET 12 15 I Oscillator charging current and multiplier limit set. A resistor from RSET to ground programs oscillator charging current. 17 I Soft-start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to over 3 V by an internal 14-µA current source when both VCC becomes valid and the device is enabled. SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large capacitor from SS to GND, the reference to the voltage regulating amplifier rises slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discharge to ground and disable the PWM. SS 13 VAO 7 9 I Voltage amplifier output VCC 15 19 I Positive supply rail VREF 9 12 O Used to set the peak limit point and as an internal reference for various device functions. This voltage must be present for the device to operate. VRMS 8 10 I One of the inputs into the multiplier. This pin provides the input RMS voltage to the multiplier circuitry. VSENSE 11 14 I This pin provides the feedback from the output. This input goes into the voltage error amplifier and the output of the error amplifier is another of the inputs into the multiplier circuit. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B 7 UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 FUNCTIONAL DESCRIPTION The UC3854A and UC3854B family of products are designed as pin compatible upgrades to the industry standard UC3854 active power factor correction circuits. The circuit enhancements allow the user to eliminate in most cases several external components currently required to successfully apply the UC3854. In addition, linearity improvements to the multiply, square and divide circuitry optimizes overall system performance. Detailed descriptions of the circuit enhancements are provided below. For in-depth design applications reference data refer to the application notes, UC3854 Controlled Power Factor Correction Circuit Design (SLUA144) and UC3854A and UC3854B Advanced Power Factor Correction Control ICs (SLUA177). Multiply/Square and Divide -1 ö æ çK = ÷ V ø as the UC3854. The The UC3854A/B multiplier design maintains the same gain constant è relationship between the inputs and output current is given as: I MOUT = I IAC ´ (VVAO - 1.5V ) 2 K ´ (VVRMS ) (1) This is nearly the same as the UC3854, but circuit differences have improved the performance and application. The first difference is with the IAC input. The UC3854A/B regulated this pin voltage to the nominal 500 mV over the full operating temperature range, rather than the 6.0 V used on the UC3854. The low offset voltage eliminates the need for a line zero crossing compensating resistor to VREF from IAC that UC3854 designs require. The maximum current at high line into IAC should be limited to 250 µA for best performance. Therefore, if VVAC(max) = 270 V, RIAC = 270 ´1.414 = 1.53M W 250 m A (2) The VRMS pin linear operating range is improved with the UC3854A/B as well. The input range for VRMS extends from 0 V to 5.5 V. Since the UC3854A squaring circuit employs an analog multiplier, rather than a linear approximation, accuracy is improved, and discontinuities are eliminated. The external divider network connected to VRMS should produce 1.5 V at low line (85 VAC). This puts 4.77 V on VRMS at high line (270 VAC) which is well within its operating range. The voltage amplifier output forms the third input to the multiplier and is internally clamped to 6.0 V. This eliminated an external zener clamp often used in UC3854 designs. The offset voltage at this input to the multiplier has been raised on the UC3854A/B to 1.5 V. The multiplier output pin, which is also common to the current amplifier non-inverting input, has a –0.3 V to 5.0 V output range, compared to the –0.3 V to 2.5 V range of the UC3854. This improvement allows the UC3854A/B to be used in applications where the current sense signal amplitude is very large. 8 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 Voltage Amplifier The UC3854A/B voltage amplifier design is essentially similar to the UC3854 with two exceptions. The first is with the internal connection. The lower voltage reduces the amount of charge on the compensation capacitors, which provides improved recovery form large signal events, such as line dropouts, or power interruption. It also minimizes the dc current flowing through the feedback. The output of the voltage amplifier is also changed. In addition to a 6.0-V temperature compensated clamp, the output short circuit current has been lowered to 2 mA typical, and an active pull down has replaced the passive pull down of the UC3854. Current Amplifier The current amplifier for an average current PFC controller needs a low offset voltage in order to minimize ac line current distortion. With this in mind, the UC3854A/B current amplifier has improved the input offset voltage from ±4 mV to 0 V to ±3 mV. The negative offset of the UC3854A/B assures that the PWM circuit will not drive the MOSFET is the current command is zero (both current amplifier inputs zero.) Previous designs required an external offset cancellation network to implement this key feature. The bandwidth of the current amplifier has been improved as well to 5 MHz typical. While this is not generally an issue at 50 Hz or 60 Hz inputs, it is essential for 400 Hz input avionics applications. Miscellaneous Several other important enhancements have been implemented in the UC3854A/B. AVCC supply voltage clamp at 20 V allows the controller to be current fed if desired. The lower startup supply current (250 µA typical), substantially reduces the power requirements of an offline startup resistor. The 10.5 V/10 V UVLO option (UC3854B) enables the controller to be powered off of an auxiliary 12-V supply. The VREF GOOD comparator assures that the MOSFET driver output remains low if the supply of the 7.5 V reference are not yet up. This improvement eliminates the need for external Schottky diodes on the PKLMT and Mult Out pins that some UC3854 designs require. The propagation delay of the disable feature has been improved to 300 ns typical. This delay was proportional to the size of the VREF capacitor on the UC3854, and is typically several orders of magnitude slower. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B 9 UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 TYPICAL CHARACTERISTICS GATE DRIVE TIMING vs LOAD CAPACITANCE 800 GATE DRIVE MAXIMUM DUTY CYCLE vs OSCILLATOR CHARGING RESISTANCE 100 700 95 Fall Time Duty Cycle − % t− Time − ns 600 500 400 Rise Time 300 90 85 80 200 75 100 0 0 0.01 0.02 0.03 0.04 70 1000 0.05 CLOAD − Load Capacitance − µF Figure 1. Figure 2. MULTIPLIER GAIN CONSTANT vs SUPPLY CURRENT 1.20 MULTIPLIER GAIN CONSTANT vs SUPPLY CURRENT 1.20 VA Out = 3.5 V VA Out = 5 V 1.16 1.12 1.12 VRMS = 1.5 V K− Multiplier Gain Constant− V K− Multiplier Gain Constant− V 1.16 1.08 VRMS = 5 V 1.04 1.00 0.96 0.92 VRMS = 3 V 0.88 VRMS = 1.5 V 1.08 1.04 1.00 0.96 VRMS = 5 V 0.92 VRMS = 1.5 V 0.88 0.84 0.84 0.80 0.80 0 10 10 k 100 k RSET − Oscillator Charging Resistance − Ω 50 100 150 IAC − Supply Current − µA Figure 3. Submit Documentation Feedback 200 250 0 50 100 150 IAC − Supply Current − µA Figure 4. 200 250 Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B UC1854A UC2854A, UC2854B UC3854A, UC3854B www.ti.com SLUS329E – MONTH 2003 – REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) 120 PHASE 120 −90 80 −45 60 −0 40 20 Phase − ° 100 0 120 PHASE 100 Gain − dB Gain − dB VOLTAGE AMPLIFIER GAIN vs FREQUENCY 100 80 80 60 60 40 40 20 20 0 0 Phase − ° 140 CURRENT AMPLIFIER GAIN vs FREQUENCY −20 GAIN fCO = 5.992 MHz −40 −60 10 k 100 k 1M −20 100 10 M 1000 10 k GAIN 100 k 1M −20 10 M f − Frequency − Hz f − Frequency − Hz Figure 5. Figure 6. OSCILLATOR FREQUENCY vs LIMIT SET RESISTANCE AND TIMING CAPACITANCE 1k fOSC − Oscillator Frequency − kHz 200 pF 100 pF 1 nF 100 500 pF 3 nF 10 nF 10 5 nF 2 nF 0 1 10 100 RSET − Multiplier Limit Set Resistance − kΩ Figure 7. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B 11 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-9326102M2A OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 5962-9326102MEA ACTIVE CDIP J 16 1 TBD Call TI Call TI -55 to 125 5962-9326102ME A UC1854BJ/883B UC1854BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1854BJ UC1854BJ883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9326102ME A UC1854BJ/883B UC1854BL OBSOLETE TO/SOT L 20 TBD Call TI Call TI -55 to 125 UC1854BL883B OBSOLETE TO/SOT L 20 TBD Call TI Call TI -55 to 125 UC2854ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854ADW UC2854ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854ADW UC2854ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854ADW UC2854ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854ADW UC2854AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854AN UC2854ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854AN UC2854BDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854BDW UC2854BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854BDW UC2854BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854BDW UC2854BDWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2854BDW UC2854BN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854BN Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UC2854BNG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2854BN UC2854BQ ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UC2854BQ UC2854BQG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UC2854BQ UC2854J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -40 to 85 UC2854J UC3854ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854ADW UC3854ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854ADW UC3854ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854ADW UC3854ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854ADW UC3854AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854AN UC3854ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854AN UC3854BDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854BDW UC3854BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854BDW UC3854BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854BDW UC3854BDWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3854BDW UC3854BN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854BN UC3854BNG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3854BN UC3854BQ OBSOLETE UTR 20 TBD Call TI Call TI 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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