TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 DirectPath™ 25-mW Headphone Amplifier With Programmable-Fixed Gain Check for Samples: TPA6139A2 FEATURES DESCRIPTION • The TPA6139A2PW is a 25mW Pop-Free stereo Head Phone driver designed to reduce component count, board space and cost. It is ideal for single supply electronics where size and cost are critical design parameters. 1 23 • • • • • • • • DirectPath™ – Eliminates Pop/Clicks – Eliminates Output DC-Blocking Capacitors – 3 V to 3.6 V Supply voltage Low Noise and THD – SNR > 105 dB at –1x Gain – Typical Vn < 15 μVms 20-20kHz at –1x Gain – THD+N < 0.003% at 10kΩ Load and –1x Gain 25 mW into 600 Ω Load 2 Vrms Output Voltage into 5kΩ Load Single Ended Input and Output Programmable Gain Select Reduces Component Count – 13x Gain Values Active Mute With More Than 80dB Attenuation Short Circuit and Thermal Protection ±8kV HBM ESD Protected Outputs Designed using TI’s patented DIRECTPATH™ technology which integrates a charge pump to generate a negative supply rail that provides a clean, pop-free ground biased output. The TPA6139A2 is capable of driving 25mW into 32Ω and 2Vms into a 600Ω load. DIRECTPATH also allows the removal of the costly output DC-blocking capacitors. The device has fixed gain single ended inputs with a gain select pin. Using a single resistor on this pin, the designer can choose from 13 internal programmable gain settings to match the line driver with the Codec output level. It also reduces the component count and board space. Headphone outputs have ±8kV HBM ESD protection enabling a simple ESD protection circuit. The TPA6139A2 has built-in active mute control with more that 80dB attenuation for pop-free mute on/off control. APPLICATIONS • • • • The TPA6139A2 does not require a power supply greater than 3.3V to generate its 25mW, nor does it require a split rail power supply. PDP / LCD TV Blu-ray Disc™, DVD Players Mini/Micro Combo Systems Soundcards The TPA6139A2 is available in a 14-pin TSSOP and a 16-pin QFN. For a pin compatible 2vrms line driver see DRV612. – + DAC Headphone Programmable Gain SOC DAC -1x to -10x LEFT TPA 6139A2 – RIGHT + 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath, DIRECTPATH are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION PIN ASSIGNMENT The TPA6139A2 is available in the: • 14-pin TSSOP package (PW) or • 16-pin QFN package (RGT) 11 5 VSS VDD 10 6 CN CP 9 7 NC NC 8 –IN_R GND 13 MUTE 1 12 OUT_R GND 2 11 GAIN GND 3 10 GND MUTE 4 9 VDD 8 4 OUT_L CP GAIN 12 NC GND 14 3 7 13 NC OUT_R NC OUT_L 15 2 6 14 CN –IN_R 5 –IN_L VSS 1 –IN_L RGT PACKAGE QFN (TOP VIEW) 16 PW PACKAGE TSSOP (TOP VIEW) PIN FUNCTIONS FUNCTION (1) PIN DESCRIPTION NAME PW NO. RGT NO. -IN_L 1 16 I Negative input, left channel OUT_L 2 1 O Output, left channel 3, 11 2, 3, 10 P Ground MUTE 4 4 I MUTE, active low VSS 5 5 O Change Pump negative supply voltage CN 6 6 I/O Charge Pump flying capacitor negative connection NC 7, 8 7. 14, 15 CP 9 8 I/O VDD 10 9 P Supply voltage, connect to positive supply GAIN 12 11 I Gain set programming pin; connect a resistor to ground. See Table 1 for recommended resistor values OUT_R 13 12 O Output, right channel -IN_R 14 13 I Negative input, right channel GND (1) 2 No internal connection Charge Pump flying capacitor positive connection I = input, O = output, P = power Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 SYSTEM BLOCK DIAGRAM Current Limit Left GAIN Control De Pop Current Limit Right Charge Pump Thermal Limit Power Management ORDERING INFORMATION (1) (1) TA PACKAGE DESCRIPTION –40°C to 85°C TPA6139A2PW 14-pin TSSOP –40°C to 85°C TPA6139A2RGT 16-pin QFN For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. THERMAL INFORMATION THERMAL METRIC (1) TPA6139A2 PW (14-Pin) TPA6139A2 RGT (16-Pin) θJA Junction-to-ambient thermal resistance 130 52 θJCtop Junction-to-case (top) thermal resistance 49 71 θJB Junction-to-board thermal resistance 63 26 ψJT Junction-to-top characterization parameter 3.6 3.0 ψJB Junction-to-board characterization parameter 62 26 θJCbot Junction-to-case (bottom) thermal resistance N/A 9.8 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 3 TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD to GND Input voltage, VI MUTE to GND VALUE UNIT –0.3 to 4 V VSS–0.3 to VDD+0.3 V –0.3 to VDD+0.3 V Maximum operating junction temperature range, TJ –40 to 150 °C Storage temperature –40 to 150 °C Lead temperature ESD Protection – HBM (1) 260 °C OUT_L, OUT_R 8 kV All other pins 2 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range unless otherwise noted MIN NOM MAX Supply voltage DC supply voltage 3.0 3.3 3.6 V VIL Low-level input voltage MUTE 38 40 43 %PVDD VIH High-level input voltage MUTE 57 60 66 %PVDD TA Free-air temperature –40 25 85 °C VDD RL 4 5 Submit Documentation Feedback UNIT kΩ Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS VDD = 3.3V, RLoad = 32Ω, TA = 25°C, Charge pump: CCP = 1.0 μF (unless otherwise noted) PARAMETER TEST CONDITIONS |VOS| Output offset voltage PSRR Power-supply rejection ratio VOH High-level output voltage VDD = 3.3 V VOL Low-level output voltage VDD = 3.3 V Vuvp_on PVDD, under voltage detection MIN VDD = 3.3 V, input ac-coupled 70 TYP MAX 0.5 1 80 UNIT mV dB 3.1 V –3.05 2.8 V V Vuvp_hysteresis PVDD, under voltage detection, hysteresis 200 mV Fcp Charge pump switching frequency 350 kHz |IIH| High-level input current, MUTE VDD = 3.3 V, VIH = VDD 1 |IIL| Low-level input current, MUTE VDD = 3.3 V, VIL = 0 V 1 I (VDD) Supply current, no load VDD, MUTE = 3.3 V Supply current, MUTED VDD = 3.3 V, MUTE = GND Tsd Thermal shutdown Thermal shutdown hysteresis PO Output Power, outputs in phase VO Output Voltage, outputs in phase µA µA 25 mA 25 mA 150 °C 15 °C THD+N = 1%, f = 1kHz, 32Ω load 25 mW THD+N = 1%, f = 1kHz, 32Ω load 0.9 THD+N = 1%, f = 1kHz, 600Ω load 2.0 Vrms Total Harmonic distortion plus noise f = 1kHz, 32Ω load, Po= 25mW, -1x gain 0.03% Total Harmonic distortion plus noise f = 1kHz, 10kΩload, Vo=2 Vrms, -1x gain 0.005% ΔAV Gain matching Between left and right channels ZO Output impedance when muted MUTE = GND Input to output attenuation when muted MUTE = GND 80 dB Signal to noise ratio A-weighted, AES17 filter, 1Vrms ref 32Ω load, -1x gain 99 dB Signal to noise ratio A-weighted, AES17 filter, 2Vrms ref 600Ω load, -1x gain 105 Noise voltage A-weighted, AES17 filter, Gain=-2x 12 THD+N THD+N SNR Vn Slew rate Gbw Unity Gain bandwidth Crosstalk Channel to channel Vincm_pos Vincm_neg Ilim Output current limit f = 1kHz, Rload = 32Ω, Po= 25mW 0.25 dB 1 Ω dB µV 4.5 V/µs 8 MHz –85 dB Positive Common mode input voltage +2.0 V Negative Common mode input voltage –2.0 60 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 V mA 5 TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com PROGRAMMABLE GAIN SETTINGS VDD = 3.3 V, Rload = 32 kΩ, TA = 25°C, Charge pump:= CCP 1 µF, CIN = 1.0 µF, 1 x gain select (unless otherwise noted) (1) PARAMETER R_Tol Gain programming resistor tolerance ΔAV Gain matching TEST CONDITIONS 6 MIN TYP MAX UNIT 2% Between left and right channels Gain step tolerance (1) TPA6139A2 0.25 dB 0.10 dB Gain steps Gain resistor 2% tolerance 249k or higher 82k0 49k2 35k1 27k3 20k5 15k4 11k5 9k09 7k50 6k19 5k11 3k90 –2.0 –1.0 –1.5 –2.3 –2.5 –3.0 –3.5 –4.0 –5.0 –5.6 –6.4 –8.3 –10.0 Input impedance Gain resistor 2% tolerance 249k or higher 82k0 49k2 35k1 27k3 20k5 15k4 11k5 9k09 7k50 6k19 5k11 3k90 37 55 44 33 31 28 24 22 18 17 15 12 10.0 V/V kΩ If pin 12, GAIN, is left floating an internal pull-up sets the gain to –2.0x Gain setting is latched during power-up Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS, LINE DRIVER VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 10 µF, Gain Step = –2V/V (unless otherwise noted) THD+N vs OUTPUT VOLTAGE 3.3 V, 100 kΩ, 1 kHz THD+N vs OUTPUT VOLTAGE 3.3 V, 600 Ω load, 1 kHz 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 5 In Phase 2 1 Out of Phase 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1m 2m 5m 10m 20m PO - Output Power - W 50m 100m 5 2 32R load 1 0.5 600R load 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 200m 300m Figure 1. 500m 700m 1 VO - Output Voltage - V 2 3 Figure 2. CHANNEL SEPARATION 3.3 V, 5 kΩ load, 2 Vrms, Blue L to R, Red R to L FFT +0 –10 25 mW into 32R -10 –20 -20 –30 -30 –40 Attenuation - dBV Attenuation - dBr +0 -40 -50 -60 -70 Left to Right –60 –70 –80 –90 –100 -80 –110 -90 Right to Left -100 –50 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k –120 –130 0 Figure 3. 5k 10k 15k f - Frequency - Hz 20k Figure 4. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 7 TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS, LINE DRIVER (continued) VDD = 3.3 V, TA = 25°C, RL = 2.5 kΩ, CPUMP = C(VSS) = 10 µF, Gain Step = –2V/V (unless otherwise noted) Gain vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 10 20 5 THD - Total Harmonic Distortion - % 22 18 16 Gain - dBr 14 12 10 8 6 4 2 0 -2 20 8 2 1 0.5 0.2 -10x gain 0.1 -4x gain 0.05 0.02 0.01 -2x gain 0.005 0.002 0.001 100 200 1k 2k 10k 20k f - Frequency - Hz 100k 200k 20 50 100 200 500 1k 2k f - Frequency - Hz Figure 5. Figure 6. MUTE TO UN-MUTE UN-MUTE TO MUTE Figure 7. Figure 8. Submit Documentation Feedback 5k 10k 20k Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 9 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value, and a mute circuit is needed during power up to minimize click and pop. The output capacitor and mute circuit consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal. Conventional solution 9-12 V VDD + Mute Circuit Co + + OPAMP Output VDD/2 GND MUTE 3.3 V DirectPath TPA 6139 A 2 Solution - TPA6139A2 Output VDD GND VSS MUTE Figure 9. Conventional and DirectPath Line Driver The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 9 illustrate the ground-referenced line-driver architecture. This is the architecture of the TPA6139A2. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 9 TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com COMPONENT SELECTION Charge Pump The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The VSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1μF is typical. Capacitor values that are smaller than 1μF cannot be recommended as it limits the negative voltage swing in low impedance loads. Decoupling Capacitors The TPA6139A2 is a DirectPath™ amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1μF, placed as close as possible to the device VDD leads works best. Placing this decoupling capacitor close to the TPA6139A2 is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier also helps, but it is not required in most applications because of the high PSRR of this device. Gain-Setting The gain setting is programmed with the GAIN pin individually for line driver and headphone section. Gain setting is latched when the MUTE pin is set high. Table 1 lists the gain settings. The default gain with the gain-set pin left open is –2x. Table 1. Gain Settings Gain_set RESISTOR GAIN GAIN (dB) INPUT RESISTANCE No connect –2.0x 6.0 37k 82k0 –1.0x 0.0 55k 49k2 –1.5x 3.5 44k 35k1 –2.3x 7.2 33k 27k3 –2.5x 8.0 31k 20k5 –3.0x 9.5 28k 15k4 –3.5x 10.9 24k 11k5 –4.0x 12.0 22k 9k09 –5.0x 14.0 18k 7k50 –5.6x 15.0 17k 6k19 –6.4x 16.1 15k 5k11 –8.3x 18.4 12k 3k90 –10x 20.0 10k Internal Under Voltage Detection The TPA6139A2 contains an internal precision band gap reference voltage and a comparator used to monitor the supply voltage, VDD. The internal VDD monitor is set at 2.8V with 200mV hysteresis. 1.25 V Bandgap AMP Enable VDD 10 Comparator Internal VDD 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the TPA6139A2. These capacitors block the dc portion of the audio source and allow the TPA6139A2 inputs to be properly biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the DC-offset voltage at the output. These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input resistor chosen from Table 1. Then the frequency and/or capacitance can be determined when one of the two values is given. 1 1 fc IN + or C IN + 2p fc R 2p RIN C IN IN IN (1) For a fixed cutoff frequency of 2Hz the size of the input capacitance is shown in the table below with the capacitors rounded up to nearest E6 values. For 20Hz cutoff simply divide the capacitor values with 10; e.g., for 1x gain, 150nF is needed. Table 2. Input Capacitor for Different Gain and Cutoff Gain_set RESISTOR GAIN Gain (dB) INPUT RESISTANCE 2 Hz Cutoff 249k –2.0x 6.0 37k 2.2 µF 82k0 –1.0x 0.0 55k 1.5 µF 49k2 –1.5x 3.5 44k 2.2 µF 35k1 –2.3x 7.2 33k 3.3 µF 27k3 –2.5x 8.0 31k 3.3 µF 20k5 –3.0x 9.5 28k 3.3 µF 15k4 –3.5x 10.9 24k 3.3 µF 11k5 –4.0x 12.0 22k 4.7 µF 9k09 –5.0x 14.0 18k 4.7 µF 7k50 –5.6x 15.0 17k 4.7 µF 6k19 –6.4x 16.1 15k 6.8 µF 5k11 –8.3x 18.4 12k 6.8 µF 3k90 –10x 20.0 10k 10 µF Pop-Free Power Up Pop-free power up is ensured by keeping the MUTE low during power supply ramp up and down. The pin should be kept low until the input AC-coupling capacitors are fully charged before asserting the MUTE pin high to precharge the ac-coupling; and, pop-less power-up is achieved. Figure 10 illustrates the preferred sequence. Supply Supply ramp MUTE Time for ac-coupling capasitors to charge Figure 10. Power-Up Sequence Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 11 TPA6139A2 SLOS700B – JANUARY 2011 – REVISED JUNE 2012 www.ti.com CAPACITIVE LOAD The TPA6139A2 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be accepted by adding a series resistor of 47 Ω or larger for the line driver output. LAYOUT RECOMMENDATIONS A proposed layout for the TPA6139A2 can be seen in the TPA6139A2EVM User's Guide (SLOU248), and the Gerber files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/TPA6139A2evm.html. To access this information, open the TPA6139A2 product folder and look in the Tools and Software folder. Ground traces are recommended to be routed as a star ground to minimize hum interference. VDD, VSS decoupling capacitors and the charge pump capacitors should be connected with short traces. PIN COMPATIBLE WITH THE DRV612 The TPA6139A2 stereo Headphone amplifier is pin compatible with the DRV612 . A single PCB layout can therefore be used with stuffing options for different board configurations. APPLICATION CIRCUIT U11 1 C11 2.2 mF OUT_LEFT -IN_L 2 OUT_L 3 GND 4 MUTE 2 5 VSS 1 mF 6 CN 7 NC MUTE 1 C1 2 1 GND 1 C12 -IN_R 14 OUT_R 13 GAIN 12 1 GND 11 R11 VDD 10 1 CP 9 C15 NC 8 TPA6139A2PW 2 IN_LEFT 2 IN_RIGHT 2.2 mF OUT_RIGHT 2 49 kW 2 1 mF GND +3.3V 1 C14 uF1 13 GND 10 MUTE VDD 9 CP C25 1 mF 1 1 +3.3V 1 5 2 1 2 GND 2 GND OUT_RIGHT 2 TPA6139A2RGT GAIN C23 1 mF IN_RIGHT -IN_R NC GND 11 8 4 12 VSS MUTE 3 1 2.2 mF C22 OUT_R OUT_L NC GND 2 7 1 OUT_LEFT NC -IN_L U21 14 2 15 1 2.2 mF CN C21 6 2 16 IN_LEFT GND GND R21 49 kW C24 1 mF GND Figure 11. Single Ended Input and Output, Gain Set to –1.5x 12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 TPA6139A2 www.ti.com SLOS700B – JANUARY 2011 – REVISED JUNE 2012 REVISION HISTORY NOTE: Page numbers in current version may differ from previous versions. Changes from Original (January 2011) to Revision A Page • Changed "2.5-mW" to "25-mW" in Title line and added revision A - May 2011 pub date to Header infomation ................. 1 • Changed pin assignment figures to match package outline drawings ................................................................................. 2 • Changed conditions statement from "RIN = 10 kΩ, Rfb = 20 kΩ" to "Step = –2V/V" for TYP CHARA, LINE DRIVER section ................................................................................................................................................................................... 7 • Changed conditions statement from "RIN = 10 kΩ, Rfb = 20 kΩ" to "Step = –2V/V" for TYP CHARA, LINE DRIVER section ................................................................................................................................................................................... 8 Changes from Revision A (May 2011) to Revision B • Page Changed the RGT package From: Preview To: Production ................................................................................................. 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s) :TPA6139A2 13 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPA6139A2PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6139A2PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6139A2RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6139A2RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPA6139A2PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPA6139A2RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPA6139A2RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6139A2PWR TSSOP PW 14 2000 367.0 367.0 35.0 TPA6139A2RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPA6139A2RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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