SST SST25VF040-20-4I-S2AE

2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
FEATURES:
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• 20 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
• Packages Available
– 8-lead SOIC 150 mil body width
for SST25VF020
– 8-lead SOIC 200 mil body width
for SST25VF040
– 8-contact WSON (5mm x 6mm)
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package
occupying less board space and ultimately lowering total
system costs. SST25VF020/040 SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS SuperFlash Technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches.
The SST25VF020/040 devices significantly improve performance, while lowering power consumption. The total
energy consumed is a function of the applied voltage, cur-
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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1
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash memory technologies. The
SST25VF020/040 devices operate with a single 2.7-3.6V
power supply.
The SST25VF020 devices are offered in an 8-lead SOIC
150 mil body width (SA) package. The SST25VF040
devices are offered in an 8-lead SOIC 200 mil body width
(S2A) package. All densities are offered in the 8-contact
WSON package. See Figure 1 for the pin assignments.
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
1231 B1.0
CE#
SCK
SI
SO
©2004 Silicon Storage Technology, Inc.
WP#
HOLD#
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
PIN DESCRIPTION
8
VDD
7
HOLD#
3
6
SCK
4
5
SI
CE#
1
SO
2
CE#
1
8
VDD
SO
2
7
HOLD#
WP#
3
6
SCK
WP#
VSS
4
5
SI
VSS
Top View
Top View
1231 08-wson P2.0
1231 08-soic P1.0
8-LEAD SOIC
8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI
Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the device.
VDD
Power Supply
To provide power supply (2.7-3.6V).
VSS
Ground
T1.0 1231
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
PRODUCT IDENTIFICATION
DEVICE OPERATION
The SST25VF020/040 is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
00000H
BFH
SST25VF020
00001H
43H
SST25VF040
00001H
44H
Manufacturer’s ID
Device ID
The SST25VF020/040 supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state
of the SCK signal when the bus master is in Stand-by
mode and no data is being transferred. The SCK signal is
low for Mode 0 and SCK signal is high for Mode 3. For both
modes, the Serial Data In (SI) is sampled at the rising edge
of the SCK clock signal and the Serial Data Output (SO) is
driven after the falling edge of the SCK clock signal.
T2.0 1231
MEMORY ORGANIZATION
The SST25VF020/040 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay blocks.
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
1231 F02.1
FIGURE 2: SPI PROTOCOL
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Hold Operation
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
17 for Hold timing.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
SCK
HOLD#
Active
Hold
Active
Hold
Active
1231 F03.0
FIGURE 3: HOLD CONDITION WAVEFORM
Write Protection
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUSREGISTER (WRSR) INSTRUCTION
SST25VF020/040 provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See
Table 5 for Block-Protection description.
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
T3.0 1231
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down function of the BPL bit is disabled.
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Status Register
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 4 describes the function of each bit in the software
status register.
The software status register provides status on whether the
flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See Table 5)
1
R/W
3
BP1
Indicate current level of block write protection (See Table 5)
1
R/W
4:5
RES
Reserved for future use
0
N/A
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
Bit
Name
Function
0
BUSY
1
T4.0 1231
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming
reached its highest memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
©2004 Silicon Storage Technology, Inc.
S71231-04-000
6
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Block Protection (BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 5, to be software protected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (VIH), the BPL bit has no effect and
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
TABLE 5: SOFTWARE STATUS REGISTER BLOCK PROTECTION1
Status
Register
Bit
Protected Memory Area
Protection Level
BP1
BP0
2 Mbit
4 Mbit
0
0
0
None
None
1 (1/4 Memory Array)
0
1
030000H-03FFFFH
060000H-07FFFFH
2 (1/2 Memory Array)
1
0
020000H-03FFFFH
040000H-07FFFFH
3 (Full Memory Array)
1
1
000000H-03FFFFH
000000H-07FFFFH
T5.0 1231
1. Default at power-up for BP1 and BP0 is ‘11’.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Instructions
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF020/040. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
TABLE 6: DEVICE OPERATION INSTRUCTIONS1
Bus Cycle2
Type/Operation3,4
1
2
3
4
5
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT
Read
03H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
X
DOUT
Sector-Erase5,6
20H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
-
-
Block-Erase5,7
52H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
-
-
Chip-Erase6
60H
Hi-Z
-
-
-
-
-
-
-
-
Byte-Program6
02H
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
Auto Address Increment (AAI) Program6,8
AFH
Hi-Z
A23-A16
Hi-Z
A15-A8
Hi-Z
A7-A0
Hi-Z
DIN
Hi-Z
Read-Status-Register (RDSR)
05H
Hi-Z
X
DOUT
-
Note9
-
Note9
-
Note9
Enable-Write-Status-Register (EWSR)10
50H
Hi-Z
-
-
-
-
-
-
-
-
Write-Status-Register (WRSR)10
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
Cycle
Write-Enable (WREN)
06H
Hi-Z
-
-
-
-
-
-
-
-
Write-Disable (WRDI)
04H
Hi-Z
-
-
-
-
-
-
-
-
90H or
ABH
Hi-Z
00H
Hi-Z
00H
Hi-Z
ID Addr11
Hi-Z
X
DOUT12
Read-ID
T6.0 1231
1. AMS = Most Significant Address
AMS = A17 for SST25VF020 and A18 for SST25VF040
Address bits above the most significant bit of each density can be VIL or VIH
2. One bus cycle is eight clock periods.
3. Operation: SIN = Serial In, SOUT = Serial Out
4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
must be executed.
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and Device
ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 43H for SST25VF020 and 44H for SST25VF040
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Read
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction outputs the data starting from the
specified address location. The data output stream is continuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47
48
55 56
63 64
70
MODE 0
ADD.
03
SI
ADD.
ADD.
MSB
MSB
N
DOUT
HIGH IMPEDANCE
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1231 F04.1
FIGURE 4: READ SEQUENCE
Byte-Program
Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 5 for the
Byte-Program sequence.
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
MODE 0
02
SI
MSB
SO
ADD.
ADD.
MSB
ADD.
DIN
MSB
LSB
HIGH IMPEDANCE
1231 F05.1
FIGURE 5: BYTE-PROGRAM SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Auto Address Increment (AAI) Program
status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the device completes programming byte, the next sequential address may
be program, enter the 8-bit command, AFH, followed by the
data to be programmed. When the last desired byte had
been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to
ensure the device completes programming. See Figure 6
for AAI programming sequence.
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total programming time when the entire memory array is to be programmed. An AAI program instruction pointing to a
protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when initiating an AAI program instruction.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI program instruction
is initiated by executing an 8-bit command, AFH, followed
by address bits [A23-A0]. Following the addresses, the data
is input sequentially from MSB (bit 7) to LSB (bit 0). CE#
must be driven high before the AAI program instruction is
executed. The user must poll the BUSY bit in the software
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0).
TBP
TBP
CE#
MODE 3
SCK
SI
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32 33 34 35 36 37 38 39
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1
MODE 0
AF
A[23:16] A[15:8]
Data Byte 1
A[7:0]
Data Byte 2
AF
TBP
CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI
AF
Last Data Byte
04
Write Disable (WRDI)
Instruction to terminate
AAI Operation
05
Read Status Register (RDSR)
Instruction to verify end of
AAI Operation
DOUT
SO
1231 F06.1
FIGURE 6: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
10
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to determine the
sector address (SAX), remaining address bits can be VIL or
VIH. CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status
register or wait TSE for the completion of the internal selftimed Sector-Erase cycle. See Figure 7 for the SectorErase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADD.
20
SI
MSB
ADD.
ADD.
MSB
HIGH IMPEDANCE
SO
1231 F07.1
FIGURE 7: SECTOR-ERASE SEQUENCE
Block-Erase
address bits [A23-A0]. Address bits [AMS-A15] (AMS = Most
significant address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed BlockErase cycle. See Figure 8 for the Block-Erase sequence.
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H, followed by
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADD.
52
SI
MSB
SO
ADD.
ADD.
MSB
HIGH IMPEDANCE
1231 F08.1
FIGURE 8: BLOCK-ERASE SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Chip-Erase
by executing an 8-bit command, 60H. CE# must be driven
high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait TCE for
the completion of the internal self-timed Chip-Erase cycle.
See Figure 9 for the Chip-Erase sequence.
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60
SI
MSB
HIGH IMPEDANCE
SO
1231 F09.1
FIGURE 9: CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 10 for the RDSR instruction sequence.
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
SI
05
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
1231 F10.1
FIGURE 10: READ-STATUS-REGISTER (RDSR) SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
12
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
HIGH IMPEDANCE
SO
1231 F11.1
FIGURE 11: WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
1231 F12.1
FIGURE 12: WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-WriteStatus-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write©2004 Silicon Storage Technology, Inc.
S71231-04-000
13
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
When WP# is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or
WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the
BP0, BP1, and BPL bit in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 and BP1 bit
at the same time. See Table 3 for a summary description of
WP# and BPL functions. CE# must be driven low before
the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 13 for EWSR and WRSR instruction
sequences.
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction
with the Enable-Write-Status-Register (EWSR) instruction
to write new values to the BP1, BP0, and BPL bits of the
status register. The Write-Status-Register instruction must
be executed immediately after the execution of the EnableWrite-Status-Register instruction (very next instruction bus
cycle). This two-step instruction sequence of the EWSR
instruction followed by the WRSR instruction works like
SDP (software data protection) command structure which
prevents any accidental alteration of the status register values. The Write-Status-Register instruction will be ignored
when WP# is low and BPL bit is set to “1”. When the WP#
is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
MODE 3
MODE 0
01
50
SI
MSB
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
1231 F13.1
FIGURE 13: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Read-ID
address 00000H and the device ID is located in address
00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between
address 00000H and 00001H until terminated by a low to
high transition on CE#.
The Read-ID instruction identifies the devices as
SST25VF020/040 and manufacturer as SST. The device
information can be read from executing an 8-bit command,
90H or ABH, followed by address bits [A23-A0]. Following
the Read-ID instruction, the manufacturer’s ID is located in
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
90 or AB
SI
00
MSB
00
ADD1
MSB
HIGH IMPEDANCE
SO
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1231 F14.1
FIGURE 14: READ-ID SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
15
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
Industrial
-40°C to +85°C
2.7-3.6V
See Figures 19 and 20
Extended
-20°C to +85°C
2.7-3.6V
Commercial
TABLE 7: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol
Parameter
Min
Max
Units
Test Conditions
IDDR
Read Current
10
mA
CE#=0.1 VDD/0.9 [email protected] MHz, SO=open
IDDW
Program and Erase Current
30
mA
CE#=VDD
ISB
Standby Current
15
µA
CE#=VDD, VIN=VDD or VSS
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
1
µA
VOUT=GND to VDD, VDD=VDD Max
0.8
V
VDD=VDD Min
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
0.7 VDD
VDD-0.2
T7.0 1231
TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
VDD Min to Read Operation
10
µs
VDD Min to Write Operation
10
µs
TPU-WRITE
1
T8.0 1231
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
COUT1
Output Pin Capacitance
CIN
1
Input Capacitance
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
T9.0 1231
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71231-04-000
16
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
TABLE 10: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
TDR
1
Data Retention
ILTH1
Latch Up
JEDEC Standard 78
T10.0 1231
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: AC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol
Parameter
FCLK
Serial Clock Frequency
TSCKH
Serial Clock High Time
20
TSCKL
Serial Clock Low Time
20
TSCKR
Serial Clock Rise Time
TSCKF
Serial Clock Fall Time
TCES1
CE# Active Setup Time
20
ns
TCEH1
CE# Active Hold Time
20
ns
TCHS1
CE# Not Active Setup Time
10
ns
TCHH
1
Min
Max
Units
20
MHz
ns
ns
5
5
ns
ns
CE# Not Active Hold Time
10
ns
TCPH
CE# High Time
100
ns
TCHZ
CE# High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
ns
TDS
Data In Setup Time
4
ns
TDH
Data In Hold Time
5
ns
THLS
HOLD# Low Setup Time
10
ns
THHS
HOLD# High Setup Time
10
ns
THLH
HOLD# Low Hold Time
15
ns
THHH
HOLD# High Hold Time
10
ns
THZ
HOLD# Low to High-Z Output
20
ns
TLZ
HOLD# High to Low-Z Output
20
ns
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
23
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
100
ms
TBP
Byte-Program
20
µs
20
0
ns
ns
T11.2 1231
1. Relative to SCK.
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
TCPH
CE#
TCHH
TCEH
TSCKF
TCES
TCHS
SCK
TDS
SI
SO
TDH
TSCKR
MSB
LSB
HIGH-Z
HIGH-Z
1231 F15.0
FIGURE 15: SERIAL INPUT TIMING DIAGRAM
CE#
TSCKH
TSCKL
SCK
TOH
TCHZ
TCLZ
SO
LSB
MSB
TV
SI
1231 F16.0
FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
CE#
THHH
THHS
THLS
SCK
THLH
THZ
TLZ
SO
SI
HOLD#
1231 F17.0
FIGURE 17: HOLD TIMING DIAGRAM
VDD
VDD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
1231 F18.0
FIGURE 18: POWER-UP TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71231-04-000
19
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
VIHT
VHT
INPUT
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
1231 F19.1
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
1231 F20.0
FIGURE 20: A TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
20
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
SST25VFXXX - XXX
Suffix1
-
XX
Suffix2
-
XXX
Environmental Attribute
E = non-Pb
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC 150 mil body width
S2 = SOIC 200 mil body width
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
20 = 20 MHz
Device Density
020 = 2 Mbit
040 = 4 Mbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash memory
Valid combinations for SST25VF020
SST25VF020-20-4C-SA
SST25VF020-20-4C-SAE
SST25VF020-20-4C-QA
SST25VF020-20-4C-QAE
SST25VF020-20-4I-SA
SST25VF020-20-4I-SAE
SST25VF020-20-4I-QA
SST25VF020-20-4I-QAE
SST25VF020-20-4E-SA
SST25VF020-20-4E-SAE
SST25VF020-20-4E-QA
SST25VF020-20-4E-QAE
Valid combinations for SST25VF040
SST25VF040-20-4C-S2A
SST25VF040-20-4C-S2AE
SST25VF040-20-4C-QA
SST25VF040-20-4C-QAE
SST25VF040-20-4I-S2A
SST25VF040-20-4I-S2AE
SST25VF040-20-4I-QA
SST25VF040-20-4I-QAE
SST25VF040-20-4E-S2A
SST25VF040-20-4E-S2AE
SST25VF040-20-4E-QA
SST25VF040-20-4E-QAE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2004 Silicon Storage Technology, Inc.
S71231-04-000
21
6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
PACKAGING DIAGRAMS
Pin #1
Identifier
TOP VIEW
SIDE VIEW
7˚
4 places
0.51
0.33
5.0
4.8
1.27 BSC
END VIEW
4.00
3.80
6.20
5.80
45˚
0.25
0.10
1.75
1.35
7˚
4 places
0.25
0.19
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
0˚
8˚
08-soic-5x6-SA-8
1.27
0.40
1mm
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 150 MIL BODY WIDTH (4.9MM X 6MM)
SST PACKAGE CODE: SA
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Pin #1
Identifier
TOP VIEW
SIDE VIEW
0.50
0.35
5.40
5.15
1.27 BSC
0.25
0.05
5.40
5.15
8.10
7.70
END VIEW
2.16
1.75
0˚
0.25
0.19
Note: 1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8˚
08-soic-EIAJ-S2A-3
0.80
0.50
1mm
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH (5.2MM X 8MM)
SST PACKAGE CODE: S2A
©2004 Silicon Storage Technology, Inc.
S71231-04-000
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6/04
2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin #1
0.25
0.19
Pin #1
Corner
1.27 BSC
5.00 ± 0.10
0.076
4.00 ± 0.10
0.48
0.35
3.40 ± 0.10
0.70
0.50
0.05 Max
6.00 ± 0.10
0.80
0.70
CROSS SECTION
0.80
0.70
Note: 1. All linear dimensions are in millimeters (max/min).
8-wson-6x5-QA-8
1mm
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)
SST PACKAGE CODE: QA
TABLE 12: REVISION HISTORY
Number
Description
Date
00
•
Initial release of S71231
(2 Mbit and 4 Mbit parts were originally described in data sheet S71192)
Apr 2003
01
•
Updated Figures 2, 4 - 14: Aligned SI waveform with rising edge of clock
Aug 2003
02
•
Added new 8-SOIC (S2A) package and associated MPNs
Oct 2003
03
•
•
2004 Data Book
Updated the Package Outline for S2A
Dec 2003
04
•
Added Extended temperature and associated MPNs
Jun 2004
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2004 Silicon Storage Technology, Inc.
S71231-04-000
24
6/04