TI LMZ23610TZE

LMZ23610
www.ti.com
SNVS707C – MARCH 2011 – REVISED MAY 2011
LMZ23610 10A SIMPLE SWITCHER® Power Module with 36V Maximum Input Voltage and
Current Sharing
Check for Samples: LMZ23610
KEY FEATURES
ELECTRICAL SPECIFICATIONS
•
•
•
•
•
•
•
•
1
23
•
•
•
•
•
•
•
Integrated Shielded Inductor
Simple PCB Layout
Frequency Synchronization Input (350 kHz to
600 kHz)
Current Sharing Capability
Flexible Startup Sequencing Using External
Soft-start, Tracking and Precision Enable
Protection Against Inrush Currents and Faults
Such as Input UVLO and Output Short Circuit
– 40°C to 125°C Junction Temperature Range
Single Exposed Pad and Standard Pinout for
Easy Mounting and Manufacturing
Fully Enabled for WEBENCH® Power Designer
Pin Compatible with LMZ22010/08,
LMZ12010/08, LMZ23608/06H, and
LMZ13610/08/06H
APPLICATIONS
•
•
•
•
Point of Load Conversions from 12V and 24V
Input Rail
Time Critical Projects
Space Constrained / High Thermal
Requirement Applications
Negative Output Voltage Applications (See AN2027, literature number SNVA425)
50W Maximum Total Output Power
Up to 10A Output Current
Input Voltage Range 6V to 36V
Output Voltage Range 0.8V to 6V
Efficiency up to 92%
DESCRIPTION
The LMZ23610 SIMPLE SWITCHER power module
is an easy-to-use step-down DC-DC solution capable
of driving up to 10A load. The LMZ23610 is available
in an innovative package that enhances thermal
performance and allows for hand or machine
soldering.
The LMZ23610 can accept an input voltage rail
between 6V and 36V and deliver an adjustable and
highly accurate output voltage as low as 0.8V. The
LMZ23610 only requires two external resistors and
three external capacitors to complete the power
solution. The LMZ23610 is a reliable and robust
design with the following protection features: thermal
shutdown, input under-voltage lockout, output overvoltage protection, short-circuit protection, output
current limit, and allows startup into a pre-biased
output. The sync input allows synchronization over
the 350 to 600 kHz switching frequency range.
PERFORMANCE BENEFITS
•
•
•
•
•
•
High Efficiency Reduces System Heat
Generation
Low Radiated Emissions (EMI) Complies with
EN55022 Class B Standard
– EN 55022:2006, +A1:2007, FCC Part 15
Subpart B
Only 7 External Components
Low Output Voltage Ripple
No External Heat Sink Required
Simple Current Sharing for Higher Current
Applications
15 x 17.79 x 5.9 mm (0.59 x 0.7 x 0.232 in)
θJA = 9.9ºC/W
θJA measured on a 75mm x 90mm four
layer PCB.
Figure 1. PFM 11 Pin Package
RoHS Compliant
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
LMZ23610
SNVS707C – MARCH 2011 – REVISED MAY 2011
www.ti.com
System Performance
100
EFFICIENCY (%)
90
80
70
60
50
40
30
24 Vin
20
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
9 10
Figure 2. Efficiency VIN = 24V VOUT = 3.3V
MAXIMUM OUTPUT CURRENT (A)
12
10
8
6
4
2
JA = 9.9 °C/W
JA = 6.8 °C/W
JA = 5.2 °C/W
0
20
40
60
80
100
TEMPERATURE (C)
120
Figure 3. Thermal derating curve
VIN = 24V, VOUT = 3.3V
Simplified Application Schematic
VOUT
6V
5V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.8V
VOUT
SH
SS
FB
PGND
AGND
EN
SYNC
VIN
VIN
LMZ23610
RFBT
15.4k
5.62k
3.32k
2.26k
1.87k
1.00k
1.07k
1.62k
0
RFBB VIN Range
2.37k 8.5...36V
1.07k
7...36V
1.07k
6...36V
1.07k
6...36V
1.50k
6...36V
1.13k
6...36V
2.05k
6...36V
6.49k
6...36V
4.02k
6...36V
VOUT
Share
Clock
CFF 4.7 nF (OPT)
Enable
RFBT
See Table
CIN
3 x 10 PF
2
CSS
0.47 PF
(OPT)
RFBB
See Table
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COUT
2 x 330 PF
Copyright © 2011, Texas Instruments Incorporated
Product Folder Links: LMZ23610
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SNVS707C – MARCH 2011 – REVISED MAY 2011
Connection Diagram
11
10
9
8
7
6
5
4
3
2
1
PGND/EP
Connect to AGND
VOUT
VOUT
SH
SS
FB
AGND
AGND
EN
SYNC
VIN
VIN
Figure 4. Top View
11-Lead PFM
PIN DESCRIPTIONS
Pin
Name
Description
1, 2
VIN
3
SYNC
Sync Input — Apply a CMOS logic level square wave whose frequency is between 350 kHz and 600 kHz to synchronize
the PWM operating frequency to an external frequency source. When not using synchronization this pin must be tied to
ground. The module free running PWM frequency is 350 kHz.
4
EN
Enable — Input to the precision enable comparator. Rising threshold is 1.274V typical. Once the module is enabled, a 20
uA source current is internally activated to accommodate programmable hysteresis.
5, 6
AGND
7
FB
Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference
point is 0.8V at this input pin. Connect the feedback resistor divider between the output and AGND to set the output
voltage.
8
SS
Soft-Start/Track input — To extend the 1.6 mSec internal soft-start connect an external soft start capacitor. For tracking
connect to an external resistive divider connected to a higher priority supply rail. See Design Steps for the LMZ23610
Application section.
9
SH
Share pin. Connect this to the share pin of other LMZ23610 modules to share the load between the devices. One device
should be configured as the master by connecting the FB normally. All other devices should be configured as slaves by
leaving their respective FB pins floating. Leave this pin floating if not used, do not ground. See Design Steps for the
LMZ23610 Application section.
10,
11
VOUT
Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and PGND.
EP
PGND
Exposed Pad / Power Ground Electrical path for the power circuits within the module. — NOT Internally connected to
AGND / pin 5. Used to dissipate heat from the package during operation. Must be electrically connected to pin 5 external
to the package.
Supply input — Nominal operating range is 6V to 36V . A small amount of internal capacitance is contained within the
package assembly. Additional external input capacitance is required between this pin and PGND.
Analog Ground — Reference point for all stated voltages. Must be externally connected to EP/PGND.
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SNVS707C – MARCH 2011 – REVISED MAY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
VIN to PGND
-0.3V to 40V
EN, SYNC to AGND
-0.3V to 5.5V
SS, FB, SH to AGND
-0.3V to 2.5V
AGND to PGND
-0.3V to 0.3V
Junction Temperature
150°C
Storage Temperature Range
ESD Susceptibility
-65°C to 150°C
(3)
± 2 kV
For soldering specifications:
see product folder at www.ti.com and literature number SNOA549
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
OPERATING RATINGS (1)
VIN
6V to 36V
EN, SYNC
0V to 5.0V
−40°C to 125°C
Operation Junction Temperature
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
ELECTRICAL CHARACTERISTICS
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 12V, VOUT = 3.3V
Symbol
Parameter
Conditions
Min
Typ
Max
(1)
Units
1.096
1.274
1.452
V
(1)
(2)
SYSTEM PARAMETERS
Enable Control
VEN
EN threshold
VEN rising
EN hysteresis source current
VEN > 1.274V
ISS
SS source current
VSS = 0V
tSS
Internal soft-start interval
IEN-HYS
13
µA
Soft-Start
40
50
60
1.6
µA
msec
Current Limit
ICL
Current limit threshold
d.c. average
12.5
A
Internal Switching Oscillator
fosc
Free-running oscillator frequency
Sync input connected to ground
314
fsync
Synchronization range
Vsync = 3.3Vp-p
314
VIL-sync
Synchronization logic zero
amplitude
Relative to AGND
VIH-sync
Synchronization logic one
amplitude
Relative to AGND
Sync d.c.
(1)
(2)
4
Synchronization duty cycle range
359
404
kHz
600
kHz
0.4
V
1.8
15
V
50
85
%
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
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SNVS707C – MARCH 2011 – REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 12V, VOUT = 3.3V
Symbol
Parameter
Conditions
Min
Typ
Max
(1)
Units
0.775
0.795
0.815
V
(1)
(2)
Regulation and Over-Voltage Comparator
VFB
VFB-OV
In-regulation feedback voltage
VSS >+ 0.8V
IO = 10A
Feedback over-voltage protection
threshold
0.86
V
5
nA
IFB
Feedback input bias current
IQ
Non Switching Quiescent Current
SYNC = 3.0V
3
mA
ISD
Shut Down Quiescent Current
VEN = 0V
32
μA
85
%
Dmax
Maximum Duty Factor
Thermal Characteristics
TSD
TSD-HYST
θJA
θJC
Thermal Shutdown
Rising
165
°C
Thermal shutdown hysteresis
Falling
15
°C
Natural Convection
9.9
°C/W
225 LFPM
6.8
500 LFPM
5.2
Junction to Ambient
Junction to Case
PERFORMANCE PARAMETERS
ΔVO
(3)
(4)
(3)
1.0
°C/W
24
mV
(4)
Output voltage ripple
[email protected] 20 MHz
ΔVO/ΔVIN
Line regulation
VIN = 12V to 20V, IOUT= 10A
ΔVO/ΔIOUT
Load regulation
VIN = 12V, IOUT= 0.001A to 10A
η
Peak efficiency
VIN = 12V VOUT = 3.3V IOUT = 5A
η
Full load efficiency
VIN = 12V VOUT = 3.3V IOUT = 10A
87.5
%
PP
±0.2
%
1
mV/A
89.5
%
Theta JA measured on a 3.0” x 3.5” four layer board, with two ounce copper on outer layers and one ounce copper on inner layers, two
hundred and ten 12 mil thermal vias, and 2W power dissipation. Refer to evaluation board application note layout diagrams.
Refer to BOM in Typical Application Bill of Materials.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Dissipation 5.0V output @ 25°C
12
90
10
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 5.0V output @ 25°C
100
80
70
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
60
50
40
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
0
9 10
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 5.
Figure 6.
Dissipation 3.3V output @ 25°C
12
90
10
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 3.3V output @ 25°C
100
80
70
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
60
50
40
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
0
9 10
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 7.
Dissipation 2.5V output @ 25°C
12
90
10
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 2.5V output @ 25°C
80
70
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
50
40
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
9 10
Figure 9.
6
9 10
Figure 8.
100
60
9 10
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
9 10
Figure 10.
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SNVS707C – MARCH 2011 – REVISED MAY 2011
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Dissipation 1.8V output @ 25°C
12
80
10
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 1.8V output @ 25°C
90
70
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
40
30
20
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
0
9 10
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 11.
Figure 12.
Dissipation 1.5V output @ 25°C
12
80
10
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 1.5V output @ 25°C
90
70
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
40
30
20
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
0
9 10
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 13.
Efficiency 1.2V output @ 25°C
Dissipation 1.2V output @ 25°C
12
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
70
DISSIPATION (W)
EFFICIENCY (%)
80
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
30
20
10
0
1
9 10
Figure 14.
90
40
9 10
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 15.
8
6
4
2
0
9 10
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 16.
9 10
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Efficiency 1.0V output @ 25°C
Dissipation 1.0V output @ 25°C
12
90
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
80
10
DISSIPATION (W)
EFFICIENCY (%)
70
60
50
40
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
30
20
10
0
0
1
8
6
4
2
0
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 17.
9 10
0
12
90
10
80
70
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
60
50
40
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 18.
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
8
6
4
2
0
0
9 10
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 19.
Efficiency 3.3V output @ 85°C
Dissipation 3.3V output @ 85°C
12
70
60
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
30
20
0
8
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
80
DISSIPATION (W)
EFFICIENCY (%)
90
40
1
9 10
Figure 20.
100
50
9 10
Dissipation 5.0V output @ 85°C
100
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 5.0V output @ 85°C
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 21.
8
6
4
2
0
9 10
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0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 22.
9 10
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LMZ23610
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SNVS707C – MARCH 2011 – REVISED MAY 2011
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Efficiency 2.5V output @ 85°C
100
Dissipation 2.5V output @ 85°C
12
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
80
DISSIPATION (W)
EFFICIENCY (%)
90
70
60
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
50
40
30
20
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 23.
8
6
4
2
0
9 10
0
14
80
12
70
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
40
30
20
10
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 25.
8
6
4
2
0
9 10
0
80
12
70
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
20
10
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 27.
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 26.
9 10
Dissipation 1.5V output @ 85°C
14
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 1.5V output @ 85°C
30
9 10
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
90
40
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 24.
Dissipation 1.8V output @ 85°C
90
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 1.8V output @ 85°C
1
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
8
6
4
2
0
9 10
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 28.
9 10
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Dissipation 1.2V output @ 85°C
14
80
12
70
DISSIPATION (W)
EFFICIENCY (%)
Efficiency 1.2V output @ 85°C
90
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
40
30
20
10
0
1
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
10
8
6
4
2
0
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 29.
9 10
0
Efficiency 1.0V output @ 85°C
80
12
DISSIPATION (W)
EFFICIENCY (%)
60
50
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36Vin
20
10
0
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 31.
10
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 33.
4
0
1
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 32.
9 10
Thermal derating VIN = 24V, VOUT = 5.0V
12
MAXIMUM OUTPUT CURRENT (A)
NORMALIZED VOUT (V/V)
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
36 Vin
1
6
0
1.000
0
8
9 10
1.001
0.998
10
2
Normalized line and load regulation VOUT = 3.3V
1.002
0.999
9 10
6 Vin
10 Vin
12 Vin
16 Vin
20 Vin
24 Vin
30 Vin
36 Vin
70
30
2 3 4 5 6 7 8
OUTPUT CURRENT (A)
Figure 30.
Dissipation 1.0V output @ 85°C
14
90
40
1
10
8
6
4
2
0
9 10
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JA = 9.9 °C/W
JA = 6.8 °C/W
JA = 5.2 °C/W
20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (C)
Figure 34.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
θJA
vs
copper heat sinking area
30
2 Layer 0 LFPM
2 Layer 225 LFPM
4 Layer 0 LFPM
4 Layer 225 LFPM
27
10
24
THETA JA (°C/W)
MAXIMUM OUTPUT CURRENT (A)
Thermal derating VIN = 24V, VOUT = 3.3V
12
8
6
4
21
18
15
12
9
2
0
JA = 9.9 °C/W
JA = 6.8 °C/W
JA = 5.2 °C/W
6
3
0
Figure 35.
4
6
8
2
COPPER AREA (in )
Figure 36.
Output ripple
12VIN, 5.0VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, [email protected] Full Load, BW = 250 MHz
Figure 37.
Figure 38.
Output ripple
12VIN, 3.3VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, [email protected] Full Load, BW = 250 MHz
Figure 39.
Figure 40.
20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (C)
2
10
12
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
Output ripple
12VIN, 1.2VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, [email protected] Full Load, BW = 250 MHz
Figure 41.
Figure 42.
Transient response
12VIN, 5.0VOUT 1 to 10A Step
Transient response
12VIN, 3.3VOUT 1 to 10A Step
Figure 43.
Figure 44.
Transient response
12VIN, 1.2VOUT 1 to 10A Step
Short circuit current
vs
input voltage
16
14
CURRENT (A)
12
10
8
6
4
Output Current
Input Current
2
0
5
Figure 45.
12
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10
15
INPUT VOLTAGE (V)
Figure 46.
20
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated
temperatures are ambient.
3.3VOUT Soft Start, no CSS
3.3VOUT Soft Start, CSS = 0.47uF
Figure 47.
Figure 48.
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BLOCK DIAGRAM
Linear
Regulator
2M
VIN
1
3
3
CIN
EN
2
350 kHz
PWM
SS
2.2 uH VOUT
VREF
3
RFBT
CINint
1
SYNC
CSS
CBST
COUT
FB
RFBB
2
Comp
SH
Filter
AGND
14
Regulator IC
EP/
PGND
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Internal Passives
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DESIGN STEPS FOR THE LMZ23610 APPLICATION
The LMZ23610 is fully supported by WEBENCH which offers: component selection, electrical and thermal
simulations. Additionally, there are both evaluation and demonstration boards that may be used as a starting
point for design. The following list of steps can be used to manually design the LMZ23610 application.
All
•
•
•
•
•
•
references to values refer to the typical applications schematic.
Select minimum operating VIN with enable divider resistors
Program VOUT with FB resistor divider selection
Select COUT
Select CIN
Determine module power dissipation
Layout PCB for required thermal performance
ENABLE DIVIDER, RENT, RENB AND RENHSELECTION
Internal to the module is a 2 mega ohm pull-up resistor connected from VIN to Enable. For applications not
requiring precision under voltage lock out (UVLO), the Enable input may be left open circuit and the internal
resistor will always enable the module. In such case, the internal UVLO occurs typically at 4.3V (VIN rising).
In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case
of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than
the LMZ23610 output rail.
Enable provides a precise 1.274V threshold to allow direct logic drive or connection to a voltage divider from a
higher enable voltage such as VIN. Additionally there is 13 μA (typ) of switched offset current allowing
programmable hysteresis. See Figure 49.
The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will
be disabled. This implements the feature of a programmable UVLO. The two resistors should be chosen based
on the following ratio:
RENT / RENB = (VIN UVLO / 1.274V) – 1
(1)
The LMZ23610 typical application shows 12.7kΩ for RENB and 42.2kΩ for RENT resulting in a rising UVLO of
5.51V. Note that this divider presents 4.62V to the EN input when VIN is raised to 20V. This upper voltage should
always be checked, making sure that it never exceeds the Abs Max 5.5V limit for Enable. A 5.1V Zener clamp
can be applied in cases where the upper voltage would exceed the EN input's range of operation. The zener
clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of RENH. It is possible to select values for
RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
VEN(rising) = 1.274 ( 1 + (RENT|| 2 meg)/ RENB)
(2)
Whereas the falling threshold level can be calculated using:
VEN(falling) = VEN(rising) – 13 µA ( RENT|| 2 meg || RENTB + RENH )
(3)
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VIN
INT-VCC (5V)
13 PA
2.0M
RENT
42.2k
RENH
ENABLE
RUN
100:
5.1V
RENB
12.7k
1.274V
Figure 49. Enable input detail
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between VOUT and AGND. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VOUT = 0.795V * (1 + RFBT / RFBB)
(4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VOUT / 0.795V) - 1
(5)
These resistors should generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For VOUT = 0.8V the FB pin can be connected to the output directly and RFBB can be set to 8.06kΩ to provide
minimum output load.
A table of values for RFBT , and RFBB, is included in the Simplified Application Schematic.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turn-on, after all UVLO conditions have been passed, an internal 1.6msec circuit slowly ramps the SS input
to implement internal soft start. If 1.6 msec is an adequate turn–on time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft start duration is given by the formula:
tSS = VREF * CSS / Iss = 0.795V * CSS / 50uA
(6)
This equation can be rearranged as follows:
CSS = tSS * 50μA / 0.795V
(7)
Using a 0.22μF capacitor results in 3.5 msec typical soft-start duration; and 0.47μF results in 7.5 msec typical.
0.47 μF is a recommended initial value.
As the soft-start input exceeds 0.795V the output of the power stage will be in regulation and the 50 μA current is
deactivated. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to
ground with an internal current sink.
• The Enable input being pulled low
• A thermal shutdown condition
• VIN falling below 4.3V (TYP) and triggering the VCC UVLO
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TRACKING SUPPLY DIVIDER OPTION
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the
3.3V system rail) where the slave module output voltage is lower than that of the master. Proper configuration
allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails
during ramp-up is small (i.e. <0.15V typ). The values for the tracking resistive divider should be selected such
that the effect of the internal 50uA current source is minimized. In most cases the ratio of the tracking divider
resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates
the soft-start time of the slave rail be shorter than the master rail; a condition that is easy to satisfy since the CSS
cap is replaced by RTKB. The tracking function is only supported for the power up interval of the master supply;
once the SS/TRK rises past 0.795V the input is no longer enabled and the 50 uA internal current source is
switched off.
3.3V Master
2.5Vout
Int VCC
50 PA
Rtkt
226
Rfbt
2.26k
SS
FB
Rtkb
107
Rfbb
1.07k
Figure 50. Tracking option input detail
COUT SELECTION
None of the required COUT output capacitance is contained within the module. A minimum value ranging from 330
μF for 6VOUT to 660 μF for 1.2VOUT applications is required based on the values of internal compensation in the
error amplifier. These minimum values can be decreased if the effective capacitor ESR is higher than 15
mOhms.
A Low ESR (15 mOhm) tantalum, organic semiconductor or specialty polymer capacitor types in parallel with a
47nF X7R ceramic capacitor for high frequency noise reduction is recommended for obtaining lowest ripple. The
output capacitor COUT may consist of several capacitors in parallel placed in close proximity to the module.
The output capacitor assembly must also meet the worst case ripple current rating of ΔiL, as calculated in
Equation 18 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low
enough to permit it. Loop response verification is also valuable to confirm closed loop behavior.
For applications with dynamic load steps; the following equation provides a good first pass approximation of COUT
for load transient requirements.
Istep
COUT t
('VOUT - ISTEP x ESR) x (
fSW
)
VOUT
(8)
For 12VIN, 3.3VOUT, a transient voltage of 5% of VOUT = 0.165V (ΔVOUT), a 9A load step (ISTEP), an output
capacitor effective ESR of 3 mOhms, and a switching frequency of 350kHz (fSW):
9A
COUT t
(0.165V - 9A x 0.003) x (
350e3
)
3.3V
t 615 PF
(9)
Note that the stability requirement for minimum output capacitance must always be met.
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One recommended output capacitor combination is two 330μF, 15 mOhm ESR tantalum polymer capacitors
connected in parallel with a 47 uF 6.3V X5R ceramic. This combination provides excellent performance that may
exceed the requirements of certain applications. Additionally some small 47nF ceramic capacitors can be used
for high frequency EMI suppression.
CIN SELECTION
The LMZ23610 module contains two internal ceramic input capacitors. Additional input capacitance is required
external to the module to handle the input ripple current of the application. The input capacitor can be several
capacitors in parallel. This input capacitance should be located in very close proximity to the module. Input
capacitor selection is generally directed to satisfy the input ripple current requirements rather than by
capacitance value. Input ripple current rating is dictated by the equation:
ICIN-RMS = IOUT x D(1-D)
where
•
D ≊ VOUT / VIN
(10)
(As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when VIN = 2 * VOUT).
Recommended minimum input capacitance is 30 uF X7R (or X5R) ceramic with a voltage rating at least 25%
higher than the maximum applied input voltage for the application. It is also recommended that attention be paid
to the voltage and temperature derating of the capacitor selected. It should be noted that ripple current rating of
ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor
manufacturer for this parameter.
If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔVIN) to be
maintained then the following equation may be used.
CIN 8
IOUT x D x (1 - D)
fSW x 'VIN
(11)
If ΔVIN is 200 mV or 1.66% of VIN for a 12V input to 3.3V output application and fSW = 350 kHz then:
10A x §
CIN 8
3.3V · § 3.3V·
x 1© 12V ¹ © 12V ¹
350 kHz x 200 mV
8 28 µF
(12)
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines. The LMZ23610 typical applications schematic
and evaluation board include a 150 μF 50V aluminum capacitor for this function. There are many situations
where this capacitor is not necessary.
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POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS
When calculating module dissipation use the maximum input voltage and the average output current for the
application. Many common operating conditions are provided in the characteristic curves such that less common
applications can be derived through interpolation. In all designs, the junction temperature must be kept below the
rated maximum of 125°C.
For the design case of VIN = 12V, VOUT = 3.3V, IOUT = 10A, and TA-MAX = 50°C, the module must see a thermal
resistance from case to ambient (θCA) of less than:
TCA <
TJ-MAX ± TA-MAX
- TJC
PIC_LOSS
(13)
Given the typical thermal resistance from junction to case (θJC) to be 1.0 °C/W. Use the 85°C power dissipation
curves in the Typical Performance Characteristics section to estimate the PIC-LOSS for the application being
designed. In this application it is 5.3W.
TCA <
125°C ± 50°C
- 1.0 °C < 13.15 °C
5.3 W
W
W
(14)
To reach θCA = 13.15, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink,
a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metal layers is:
Board Area_cm2 8
500 . °C x cm 2
TCA
W
(15)
As a result, approximately 38.02 square cm of 2 oz copper on top and bottom layers is the minimum required
area for the example PCB design. This is 6.16 x 6.16 cm (2.42 x 2.42 in) square. The PCB copper heat sink
must be connected to the exposed pad. For best performance, use approximately 100, 12mil (305 μm) thermal
vias spaced 59 mil (1.5 mm) apart connect the top copper to the bottom copper.
Another way to estimate the temperature rise of a design is using θJA. An estimate of θJA for varying heat sinking
copper areas and airflows can be found in the typical applications curves. If our design required the same
operating conditions as before but had 225 LFPM of airflow. We locate the required θJA of
TJA <
TJ-MAX ± TA-MAX
PIC_LOSS
(125 - 50) °C
°C
< 14.15
TJA <
5.3 W
W
(16)
On the Theta JA vs copper heatsinking curve, the copper area required for this application is now only 2 square
inches. The airflow reduced the required heat sinking area by a factor of three.
To reduce the heat sinking copper area further, this package is compatible with D3-PAK surface mount heat
sinks.
For an example of a high thermal performance PCB layout for SIMPLE SWITCHER power modules, refer to AN2093 (SNVA460), AN-2084 (SNVA456), AN-2125 (SNVA473), AN-2020 (SNVA419) and AN-2026 (SNVA424).
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PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules. A good layout example is shown in
Figure 58.
VOUT
VIN
VOUT
VIN
High
di/dt
CIN
COUT
PGND
Loop 2
Loop 1
Figure 51. High Current Loops
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as
shown in Figure 51. The high current loops that do not overlap have high di/dt content that will cause
observable high frequency noise on the output pin if the input capacitor (CIN) is placed at a distance away
from the LMZ23610. Therefore place CIN as close as possible to the LMZ23610 VIN and PGND exposed
pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input
and output capacitor should consist of a localized top side plane that connects to the PGND exposed pad
(EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the AGND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior. Additionally provide a single point ground connection from pin 4 (AGND) to EP/PGND.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB should be located close to the FB pin. Since the FB node is high
impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB should be routed
away from the body of the LMZ23610 to minimize possible noise pickup.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.
If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heatspreading ground planes. For best results use a 10 x 10 via array or larger with a minimum via diameter of
12mil (305 μm) thermal vias spaced 46.8mil (1.5 mm). Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
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ADDITIONAL FEATURES
SYNCHRONIZATION INPUT
The PWM switching frequency can be synchronized to an external frequency source. The PWM switching will be
in phase with the external frequency source. If this feature is not used, connect this input either directly to
ground, or connect to ground through a resistor of 1.5 kΩ ohm or less. The allowed synchronization frequency
range is 314 kHz to 600 kHz. The typical input threshold is 1.4V. Ideally, the input clock should overdrive the
threshold by a factor of 2, so direct drive from 3.3V logic via a 1.5kΩ or less Thevenin source resistance is
recommended. Note that applying a sustained “logic 1” corresponds to zero Hz PWM frequency and will cause
the module to stop switching.
CURRENT SHARING
When a load current higher than 10A is required by the application, the LMZ23610 can be configured to share
the load between multiple devices. To share the load current between the devices, connect the SH pin of all
current sharing LMZ23610 modules. One device should be configured as the master by connecting FB normally.
All other devices should be configured as slaves by leaving their respective FB pins floating. The modules should
be synchronized by a clock signal to avoid beat frequencies in the output voltage caused by small differences in
the internal 359 kHz clock. If the modules are not synchronized, the magnitude of the ripple voltage will depend
on the phase relationship of the internal clocks. The external synchronizing clocks can be in phase for all
modules, or out of phase to reduce the current stress on the input and output capacitors. As an example, two
modules can be run 180 degrees out of phase, and three modules can be run 120 degrees out of phase. The
VIN, VOUT, PGND, and AGND pins should also be connected with low impedance paths. It is particularly
important to pay close attention to the layout of AGND and SH, as offsets in grounding or noise picked up from
other devices will be seen as a mismatch in current sharing and could cause noise issues.
Current sharing modules can be configured to share the same set of bulk input and output capacitors, while each
having their own local input and output bypass capacitors. A CIN_BYP >= 30uF is still recommended for each
module that is connected in a current sharing configuration. A COUT_BYP consisting of 47nF X7R ceramic
capacitor in parallel with a 22µF ceramic capacitor is recommended to locally bypass the output voltage for each
module. These capacitors will provide local bypassing of high frequency switched currents.
The loop gain of the master module increases by a factor of two when the share pin is connected with a second
module. This increases the bulk output capacitance required for stability. For example, two modules configured
to provide 1.2VOUT and 20 amps have a required total bulk output capacitance of COUT_BULK = 2 x 450µF (ESR
25mOhms). This is a thirty six percent increase in the required output capacitance of a stand alone module. Up
to 6 modules can be connected in parallel for loads up to 60A. For more information on current sharing refer to
AN-2093 LMZ23610/8/6 and LMZ22010/8/6 Current Sharing Evaluation Board (literature number SNVA460).
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VOUT
SH
SS
X X
Clk
CIN_BYP
FB
AGND
PGND
EN
SYNC
VIN
SLAVE
Share
COUT_BYP
Enable
VIN
VOUT
Clk
CIN_BYP
VOUT
SH
SS
FB
AGND
PGND
EN
VIN
CIN_BULK
SYNC
MASTER
COUT_BULK
LOAD
Share
CSS
Enable
COUT_BYP
RFBB
RFBT
Figure 52. Current Sharing Example Schematic
Figure 53. Output voltage ripple of two modules
with synchronization clocks in phase
Figure 54. Output voltage ripple of two modules
with synchronization clocks 180 degrees out of
phase
OUTPUT OVER-VOLTAGE PROTECTION
If the voltage at FB is greater than a 0.86V internal reference, the output of the error amplifier is pulled toward
ground, causing VOUT to fall.
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CURRENT LIMIT
The LMZ23610 is protected by both low side (LS) and high side (HS) current limit circuitry. The LS current limit
detection is carried out during the off-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 13A (typical) the
current limit comparator disables the start of the next switching period. Switching cycles are prohibited until
current drops below the limit. It should also be noted that d.c. current limit is dependent on duty cycle as
illustrated in the graph in the Typical Performance Characteristics section. The HS current limit monitors the
current of top side MOSFET. Once HS current limit is detected (16A typical) , the HS MOSFET is shutoff
immediately, until the next cycle. Exceeding HS current limit causes VOUT to fall. Typical behavior of exceeding
LS current limit is that fSW drops to 1/2 of the operating frequency.
THERMAL PROTECTION
The junction temperature of the LMZ23610 should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VOUT to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 150 °C (typ Hyst = 15°C) the SS
pin is released, VOUT rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require additional
derating at elevated temperatures.
PRE-BIASED STARTUP
The LMZ23610 will properly start up into a pre-biased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the startup sequence. The
following scope capture shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.8V
pre-bias rising to 3.3V. Trace three is the SS voltage with a CSS= 0.47uF. Risetime determined by CSS.
Figure 55. Pre-Biased Startup
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DISCONTINUOUS CONDUCTION AND CONTINUOUS CONDUCTION MODES
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM, inductor
current is maintained to an average value equaling Iout. In DCM the low-side switch will turn off when the
inductor current falls to zero, this causes the inductor current to resonate. Although it is in DCM, the current is
allowed to go slightly negative to charge the bootstrap capacitor.
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
off-time.
Following is a comparison pair of waveforms showing both the CCM (upper) and DCM operating modes.
Figure 56. CCM and DCM Operating Modes
VIN = 12V, VO = 3.3V, IO = 3A/0.3A
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB =
(VIN - VOUT) x D
2 x L x fSW
(17)
The inductor internal to the module is 2.2 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ΔiL). ΔiL can be calculated with:
'iL =
(VIN - VOUT) x D
L x fSW
where
•
•
VIN is the maximum input voltage
fSW is typically 359 kHz
(18)
If the output current IOUT is determined by assuming that IOUT = IL, the higher and lower peak of ΔiL can be
determined.
24
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Product Folder Links: LMZ23610
LMZ23610
www.ti.com
SNVS707C – MARCH 2011 – REVISED MAY 2011
Typical Application Schematic Diagram and BOM
CIN2,3,4
VOUT
Share
CSS
RSYNC
CIN1
VOUT
SH
SS
FB
PGND
AGND
Clk
+ CIN5
(OPT)
CIN6
(OPT)
EN
VIN
SYNC
VIN
LMZ23610
CO3,4
CO1
(OPT)
CO2
(OPT)
CO5
(OPT)
LOAD
RFBB
RENT
RFBT
RENB
D1
5.1V
(OPT)
Figure 57.
Table 1. Typical Application Bill of Materials
Ref Des
Description
Case Size
Manufacturer
Manufacturer P/N
U1
SIMPLE SWITCHER
PFM-11
Texas Instruments
LMZ23610TZ
CIN1,6 (OPT)
0.047 µF, 50V, X7R
1206
Yageo America
CC1206KRX7R9BB473
CIN2,3,4
10 µF, 50V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
CIN5 (OPT)
CAP, AL, 150µF, 50V
Radial G
Panasonic
EEE-FK1H151P
CO1,5 (OPT)
0.047 µF, 50V, X7R
1206
Yageo America
CC1206KRX7R9BB473
CO2 (OPT)
47 µF, 10V, X7R
1210
Murata
GRM32ER61A476KE20L
CO3,4
330 μF, 6.3V, 0.015 ohm
CAPSMT_6_UE
Kemet
T520D337M006ATE015
RFBT
3.32 kΩ
0805
Panasonic
ERJ-6ENF3321V
RFBB
1.07 kΩ
0805
Panasonic
ERJ-6ENF1071V
RSYNC
1.50 kΩ
0805
Vishay Dale
CRCW08051K50FKEA
ERJ-6ENF4222V
RENT
42.2 kΩ
0805
Panasonic
RENB
12.7 kΩ
0805
Panasonic
ERJ-6ENF1272V
CSS
0.47 μF, ±10%, X7R, 16V
0805
AVX
0805YC474KAT2A
D1 (OPT)
5.1V, 0.5W
SOD-123
Diodes Inc.
MMSZ5231BS-7-F
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Product Folder Links: LMZ23610
25
LMZ23610
SNVS707C – MARCH 2011 – REVISED MAY 2011
www.ti.com
Figure 58. Layout example
26
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Product Folder Links: LMZ23610
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMZ23610TZ/NOPB
ACTIVE
PFM
NDY
11
32
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 85
LMZ23610
LMZ23610TZE/NOPB
ACTIVE
PFM
NDY
11
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 85
LMZ23610
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMZ23610TZE/NOPB
Package Package Pins
Type Drawing
PFM
NDY
11
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
32.4
Pack Materials-Page 1
15.45
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
18.34
6.2
20.0
32.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ23610TZE/NOPB
PFM
NDY
11
250
367.0
367.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
NDY0011A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA11A (Rev F)
www.ti.com
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