Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 LMZ10501 1-A SIMPLE SWITCHER® Nano Module With 5.5-V Maximum Input Voltage 1 Features 2 Applications • • • • • • • • • • • • • • • 1 • • • • • Output Current Up to 1 A Input Voltage Range 2.7 V to 5.5 V Output Voltage Range 0.6 V to 3.6 V Efficiency up to 95% Integrated Inductor 8-Pin LLP Footprint –40°C to 125°C Junction Temperature Range Adjustable Output Voltage 2.0-MHz Fixed PWM Switching Frequency Integrated Compensation Soft-Start Function Current Limit Protection Thermal Shutdown Protection Input Voltage UVLO for Power-Up, Power-Down, and Brown-Out Conditions Only 5 External Components — Resistor Divider and 3 Ceramic Capacitors Small Solution Size Low Output Voltage Ripple Easy Component Selection and Simple PCB Layout High Efficiency Reduces System Heat Generation • • • Point of Load Conversions From 3.3-V and 5-V Rails Space Constrained Applications Low Output Noise Applications Quick Links to Reference Designs: VOUT = 1.2 V, VOUT = 1.8 V, VOUT = 2.5 V, VOUT = 3.3 V 3 Description The LMZ10501 SIMPLE SWITCHER® nano module is an easy-to-use step-down DC-DC solution capable of driving up to 1-A load in space-constrained applications. Only an input capacitor, an output capacitor, a small VCON filter capacitor, and two resistors are required for basic operation. The nano module comes in an 8-pin LLP footprint package with an inductor. Internal current limit based soft-start function, current overload protection, and thermal shutdown are also provided. Device Information(1) PART NUMBER LMZ10501 Typical Efficiency at VIN = 3.6 V Radiated EMI (CISPR22) VIN = 5.0 V, VOUT = 1.8 V, IOUT = 1A 80 80 70 70 60 50 VOUT=1.2V VOUT=1.8V VOUT=2.5V VOUT=3.3V 20 0.0 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 1.0 C001 Radiated Emissions (dBµV/m) EFFICIENCY (%) 90 30 BODY SIZE (NOM) 3.00 mm x 2.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 100 40 PACKAGE SIL (8) Evaluation Board EN 55022 Class B Limit EN 55022 Class A Limit 60 50 40 30 20 10 0 0 200 400 600 Frequency (MHz) 800 1000 C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... System Characteristics ............................................. Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 7.2 7.3 7.4 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 20 9.1 Voltage Range ........................................................ 20 9.2 Current Capability ................................................... 20 9.3 Input Connection .................................................... 20 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 21 10.3 Package Considerations ....................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2014) to Revision F • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision D (March 2013) to Revision E • 2 Page Page Added new package SIL0008A ............................................................................................................................................. 3 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 5 Pin Configuration and Functions 8-Pin SIL Package SIDE VIEW TOP VIEW BOTTOM VIEW 1 8 8 VREF 2 7 7 VIN 3 6 6 PGND 4 5 5 VOUT PAD (SGND) EN 1 VCON 2 FB 3 SGND 4 Pin Functions PIN NAME NO. I/O DESCRIPTION EN 1 I Enable Input. Set this digital input higher than 1.2V for normal operation. For shutdown, set low. Pin is internally pulled up to VIN and can be left floating for always-on operation. VCON 2 I Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to set the VOUT voltage. VOUT = 2.5 x VCON. Connect a small (470pF) capacitor from this pin to SGND to provide noise filtering. FB 3 I Feedback of the error amplifier. Connect directly to output capacitor to sense VOUT. SGND 4 I Ground for analog and control circuitry. Connect to PGND at a single point. VOUT 5 O Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter capacitor between VOUT and PGND. PGND 6 I Power ground for the power MOSFETs and gate-drive circuitry. VIN 7 I Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to these two pins. Typical capacitor values are between 4.7µF and 22µF. VREF 8 O 2.35-V voltage reference output. Typically connected to VCON pin through a resistive divider to set the output voltage. I The center pad underneath the SIL0008A package is internally tied to SGND. This pad should be connected to the ground plane for improved thermal performance. PAD Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 3 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VIN, VREF to SGND MIN MAX UNIT −0.2 +6.0 V PGND to SGND −0.2 +0.2 V EN, FB, VCON (SGND −0.2) (VIN +0.2) w/6.0 max V VOUT (PGND −0.2) (VIN +0.2) w/6.0 max V −40 125 °C 260 °C Junction Temperature (TJ-MAX) Maximum Lead Temperature (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For the Electrical Characteristics table for specifications and test conditions. 6.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT −65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 250 V V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Input Voltage Range Recommended Load Current Junction Temperature (TJ) Range MIN MAX 2.7 5.5 UNIT 0 1000 mA −40 125 °C V 6.4 Thermal Information LMZ10501 THERMAL METRIC (1) SIL UNIT 8 PINS (2) RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 25 RθJB Junction-to-board thermal resistance 9.2 ψJT Junction-to-top characterization parameter 1.5 ψJB Junction-to-board characterization parameter 9.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 25 (1) (2) 4 SIL0008A Package 45.8 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Junction-to-ambient thermal resistance (θJA) is based on 4 layer board thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. θJA varies with PCB copper area, power dissipation, and airflow. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted). Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 3.6 V, VEN = 1.2 V. (1) PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT 5.875 5.9925 V V/V SYSTEM PARAMETERS VREF x GAIN Reference voltage x VCON to FB Gain VIN = VEN = 5.5V, VCON = 1.44V 5.7575 GAIN VCON to FB Gain VIN = 5.5V, VCON = 1.44V 2.4375 2.5 2.5750 VINUVLO VIN rising threshold 2.24 2.41 2.64 V VINUVLO VIN UVLO hysteresis 120 165 200 mV HYST ISHDN Shutdown supply current VIN = 3.6V, VEN = 0.5V (3) 11 18 µA Iq DC bias current into VIN VIN = 5.5V, VCON = 1.6V, IOUT = 0A 6.5 9.5 mA RDROPOUT VIN to VOUTresistance IOUT = 200 mA 305 575 mΩ I LIM DC Output Current Limit VCON = 1.72V FOSC 2.25 MHz (4) 1025 1350 Internal oscillator frequency 1.75 2.0 VIH,ENABLE Enable logic HIGH voltage 1.2 VIL,ENABLE Enable logic LOW voltage TSD Thermal shutdown TSD-HYST Thermal shutdown hysteresis DMAX Maximum duty cycle TON-MIN Minimum on-time θJA SIL0008A Package Thermal Resistance (1) (2) (3) (4) mA V 0.5 Rising Threshold V 150 °C 20 °C 100% 50 ns 20mm x 20mm board 2 layers, 2 oz copper, 0.5W, no airlow 77 °C/W 15mm x 15mm board 2 layers, 2 oz copper, 0.5W, no airlow 88 10mm x 10mm board 2 layers, 2 oz copper, 0.5W, no airlow 107 Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate the Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Shutdown current includes leakage current of the high side PFET. Current limit is built-in, fixed, and not adjustable. 6.6 System Characteristics The following specifications are ensured by design providing the component values in Figure 12 are used (CIN = COUT = 10 µF, 6.3 V, 0603, TDK C1608X5R0J106K). These parameters are not ensured by production testing. Unless otherwise stated the following conditions apply: TA = 25°C. PARAMETER ΔVOUT/VO UT ΔVOUT/VO UT ΔVOUT/VO UT VREF TRISE TEST CONDITIONS MIN TYP Output Voltage Regulation Over Line VOUT = 0.6 V Voltage and Load Current ΔVIN = 2.7 V to 4.2 V ΔIOUT = 0A to 1A ±1.75% Output Voltage Regulation Over Line VOUT = 1.5 V Voltage and Load Current ΔVIN = 2.7 V to 5.5 V ΔIOUT = 0A to 1A ±0.92% Output Voltage Regulation Over Line VOUT = 3.6 V Voltage and Load Current ΔVIN = 4.0 V to 5.5 V ΔIOUT = 0A to 1A ±0.38% Rise time of reference voltage EN = Low to High, VIN = 4.2 V VOUT = 2.7 V, IOUT = 1A MAX UNIT 10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 µs 5 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com System Characteristics (continued) The following specifications are ensured by design providing the component values in Figure 12 are used (CIN = COUT = 10 µF, 6.3 V, 0603, TDK C1608X5R0J106K). These parameters are not ensured by production testing. Unless otherwise stated the following conditions apply: TA = 25°C. PARAMETER η TEST CONDITIONS MIN TYP MAX UNIT Peak Efficiency VIN = 5.0 V, VOUT = 3.3 V IOUT = 200 mA 95% Full Load Efficiency VIN = 5.0 V, VOUT = 3.6 V IOUT = 1000 mA 91% VOUT Ripple Output voltage ripple VIN = 5.0 V, VOUT = 1.8 V IOUT = 1000 mA 10 mV pk-pk Line Transient Line transient response VIN = 2.7 V to 5.5 V, TR = TF= 10 µs, VOUT = 1.8 V, IOUT = 1000 mA 30 mV pk-pk Load Transient Load transient response VIN = 5.0 V TR = TF = 40 µs, VOUT = 1.8 V IOUT = 100 mA to 1000 mA 30 mV pk-pk 6 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 6.7 Typical Characteristics Unless otherwise specified the following conditions apply: VIN = 3.6 V, TA = 25°C 1.2 1.0 0.40 OUTPUT CURRENT (A) DROPOUT VOLTAGE (V) 0.50 0.30 0.20 VIN=2.7V VIN=3V VIN=3.3V VIN=3.6V 0.10 0.00 0.0 0.2 0.4 0.6 0.8 0.6 0.4 0.0 60 1.0 OUTPUT CURRENT (A) 1.0 0.8 0.6 0.4 VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 70 100 110 120 AMBIENT TEMPERATURE (C) 130 60 0.6 0.4 VIN=4V VIN=4.5V VIN=5V VIN=5.5V 0.2 0.0 60 70 C001 80 90 100 110 120 130 AMBIENT TEMPERATURE (C) C003 Figure 4. Thermal Derating VOUT = 2.5 V, ΘJA = 77°C/W Radiated Emissions (dBµV/m) OUTPUT CURRENT (A) 70 80 0.8 130 VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 1.2 1.0 120 0.4 C002 Figure 3. Thermal Derating VOUT = 1.8 V, ΘJA = 77°C/W 110 0.6 0.0 90 100 0.8 0.2 80 90 Figure 2. Thermal Derating VOUT = 1.2 V, ΘJA = 77°C/W 1.2 60 80 AMBIENT TEMPERATURE (C) 1.2 0.0 70 C001 Figure 1. Dropout Voltage vs Load Current and Input Voltage, TA = 85°C 0.2 VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 0.2 1.0 LOAD CURRENT (A) OUTPUT CURRENT (A) 0.8 Evaluation Board EN 55022 Class B Limit EN 55022 Class A Limit 70 60 50 40 30 20 10 0 80 90 100 110 AMBIENT TEMPERATURE (C) 120 0 130 Figure 5. Thermal Derating VOUT = 3.3 V, ΘJA = 77°C/W 200 400 600 Frequency (MHz) C004 800 1000 C001 Figure 6. Radiated EMI (Cispr22) VIN = 5.0 V, VOUT = 1.8 V, IOUT = 1-A Default Evaluation Board BOM Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 7 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) Unless otherwise specified the following conditions apply: VIN = 3.6 V, TA = 25°C 100 Radiated Emissions (dBµV/m) VCON Peak Emissions Quasi Peak Limit Average Limit 90 80 500 mV/Div 70 60 50 300 mA/Div IL 40 300 mA/Div 30 20 10 IOUT 500 mV/Div VOUT 10 µs/Div 0 0.1 1 10 Frequency (MHz) 100 C001 Figure 7. Conducted EMI VIN = 5.0 V, VOUT = 1.8 V, IOUT = 1-A Default Evaluation Board BOM with Additional 2.2-µh 1-µf LC Input Filter 8 Submit Documentation Feedback Figure 8. Startup Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 7 Detailed Description 7.1 Overview The LMZ10501 SIMPLE SWITCHER® nano module is an easy-to-use step-down DC-DC solution capable of driving up to 1A load in space-constrained applications. Only an input capacitor, an output capacitor, a small VCON filter capacitor, and two resistors are required for basic operation. The nano module comes in 8-pin LLP footprint package with an integrated inductor. The LMZ10501 operates in fixed 2.0MHz PWM (Pulse Width Modulation) mode, and is designed to deliver power at maximum efficiency. The output voltage is typically set by using a resistive divider between the built-in reference voltage VREF and the control pin VCON. The VCON pin is the positive input to the error amplifier. The output voltage of the LMZ10501 can also be dynamically adjusted between 0.6V and 3.6V by driving the VCON pin externally. Internal current limit based softstart function, current overload protection, and thermal shutdown are also provided. 7.2 Functional Block Diagram VREF VIN UVLO REFERENCE VOLTAGE VCON ERROR AMPLIFIER FB COMP CURRENT COMP CURRENT SENSE L VOUT MOSFET CONTROL LOGIC Integrated Inductor VIN UVLO EN MAIN CONTROL TSD OSCILLATOR SGND PGND 7.3 Feature Description 7.3.1 Current Limit The LMZ10501 current limit feature protects the module during an overload condition. The circuit employs positive peak current limit in the PFET and negative peak current limit in the NFET switch. The positive peak current through the PFET is limited to 1.7A (typ.). When the current reaches this limit threshold the PFET switch is immediately turned off until the next switching cycle. This behavior continues on a cycle-by-cycle basis until the overload condition is removed from the output. The typical negative peak current limit through the NFET switch is -0.6A (typ.). The ripple of the inductor current depends on the input and output voltages. This means that the DC level of the output current when the peak current limiting occurs will also vary over the line voltage and the output voltage level. Refer to the DC Output Current Limit plots in the Typical Characteristics section for more information. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 9 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com Feature Description (continued) 7.3.2 Startup Behavior and Softstart The LMZ10501 features a current limit based soft start circuit in order to prevent large in-rush current and output overshoot as VOUT is ramping up. This is achieved by gradually increasing the PFET current limit threshold to the final operating value as the output voltage ramps during startup. The maximum allowed current in the inductor is stepped up in a staircase profile for a fixed number of switching periods in each step. Additionally, the switching frequency in the first step is set at 450kHz and is then increased for each of the following steps until it reaches 2MHz at the final step of current limiting. This current limiting behavior is illustrated in Figure 9 and allows for a smooth VOUT ramp up. VCON 500 mV/Div 300 mA/Div IL 300 mA/Div IOUT 500 mV/Div VOUT 10 µs/Div Figure 9. Startup Behavior of Current Limit Based Softstart. The soft start rate is also limited by the VCON ramp up rate. The VCON pin is discharged internally through a pull down device before startup occurs. This is done to deplete any residual charge on the VCON filter capacitor and allow the VCON voltage to ramp up from 0V when the part is started. The events that cause VCON discharge are thermal shutdown, UVLO, EN low, or output short circuit detection. The minimum recommended capacitance on VCON is 220pF and the maximum is 1nF. The duration of startup current limiting sequence takes approximately 75µs. After the sequence is completed, the feedback voltage is monitored for output short circuit events. 7.3.3 Output Short Circuit Protection In addition to cycle by cycle current limit, the LMZ10501 features a second level of short circuit protection. If the load pulls the output voltage down and the feedback voltage falls to 0.375 V, the output short circuit protection will engage. In this mode the internal PFET switch is turned OFF after the current limit comparator trips and the beginning of the next cycle is inhibited for approximately 230µs. This forces the inductor current to ramp down and limits excessive current draw from the input supply when the output of the regulator is shorted. The synchronous rectifier is always OFF in this mode. After 230 µs of non-switching a new startup sequence is initiated. During this new startup sequence the current limit is gradually stepped up to the nominal value as illustrated in the Startup Behavior and Softstart section. After the startup sequence is completed again, the feedback voltage is monitored for output short circuit. If the short circuit is still persistent after the new startup sequence, switching will be stopped again and there will be another 230-µs off period. A persistent output short condition results in a hiccup behavior where the LMZ10501 goes through the normal startup sequence, then detects the output short at the end of startup, terminates switching for 230µs, and repeats this cycle until the output short is released. This behavior is illustrated in Figure 10. VOUT 1V/Div IIN 100 mA/Div IL 0.5A/Div VCON 100 µs/Div 1V/Div Figure 10. Hiccup Behavior with Persistent Output Short Circuit. 10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 Feature Description (continued) Since the output current is limited during normal startup by the softstart function, the current charging the output capacitor is also limited. This results in a smooth VOUT ramp up to nominal voltage. However, using excessively large output capacitance or VCON capacitance under normal conditions can prevent the output voltage from reaching 0.375 V at the end of the startup sequence. In such cases the module will maintain the described above hiccup mode and the output voltage will not ramp up to final value. To cause this condition, one would have to use unnecessarily large output capacitance for 1A load applications. See the Input And Output Capacitor Selection section for guidance on maximum capacitances for different output voltage settings. 7.3.4 Thermal Overload Protection The junction temperature of the LMZ10501 should not be allowed to exceed its maximum operating rating of 125°C. Thermal protection is implemented by an internal thermal shutdown circuit which activates at 150°C (typ). When this temperature is reached, the device enters a low power standby state. In this state switching remains off causing the output voltage to fall. Also, the VCON capacitor is discharged to SGND. When the junction temperature falls back below 130°C (typ) normal startup occurs and VOUT rises smoothly from 0V. Applications requiring maximum output current may require derating at elevated ambient temperature. See the Typical Characteristics section for thermal derating plots for various output voltages. 7.4 Device Functional Modes 7.4.1 Circuit Operation The LMZ10501 is a synchronous Buck power module using a PFET for the high side switch and an NFET for the synchronous rectifier switch. The output voltage is regulated by modulating the PFET switch on-time. The circuit generates a duty-cycle modulated rectangular signal. The rectangular signal is averaged using a low pass filter formed by the integrated inductor and an output capacitor. The output voltage is equal to the average of the dutycycle modulated rectangular signal. In PWM mode, the switching frequency is constant. The energy per cycle to the load is controlled by modulating the PFET on-time, which controls the peak inductor current. In current mode control architecture, the inductor current is compared with the slope compensated output of the error amplifier. At the rising edge of the clock, the PFET is turned ON, ramping up the inductor current with a slope of (VIN VOUT)/L. The PFET is ON until the current signal equals the error signal. Then the PFET is turned OFF and NFET is turned ON, ramping down the inductor current with a slope of VOUT /L. At the next rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, resulting in an increase of the error signal. As the error signal goes up, the peak inductor current is increased, elevating the average inductor current and responding to the heavier load. To ensure stability, a slope compensation ramp is subtracted from the error signal and internal loop compensation is provided. 7.4.2 Input Under Voltage Detection The LMZ10501 implements an under voltage lock out (UVLO) circuit to ensure proper operation during startup, shutdown and input supply brownout conditions. The circuit monitors the voltage at the VIN pin to ensure that sufficient voltage is present to bias the regulator. If the under voltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. 7.4.3 Shutdown Mode To shutdown the LMZ10501, pull the EN pin low (< 0.5 V). In the shutdown mode all internal circuits are turned OFF. 7.4.4 EN Pin Operation The EN pin is internally pulled up to VIN through a 790kΩ (typ.) resistor. This allows the nano module to be enabled by default when the EN pin is left floating. In such cases VIN will set EN high when VIN reaches 1.2 V. As the input voltage continues to rise, operation will start once VIN exceeds the under-voltage lockout (UVLO) threshold. To set EN high externally, pull it up to 1.2 V or higher. Note that the voltage on EN must remain at less than VIN+ 0.2 V due to absolute maximum ratings of the device. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 11 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com Device Functional Modes (continued) 7.4.5 Internal Synchronous Rectification The LMZ10501 uses an internal NFET as a synchronous rectifier to minimize the switch voltage drop and increase efficiency. The NFET is designed to conduct through its intrinsic body diode during the built-in dead time between the PFET on-time and the NFET on-time. This eliminates the need for an external diode. The dead time between the PFET and NFET connection prevents shoot through current from VIN to PGND during the switching transitions. 7.4.6 High Duty Cycle Operation The LMZ10501 features a transition mode designed to extend the output regulation range to the minimum possible input voltage. As the input voltage decreases closer and closer to VOUT, the off-time of the PFET gets smaller and smaller and the duty cycle eventually needs to reach 100% to support the output voltage. The input voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10501 input voltage is lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10501 doubles the switching period to extend the off-time for that VIN and maintain regulation. If VIN is lowered even more, the off-time of the PFET will reach the 35ns mark again. The LMZ10501 will then reduce the frequency again, achieving less than 100% duty cycle operation and maintaining regulation. As VIN is lowered even more, the LMZ10501 will continue to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases further, 100% duty cycle is reached. This behavior of extending the VIN regulation range is illustrated in Figure 11. 1V/Div INPUT VOLTAGE 1V/Div SWITCH NODE 20 MHz BW 5 µs/Div Figure 11. High Duty Cycle Operation and Switching Frequency Reduction 12 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information This section describes a simple design procedure. Alternatively, WEBENCH® can be used to create and simulate a design using the LMZ10501. The WEBENCH® tool can be accessed from the LMZ10501 product folder at http://www.ti.com/product/lmz10501. For designs with typical output voltages (1.2 V, 1.8 V, 2.5 V, 3.3 V), jump to the Application Curves section for quick reference designs. 8.2 Typical Application EN VREF RT VCON RB CVC FB VIN CIN 10PF PGND SGND VOUT COUT 10PF Figure 12. Typical Application Circuit 8.2.1 Design Requirements The detailed design procedure is based on the required input and output voltage specifications for the design. The input voltage range of the LMZ10501 is 2.7V to 5.5V. The output voltage range is 0.6V to 3.6V. The output current capability is 1A. 8.2.2 Detailed Design Procedure 8.2.2.1 Setting The Output Voltage The LMZ10501 provides a fixed 2.35V VREF voltage output. As shown in Figure 12 above, a resistive divider formed by RT and RB sets the VCON pin voltage level. The VOUT voltage tracks VCON and is governed by the following relationship: VOUT = GAIN x VCON where GAIN is 2.5V/V from VCON to VFB (1) This equation is valid for output voltages between 0.6V and 3.6V and corresponds to VCON voltage between 0.24V and 1.44V, respectively. 8.2.2.1.1 RT And RB Selection For Fixed VOUT The parameters affecting the output voltage setting are the RT, RB, and the product of the VREF voltage x GAIN. The VREF voltage is typically 2.35V. Since VCON is derived from VREF via RT and RB, VCON = VREF x RB/ (RB + RT) (2) After substitution, VOUT = VREF x GAIN x RB/ (RB + RT) RT = (GAIN x VREF / VOUT – 1) x RB (3) (4) Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 13 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com Typical Application (continued) The ideal product of GAIN x VREF = 5.875 V. Choose RT to be between 80kΩ and 300kΩ. Then, RB can be calculated using Equation 5 below. RB = (VOUT / (5.875 V – VOUT)) x RT (5) Note that the resistance of RT should be ≥ 80kΩ. This ensures that the VREF output current loading is not exceeded and the reference voltage is maintained. The current loading on VREF should not be greater than 30 µA. 8.2.2.1.2 Output Voltage Accuracy Optimization Each nano module is optimized to achieve high VOUT accuracy. Equation 1 shows that, by design, the output voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from VREF. Therefore, as shown in Equation 3, the accuracy of the output voltage is a function of the VREF x GAIN product as well as the tolerance of the RT and RB resistors. The typical VREF x GAIN product by design is 5.875 V. Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875 V value as possible, achieving high VOUT accuracy. See the Features Description section for the VREF x GAIN product tolerance limits. 8.2.2.2 Dynamic Output Voltage Scaling The VCON pin on the LMZ10501 can be driven externally by a DAC to scale the output voltage dynamically. The output voltage VOUT = 2.5 V/V x VCON. When driving VCON with a source different than VREF place a 1.5kΩ resistor in series with the VCON pin. Current limiting the external VCON helps to protect this pin and allows the VCON capacitor to be fully discharged to 0V after fault conditions. 8.2.2.3 Integrated Inductor The LMZ10501 includes an inductor with over 1.2A DC current rating and soft saturation profile for up to 2A. This inductor allows for low package height and provides an easy to use, compact solution with reduced EMI. 8.2.2.4 Input And Output Capacitor Selection The LMZ10501 is designed for use with low ESR multi-layer ceramic capacitors (MLCC) for its input and output filters. Using a 10 µF 0603 or 0805 with 6.3V or 10V rating ceramic input capacitor typically provides sufficient VIN bypass. Use of multiple 4.7 µF or 2.2 µF capacitors can also be considered. Ceramic capacitors with X5R and X7R temperature characteristics are recommended for both input and output filters. These provide an optimal balance between small size, cost, reliability, and performance for space sensitive applications. The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals. For example, a typical 0805 case size X5R 6.3 V 10 µF ceramic capacitor may only have 4.8 µF left in it when a 5.0-V DC bias is applied. Similarly, a typical 0603 case size X5R 6.3V 10 µF ceramic capacitor may only have 2.4 µF at the same 5.0V DC. Smaller case size capacitors may have even larger percentage drop in value with DC bias. The optimum output capacitance value is application dependent. Too small output capacitance can lead to instability due to lower loop phase margin. On the other hand, if the output capacitor is too large, it may prevent the output voltage from reaching the 0.375 V required voltage level at the end of the startup sequence. In such cases, the output short circuit protection can be engaged and the nano module will enter a hiccup mode as described in the Output Short Circuit Protection section. Table 1 sets the minimum output capacitance for stability and maximum output capacitance for proper startup for various output voltage settings. Note that the maximum COUT value in Table 1 assumes that the filter capacitance on VCON is the maximum recommended value of 1nF and the RT resistor value is less than 300kΩ. Lower VCON capacitance can extend the maximum COUT range. There is no great performance benefit in using excessive COUT values. 14 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 Typical Application (continued) Table 1. Output Capacitance Range Output Voltage Minimum COUT Suggested COUT Maximum COUT 0.6V 4.7µF 10µF 47µF 1.0V 3.3µF 10µF 47µF 1.2V 3.3µF 10µF 47µF 1.8V 3.3µF 10µF 68µF 2.5V 3.3µF 10µF 100µF 3.3V 3.3µF 10µF 100µF Use of multiple 4.7-µF or 2.2-µF output capacitors can be considered for reduced effective ESR and smaller output voltage ripple. In addition to the main output capacitor, small 0.1-µF – 0.01-µF parallel capacitors can be used to reduce high frequency noise. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 15 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com 8.2.3 Application Curves 8.2.3.1 VOUT = 1.2 V VIN VIN EN 100 1.2V VOUT CIN 90 VOUT 80 EFFICIENCY (%) VREF FB RT VCON COUT PGND RB SGND CVC 70 60 50 VIN=2.7V VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 40 CIN COUT CVC RT RB 10 P)86.3V 10 PF 86.3V 470 pF 86.3V 243 k: 1% 63.4 k: 1% 0805 X7R or X5R 0805 X7R or X5R 0603 X7R or X5R 0603 0603 30 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 LOAD CURRENT (A) 1 C001 Figure 14. Efficiency VOUT = 1.2 V Figure 13. Schematic VOUT = 1.2 V COUT = 10F 10V 0805 X5R VOUT RIPPLE COUT = 10F 10V 0805 X5R 50mV/Div OUTPUT VOLTAGE 10mV/Div LOAD CURRENT 500mA/Div 250MHz BW 1µs/Div 20 MHz BW Figure 15. Output Ripple VOUT = 1.2 V Figure 16. Load Transient VOUT = 1.2 V 1.8 VIN=2.7V VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 1.23 1.7 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) 1.24 500 µs/Div 1.22 1.21 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) Figure 17. Line and Load Regulation VOUT = 1.2 V 16 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) C002 5.0 5.5 C001 Figure 18. DC Current Limit VOUT = 1.2 V, TA=85°C Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 8.2.3.2 VOUT = 1.8 V VIN VIN EN 100 1.8V VOUT CIN 90 VOUT 80 EFFICIENCY (%) VREF FB RT VCON COUT PGND RB SGND CVC 70 60 50 VIN=2.7V VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 40 CIN COUT CVC RT RB 10 P)86.3V 10 PF 86.3V 470 pF 86.3V 187 k: 1% 82.5 k: 1% 0805 X7R or X5R 0805 X7R or X5R 0603 X7R or X5R 0603 0603 30 20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 LOAD CURRENT (A) 1.0 C001 Figure 20. Efficiency VOUT = 1.8 V Figure 19. Schematic VOUT = 1.8 V COUT = 10F 10V 0805 X5R VOUT RIPPLE COUT = 10F 10V 0805 X5R 50mV/Div OUTPUT VOLTAGE 10mV/Div LOAD CURRENT 500mA/Div 250MHz BW 1µs/Div 20 MHz BW Figure 21. Output Ripple VOUT = 1.8 V Figure 22. Load Transient VOUT = 1.8 V 1.8 VIN=2.7V VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 1.80 1.7 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) 1.81 500 µs/Div 1.79 1.78 1.6 1.5 1.4 1.3 1.2 1.1 1.77 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 2.5 Figure 23. Line and Load Regulation VOUT = 1.8 V 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) C001 5.5 C002 Figure 24. DC Current Limit VOUT = 1.8 V, TA= 85°C Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 17 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com 8.2.3.3 VOUT = 2.5 V VIN VIN EN 100 2.5V VOUT CIN 90 VOUT 80 EFFICIENCY (%) VREF FB RT VCON COUT PGND RB SGND CVC 70 60 50 VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 40 CIN COUT CVC RT RB 10 P)86.3V 10 PF 86.3V 470 pF 86.3V 150 k: 1% 118 k: 1% 0805 X7R or X5R 0805 X7R or X5R 0603 X7R or X5R 0603 0603 30 20 0.0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 1.0 C003 Figure 26. Efficiency VOUT = 2.5 V Figure 25. Schematic VOUT = 2.5 V COUT = 10F 10V 0805 X5R VOUT RIPPLE COUT = 10F 10V 0805 X5R 50mV/Div OUTPUT VOLTAGE 10mV/Div LOAD CURRENT 500mA/Div 250MHz BW 1µs/Div 20 MHz BW Figure 28. Load Transient VOUT = 2.5 V Figure 27. Output Ripple VOUT = 2.5 V 1.8 VIN=3.3V VIN=3.6V VIN=5V VIN=5.5V 2.60 1.7 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) 2.65 500 µs/Div 2.55 2.50 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.45 0.0 0.2 0.4 0.6 0.8 1.0 LOAD CURRENT (A) Figure 29. Line and Load Regulation VOUT = 2.5 V 18 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) C004 5.0 5.5 C003 Figure 30. DC Current Limit VOUT = 2.5 V, TA= 85°C Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 8.2.3.4 VOUT = 3.3 V VIN VIN EN 100 3.3V VOUT CIN 90 VOUT 80 EFFICIENCY (%) VREF FB RT VCON COUT PGND RB SGND CVC 70 60 50 40 CIN COUT CVC RT RB 10 P)86.3V 10 PF 86.3V 470 pF 86.3V 118 k: 1% 150 k: 1% 0805 X7R or X5R 0805 X7R or X5R 0603 X7R or X5R 0603 0603 VIN=4V VIN=4.5V VIN=5V VIN=5.5V 30 20 0.0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 1.0 C001 Figure 32. Efficiency VOUT = 3.3 V Figure 31. Schematic VOUT = 3.3 V COUT = 10F 10V 0805 X5R VOUT RIPPLE COUT = 10F 10V 0805 X5R 50mV/Div OUTPUT VOLTAGE 10mV/Div LOAD CURRENT 500mA/Div 250MHz BW 1µs/Div 20 MHz BW Figure 34. Load Transient VOUT = 3.3 V 3.30 1.8 3.29 1.7 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) Figure 33. Output Ripple VOUT = 3.3 V 3.28 3.27 3.26 3.25 3.24 VIN=4V VIN=4.5V VIN=5V VIN=5.5V 3.23 3.22 0.0 0.2 0.4 0.6 0.8 500 µs/Div 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.0 LOAD CURRENT (A) 2.5 Figure 35. Line and Load Regulation VOUT = 3.3 V 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) C002 5.5 C004 Figure 36. DC Current Limit VOUT = 3.3 V, TA= 85°C Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 19 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com 9 Power Supply Recommendations 9.1 Voltage Range The voltage of the input supply must not exceed the Absolute Maximum Ratings and the Recommended Operating Conditions of the LMZ10501. 9.2 Current Capability The input supply must be able to supply the required input current to the LMZ10501 converter. The required input current depends on the application's minimum required input voltage (VIN-MIN), the required output power (VOUT x IOUT-MAX), and the converter efficiency (η). IIN = VOUT x IOUT-MAX / (VIN-MIN x η) (6) For example, for a design with 5-V minimum input voltage,1.8-V output, and 1-A maximum load, considering 82% conversion efficiency, the required input current at steady state is 0.439A. 9.3 Input Connection Long input connection cables can cause issues with the normal operation of any Buck converter. 9.3.1 Voltage Drops Using long input wires to connect the supply to the input of any converter adds impedance in series with the input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the converter is loaded. If the input voltage is near the minimum operating voltage, this added voltage drop can cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some bulk (i.e. electrolytic) capacitance at the input of the converter. 9.3.2 Stability The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in an under damped RLC network at the input of the Buck converter. This can cause oscillations on the input and instability. If long wires are used, it is recommended to add some electrolytic capacitance in parallel with the ceramic input capacitor. The electrolytic capacitor's ESR will improve the damping. Use an electrolytic capacitor with CELECTROLYTIC≥ 4xCCERAMIC and ESRELECTROLYTIC≈ √ (LCABLE / CCERAMIC) For example, two cables (one for VIN and one for GND), each 1 meter (~3ft) long with ~1.0mm diameter (18AWG), placed 1cm (~0.4in) apart will form a rectangular loop resulting in about 1.2µH of inductance. The inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 10µF ceramic input capacitor, the recommended parallel CELECTROLYTIC is ≥ 40 µF. Using a 47µF capacitor will be sufficient. The recommended ESRELECTROLYTIC≈ 0.35Ω or larger, based on about 1.2µH of inductance and 10µF of ceramic input capacitance. See application note SNVA489 for more details on input filter design. 20 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 10 Layout 10.1 Layout Guidelines The board layout of any DC-DC switching converter is critical for the optimal performance of the design. Bad PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still converts the voltage properly, the board layout can mean the difference between passing or failing EMI regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a path for the high di/dt switching current during each switching period. This loop should always be kept as short as possible when laying out a board for any Buck converter. The LMZ10501 integrates the inductor and simplifies the DC-DC converter board layout. Refer to the example layout in Figure 37. There are a few basic requirements to achieve a good LMZ10501 layout. 1. Place the input capacitor CIN as close as possible to the VIN and PGND pins. VIN (pin 7) and PGND (pin 6) on the LMZ10501 are next to each other which makes the input capacitor placement simple. 2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and SGND pins. The CVC capacitor (not RB) should be the component closer to the VCON pin, as shown in Figure 37. This allows for better bypass of the control voltage set at VCON. 3. Run the feedback trace (from VOUT to FB) away from noise sources. 4. Connect SGND to a quiet GND plane. 5. Provide enough PCB area for proper heatsinking. Refer to the Electrical Characteristics table for example θJA values for different board areas. Also, refer to AN-2020 for additional thermal design hints. Refer to the evaluation board user guide SNVU313 for a complete board layout example. 10.2 Layout Example RB RESISTOR RT RESISTOR HIGH di/dt LOOP KEEP IT SMALL EN VREF VCON VIN FB PGND SGND VOUT VIN INPUT CAPACITOR PGND VOUT FEEDBACK TRACE SGND CONNECTION TO QUIET PGND PLANE OUTPUT CAPACITOR VCON CAPACITOR Figure 37. Example Top Layer Board Layout Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 21 LMZ10501 SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 www.ti.com 10.3 Package Considerations Use the following recommendations when utilizing machine placement : • Use 1.06mm (42mil) or smaller nozzle size. The pick up area is the top of the inductor which is 1.6mm x 2mm. • Soft tip pick and place nozzle is recommended. • Add 0.05mm to the component thickness so that the device will be released 0.05mm (2mil) into the solder paste without putting pressure or splashing the solder paste. • Slow the pick arm when picking the part from the tape and reel carrier and when depositing the IC on the board. • If the machine releases the component by force, use minimum force or no more than 3 Newtons. For manual placement: • Use a vacuum pick up hand tool with soft tip head. • If vacuum pick up tool is not available, use non-metal tweezers and hold the part by sides. • Use minimal force when picking and placing the module on the board. • Using hot air station provides better temperature control and better controlled air flow than a heat gun. • Go to the video section at www.ti.com/product/lmz10501 for a quick video on how to solder rework the LMZ10501. 22 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 LMZ10501 www.ti.com SNVS677F – MAY 2011 – REVISED NOVEMBER 2014 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation • AN-2162 Simple Success With Conducted EMI From DC- DC Converters, SNVA489 • MZ10501SIL and LMZ10500SIL SIMPLE SWITCHER® Nano Module Evaluation Board, SNVU313 11.2 Trademarks SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMZ10501 23 PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMZ10501SH/NOPB OBSOLETE POS NQB 8 TBD Call TI Call TI -40 to 85 SP LMZ10501SHE/NOPB OBSOLETE POS NQB 8 TBD Call TI Call TI -40 to 85 SP LMZ10501SHX/NOPB OBSOLETE POS NQB 8 TBD Call TI Call TI -40 to 85 SP LMZ10501SILR ACTIVE uSiP SIL 8 3000 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 125 TXN5010EC (501 ~ DG) 9811 0501 0501 9811 DG LMZ10501SILT ACTIVE uSiP SIL 8 250 Green (RoHS & no Sb/Br) Call TI Level-3-260C-168 HR -40 to 125 TXN5010EC (501 ~ DG) 9811 0501 0501 9811 DG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 13-Jun-2015 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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