TAS5721 48-Pin TSSOP (DCA) www.ti.com SLOS739 – JULY 2012 Digital Audio Power Amplifier with EQ, DRC, 2.1 Support, and Headphone/Line Driver Check for Samples: TAS5721 FEATURES 1 • • Audio Input/Output – 10 W x 2 into 8 Ω With PVDD = 24 V – 8 W x 2 + 12 W x 1 into 8 Ω With PVDD = 24 V – Supports 2.0, Single Device 2.1, and Mono Modes – Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S) – Integrated DirectPath™ Headphone Amplifier and 2 VRMS Line Driver Audio/PWM Processing – Independent Channel Volume Controls With 24-dB to Mute in 0.5 dB Steps – Separate Dynamic Range Control for Satellite and Sub Channels – 21 Programmable Biquads for Speaker EQ – Programmable Two-Band Dynamic Range Control – Support for 3D Effects General Features – I2C™ Serial Control Interface Operational Without MCLK – Configurable I2C Address (0x34 or 0x36) – Automatic Sample Rate Detection – Thermal and Short-Circuit Protection – Wide PVDD Supply Range (4.5 V to 24 V) APPLICATIONS • LED/LCD TVs, Soundbar, Docking Stations, PC Speakers Output Power vs. PVDD in 2.0 Mode 15 2.0 BTL Mode TA = 25°C Output Power (W) • 23 10 5 THD+N = 1%, 4Ω THD+N = 10%, 4Ω THD+N = 1%, 6Ω THD+N = 10%, 6Ω THD+N = 1%, 8Ω THD+N = 10%, 8Ω 0 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 G001 DVDD DRVDD AVDD PVDD TAS5721 DRVDD MCLK Monitoring and Watchdog MCLK LRCLK Internal Regulation and Power Distribution Power-On Reset (POR) SCLK Sample Rate Auto-Detect SDIN PLL Digital Audio Processor (DAP) Open Loop 4 Channel PWM Amplifier Digital to PWM Converter (DPC) Serial Audio Port (SAP) Sample Rate Converter (SRC) Internal Voltage Supplies Sensing and Protection 3 Ch. PWM Modulator Noise Shaping Click and Pop Suppression SPK_OUTA Temperature Short Circuits PVDD Voltage Output Current SPK_OUTB Fault Notification SPK_OUTD SPK_OUTC Internal Register/State Machine Interface DRVDD 2 I C Control Port SCL SDA PDN RST Stereo Headphone Amplifier Charge Pump DR_CP DR_CN DR_VSS DR_INA DR_OUTA DR_OUTB DR_INB 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath, FilterPro are trademarks of Texas Instruments. I2C is a trademark of Philips Semiconductor Corp. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TAS5721 SLOS739 – JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The TAS5721 is an efficient, digital-input audio amplifier for driving 2.0 speaker systems configured as a bridge tied load (BTL), 2.1 systems with two satellite speakers and one subwoofer, or in PBTL systems driving a single speaker configured as a parallel bridge tied load (PBTL). One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data formats and sample rates. A fully programmable data path routes these channels to the internal speaker drivers. The TAS5721 is a slave-only device, receiving all clocks from external sources. The TAS5721 operates with a PWM carrier frequency between a 384-kHz switching rate and a 288-KHz switching rate, depending on the input sample rate. Oversampling, combined with a fourth-order noise shaper, provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. An integrated ground centered DirectPath™ combination headphone amplifier and 2VRMS line driver is integrated in the TAS5721. DVDD DRVDD AVDD PVDD TAS5721 DRVDD MCLK Monitoring and Watchdog MCLK LRCLK Internal Regulation and Power Distribution Power-On Reset (POR) SCLK Sample Rate Auto-Detect SDIN PLL Digital Audio Processor (DAP) Open Loop 4 Channel PWM Amplifier Digital to PWM Converter (DPC) Serial Audio Port (SAP) Sample Rate Converter (SRC) Internal Voltage Supplies Sensing and Protection 3 Ch. PWM Modulator Noise Shaping Click and Pop Suppression SPK_OUTA Temperature Short Circuits PVDD Voltage Output Current SPK_OUTB Fault Notification SPK_OUTD SPK_OUTC Internal Register/State Machine Interface DRVDD 2 I C Control Port SCL SDA PDN RST Stereo Headphone Amplifier Charge Pump DR_CP DR_CN DR_VSS DR_INA DR_OUTA DR_OUTB DR_INB Figure 1. DAP Process Structure 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 PIN ASSIGNMENT AND DESCRIPTIONS TAS5721 DCA Package (Top View) PGND 1 48 SPK_OUTB SPK_OUTA 2 47 BSTRPB BSTRPA 3 46 BSTRPC PVDD 4 45 SPK_OUTC TEST1 5 44 PGND TEST2 6 43 SPK_OUTD DR_INA 7 42 BSTRPD DR_OUTA 8 41 PVDD DR_OUTB 9 40 GVDD_REG DR_INB 10 39 DR_SD DR_VSS 11 38 SSTIMER DR_CN 12 PowerPAD DR_CP 13 37 AVDD_REG2 36 AGND DRVDD 14 35 DGND PLL_GND 15 34 DVDD PLL_FLTM 16 33 TEST3 PLL_FLTP 17 32 RST 31 NC AVDD_REG1 18 AVDD 19 30 SCL ADR/FAULT 20 29 SDA MCLK 21 28 SDIN OSC_RES 22 27 SCLK OSC_GND 23 26 LRCLK DVDD_REG 24 25 PDN Pin Out PIN NAME TYPE (1) TERMINATION DESCRIPTION NO. ADR/FAULT 20 DI/DO - Dual function terminal which sets the LSB of the I2C address to 0 if pulled to GND, 1 if pulled to DVDD. If configured to be a fault output by the methods described in I²C Address Selection and Fault Output, this terminal is pulled low when an internal fault occurs. A pull-up or pull-down resistor is required, as is shown in the Typical Application Circuit Diagrams. AGND 36 P - Ground reference for analog circuitry (2) AVDD 19 P - Power supply for internal analog circuitry AVDD_REG1 18 P - Voltage regulator derived from AVDD supply (3) AVDD_REG2 37 P - Voltage regulator derived from AVDD supply (3) BSTRPx 3, 42, 46, 47 P - Connection points for the bootstrap capacitors, which are used to create a power supply for the high-side gate drive of the device DGND 35 P - Ground reference for digital circuitry (2) DR_CN 12 P - Negative terminal for capacitor connection used in headphone amplifier and line driver charge pump DR_CP 13 P - Positive terminal for capacitor connection used in headphone amplifier and line driver charge pump DR_INx 7, 10 AI - Input for channel A or B of headphone amplifier or line driver (1) (2) (3) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output This terminal should be connected to the system ground This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 3 TAS5721 SLOS739 – JULY 2012 www.ti.com Pin Out (continued) DR_OUTx 8, 9 AO - Output for channel A or B of headphone amplifier or line driver DR_SD 39 DI - Places the headphone amplifier/line driver in shutdown when pulled low. DR_VSS 11 P - Negative supply generated by charge pump for ground centered headphone and line driver output DRVDD 14 P - Power supply for internal headphone and line driver circuitry DVDD 34 P - Power supply for the internal digital circuitry DVDD_REG 24 P - Voltage regulator derived from DVDD supply (3) GVDD_REG 40 P - Voltage regulator derived from PVDD supply (3) LRCLK 26 DI Pulldown Word select clock for the digital signal that is active on the input data line of the serial port MCLK 21 DI Pulldown Master clock used for internal clock tree and sub-circuit and state machine clocking NC 31 - - Not connected inside the device (all no connect terminals should be connected to ground) OSC_GND 23 P - Ground reference for oscillator circuitry (this terminal should be connected to the system ground) OSC_RES 22 AO - Connection point for oscillator trim resistor PDN 25 DI Pullup PGND 1 P - Ground reference for power device circuitry (4) PLL_FLTM 16 AI/AO - Negative connection point for the PLL loop filter components PLL_FLTP 17 AI/AO - Positive connection point for the PLL loop filter components PLL_GND 15 P - Ground reference for PLL circuitry (this terminal should be connected to the system ground) PowerPAD - P - Thermal and ground pad thatprovides both an electrical connection to the ground plane and a thermal path to the PCB for heat dissipation. This pad must be grounded to the system ground. PVDD 4, 41 P - Power supply for internal power circuitry RST 32 DI Pullup SCL 30 DI - SCLK 27 DI Pulldown SDA 29 DI/DO - SDIN 28 DI Pulldown SPK_OUTx 2, 43, 45, 48 AO - Speaker amplifier outputs SSTIMER 38 AI - Connection point for the capacitor that is used by the ramp timing circuit, as described in Output Mode and MUX Selection TEST1 5 DO - Used by TI for testing during device production (this terminal must be left floating) TEST2 6 DO - Used by TI for testing during device production (this terminal must be left floating) TEST3 33 DI - Used by TI for testing during device production (this terminal must be connected to GND) (4) 4 Quick powerdown of the device that is used upon an unexpected loss of PVDD or DVDD power supply in order to quickly transition the outputs of the speaker amplifier to a 50/50 duty cycle. This quick powerdown feature avoids the audible anamolies that would occur as a result of loss of either of the supplies. If this pin is used to place the device into quick powerdown mode, the RST pin of the device must be toggled before the device is brought out of quick powerdown. Places the device in reset when pulled low I2C serial control port clock Bit clock for the digital signal that is active on the input data line of the serial data port I2C serial control port data Data line to the serial data port This terminal should be connected to the system ground Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 TYPICAL APPLICATION CIRCUITS R2 10K 0402 C1 1.5 µfd/10 V 0402 X5R R1 R3 10K 0402 0 0402 C2 DNP C3 DNP 220 pfd/50 V 0402 COG HEADPHONES FOR PWM INPUT ONLY 1000 pfd/50 V 0402 COG GND STUFF OPTION R5 L1 10K 0402 C4 1.5 µfd/10 V 0402 X5R R4 R6 10K 0402 C5 C6 DNP C27 220 pfd/50 V 0402 COG C7 0 0402 U1 0.033 µfd/50 V 0402 X7R 1 PVDD DNP 2 1000 pfd/50 V 0402 COG 3 + GND C8 C9 4 220 µfd/35 V M 0.1 µfd/50 V 0402 X7R 5 SPK_OUTB PGND BSTRPB SPK_OUTA AVDD C12 C13 10 µfd/6.3 V 0603 X5R 1 µfd/10 V 0402 X5R GND 6 GND 7 8 9 GND 10 0.047 µfd/16 V 0402 X7R System Processor and Associated Components R7 470 0402 TEST2 SPK_OUTC PGND DR_INA SPK_OUTD DR_OUTA BSTRPD 4700 pfd/25 V 0402 X7R 13 14 R8 15 C17 4700 pfd/25 V 0402 X7R 17 18 19 AVDD C19 10 µfd/6.3 V 0603 X5R 0.1 µfd/16 V 0402 X7R GND 21 R9 22 18.20K 0402 GND 24 GND GND 0.33 µfd/50 V 0805 X7R 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY 18 0603 DGND PLL_FLTM DVDD PLL_FLTP TEST3 AVDD_REG1 RST AVDD ADR/FAULT SCL MCLK SDA SDIN OSC_RES LRCLK OSC_GND PDN DVDD_REG GND OUTPUTS C30 GND GND R16 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY 18 0603 0.33 µfd/50 V 0805 X7R GND C40 0.33 µfd/50 V 0805 X7R GND STUFF OPTION NOTE 38 PVDD GND 0.1 µfd/16 V 0402 X7R 35 C32 0.1 µfd/50 V 0402 X7R 37 36 C39 C36 0.33 µfd/50 V 0805 X7R L4 C26 AVDD_REG2 PLL_GND C38 + C31 220 µfd/35 V M GND GND GND 34 33 32 31 30 GROUND REFERENCED CAPS REQUIRED IF BD MODULATION IS USED DVDD C34 C33 0.1 µfd/16 V 0402 X7R 10 µfd/6.3 V 0603 X5R GND GND 29 28 27 26 25 TAS5721DCA C20 GND 15 µH/3.5 A A7503AY 39 2200 pfd/50 V 0402 X7R SCLK 23 15k 4.7 µfd/6.3 V 0402 X5R C23 40 DRVDD NC 20 GND R15 41 DR_CP AGND 16 0.047 µfd/16 V 0402 X7R C18 SSTIMER 0.33 µfd/50 V 0805 X7R GND 18 0603 C25 1 µfd/10 V 0402 X5R GND C16 42 C24 DR_SD R14 330 pfd/50 V 0402 COG C29 43 DR_VSS DR_CN 0.33 µfd/50 V 0805 X7R L3 1 µfd/25 V 0603 X5R 12 C28 GND 0.033 µfd/50 V 0402 X7R GVDD_REG C37 C35 44 DR_OUTB DR_INB 18 0603 45 C11 GND 470 0402 C22 TEST1 1 µfd/10 V 0402 X5R GND 46 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY L2 0.033 µfd/50 V 0402 X7R PVDD 11 C15 C21 0.033 µfd/50 V 0402 X7R PVDD C10 C14 47 BSTRPA BSTRPC GND GND 48 R13 GND HTSSOP48-DCA GND U1 HTSSOP48-DCA PowerPAD GND Figure 2. Typical Application Circuit for Mono (PBTL) Configuration Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 5 TAS5721 SLOS739 – JULY 2012 www.ti.com R2 10K 0402 C1 1.5 µfd/10 V 0402 X5R R1 R3 10K 0402 C2 DNP C3 DNP 220 pfd/50 V 0402 COG 0 0402 HEADPHONES FOR PWM INPUT ONLY 1000 pfd/50 V 0402 COG GND STUFF OPTION R5 L1 10K 0402 C4 1.5 µfd/10 V 0402 X5R R4 R6 10K 0402 C5 C6 DNP C27 220 pfd/50 V 0402 COG C7 0 0402 U1 0.033 µfd/50 V 0402 X7R 1 PVDD DNP 2 1000 pfd/50 V 0402 COG 3 + GND 4 C8 C9 220 µfd/35 V M 0.1 µfd/50 V 0402 X7R PGND SPK_OUTB SPK_OUTA BSTRPB GND AVDD C12 C13 10 µfd/6.3 V 0603 X5R 1 µfd/10 V 0402 X5R GND 6 GND GND DR_INA 7 DR_OUTA 8 DR_OUTB 9 DR_INB C10 10 11 0.047 µfd/16 V 0402 X7R System Processor and Associated Components C15 470 0402 14 R8 15 C17 17 0.047 µfd/16 V 0402 X7R 18 19 AVDD C19 0.1 µfd/16 V 0402 X7R GND SPK_OUTD DR_OUTA BSTRPD DR_SD SSTIMER 42 21 R9 GND 22 18.20K 0402 GND DGND DVDD PLL_FLTP TEST3 AVDD_REG1 RST AVDD ADR/FAULT SCL MCLK SDA SDIN OSC_RES LRCLK OSC_GND PDN DVDD_REG C38 0.33 µfd/50 V 0805 X7R R15 330 pfd/50 V 0402 COG C24 C30 1 µfd/25 V 0603 X5R 330 pfd/50 V 0402 COG R16 GND GND 18 0603 39 GND C39 C36 0.33 µfd/50 V 0805 X7R 15 µH/3.5 A A7503AY 0.33 µfd/50 V 0805 X7R GND C40 0.33 µfd/50 V 0805 X7R GND OUTPUTS STUFF OPTION NOTE 38 PVDD GND 0.1 µfd/16 V 0402 X7R 35 C32 0.1 µfd/50 V 0402 X7R 37 36 15 µH/3.5 A A7503AY 18 0603 L4 C26 PLL_FLTM 15 µH/3.5 A A7503AY + C31 220 µfd/35 V M GND GND GND 34 33 32 31 30 GROUND REFERENCED CAPS REQUIRED IF BD MODULATION IS USED DVDD C34 C33 0.1 µfd/16 V 0402 X7R 10 µfd/6.3 V 0603 X5R GND GND 29 28 27 26 25 TAS5721DCA C20 GND GND 40 DRVDD SCLK 23 24 4.7 µfd/6.3 V 0402 X5R C29 C23 2200 pfd/50 V 0402 X7R AVDD_REG2 0.33 µfd/50 V 0805 X7R GND 18 0603 41 DR_CP PLL_GND 0.33 µfd/50 V 0805 X7R L3 43 DR_VSS DR_CN C37 C35 44 0.033 µfd/50 V 0402 X7R DR_INB R14 330 pfd/50 V 0402 COG 45 DR_OUTB NC 20 15k GND PGND DR_INA AGND 16 4700 pfd/25 V 0402 X7R 10 µfd/6.3 V 0603 X5R SPK_OUTC 18 0603 C25 13 C18 TEST2 1 µfd/10 V 0402 X5R GND C16 C28 GND 0.033 µfd/50 V 0402 X7R GVDD_REG 12 GND 470 0402 C22 C11 4700 pfd/25 V 0402 X7R R7 46 TEST1 1 µfd/10 V 0402 X5R GND C21 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY L2 0.033 µfd/50 V 0402 X7R PVDD PVDD C14 47 BSTRPA BSTRPC 5 GND 48 R13 GND HTSSOP48-DCA GND U1 HTSSOP48-DCA PowerPAD GND Figure 3. Typical Application Diagram for 2.0 Configuration 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 R2 10K 0402 C1 1.5 µfd/10 V 0402 X5R R1 R3 10K 0402 C2 DNP C3 DNP 220 pfd/50 V 0402 COG 0 0402 HEADPHONES FOR PWM INPUT ONLY 1000 pfd/50 V 0402 COG GND STUFF OPTION R5 L1 10K 0402 C4 1.5 µfd/10 V 0402 X5R R4 R6 10K 0402 C5 C6 DNP C27 220 pfd/50 V 0402 COG C7 0 0402 U1 0.033 µfd/50 V 0402 X7R 1 PVDD DNP 2 1000 pfd/50 V 0402 COG 3 + GND 4 C8 C9 220 µfd/35 V M 0.1 µfd/50 V 0402 X7R PGND SPK_OUTB SPK_OUTA BSTRPB GND AVDD C12 C13 10 µfd/6.3 V 0603 X5R 1 µfd/10 V 0402 X5R GND 6 GND 7 8 9 GND 10 470 0402 TEST2 SPK_OUTC PGND DR_INA SPK_OUTD DR_OUTA BSTRPD 12 14 R8 15 4700 pfd/25 V 0402 X7R 17 18 19 AVDD C19 10 µfd/6.3 V 0603 X5R 0.1 µfd/16 V 0402 X7R GND 21 R9 GND 22 18.20K 0402 SSTIMER 23 24 C38 0.33 µfd/50 V 0805 X7R GND GND R15 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY 18 0603 C39 C36 0.33 µfd/50 V 0805 X7R 0.33 µfd/50 V 0805 X7R L4 C24 C30 1 µfd/25 V 0603 X5R 330 pfd/50 V 0402 COG R16 40 GND GND GND 15 µH/3.5 A A7503AY C40 18 0603 0.33 µfd/50 V 0805 X7R 39 GND STUFF OPTION NOTE 38 PVDD GND C26 AVDD_REG2 PLL_GND PLL_FLTM DGND PLL_FLTP DVDD TEST3 AVDD_REG1 RST AVDD ADR/FAULT SCL MCLK SDA SDIN OSC_RES OSC_GND LRCLK PDN DVDD_REG 0.1 µfd/50 V 0402 X7R 37 36 0.1 µfd/16 V 0402 X7R 35 C32 + C31 220 µfd/35 V M GND GND GND 34 33 32 31 30 GROUND REFERENCED CAPS REQUIRED IF BD MODULATION IS USED DVDD C34 C33 0.1 µfd/16 V 0402 X7R 10 µfd/6.3 V 0603 X5R GND GND 29 28 STUFF OPTION PVDD PVDD 27 26 25 + R17 15K 0402 1/16W TAS5721DCA C20 GND C29 C23 2200 pfd/50 V 0402 X7R SCLK 15k 4.7 µfd/6.3 V 0402 X5R 15 µH/3.5 A A7503AY 18 0603 41 DRVDD NC 20 GND GND 42 DR_CP AGND 16 0.047 µfd/16 V 0402 X7R C18 DR_SD R14 330 pfd/50 V 0402 COG GND C25 13 C17 DR_CN 0.33 µfd/50 V 0805 X7R 0.33 µfd/50 V 0805 X7R L3 43 DR_VSS 1 µfd/10 V 0402 X5R GND C16 C28 GND 0.033 µfd/50 V 0402 X7R GVDD_REG C37 C35 44 DR_OUTB DR_INB 18 0603 45 C11 GND 470 0402 C22 0.033 µfd/50 V 0402 X7R 1 µfd/10 V 0402 X5R GND 4700 pfd/25 V 0402 X7R R7 System Processor and Associated Components C15 46 TEST1 PVDD 11 0.047 µfd/16 V 0402 X7R C21 330 pfd/50 V 0402 COG 15 µH/3.5 A A7503AY L2 0.033 µfd/50 V 0402 X7R PVDD C10 C14 47 BSTRPA BSTRPC 5 GND 48 R13 GND HTSSOP48-DCA GND U1 HTSSOP48-DCA PowerPAD 220 µfd/35 V M + R18 15K 0402 1/16W C42 220 µfd/35 V M GND PVDD OUTPUTS C41 GND PVDD GND + R19 15K 0402 1/16W + R20 15K 0402 1/16W GND C43 220 µfd/35 V M C44 220 µfd/35 V M GND SPLIT CAP Figure 4. Typical Application Diagram for 2.1 Configuration Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 7 TAS5721 SLOS739 – JULY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). Supply voltage (1) VALUE UNIT DVDD, AVDD, DRVDD –0.3 to 3.6 V PVDD –0.3 to 30 V –0.3 to DRVDD + 6 V V DR_INx 3.3-V digital input Input voltage –0.5 to DVDD + 0.5 5-V tolerant (2) digital input (except MCLK) –0.5 to DVDD + 2.5 (3) 5-V tolerant MCLK input –0.5 to AVDD + 2.5 (3) 32 (4) SPK_OUTx to GND BSTRPx to GND 39 Operating free-air temperature Storage temperature range, Tstg (1) V V (4) V 0 to 85 °C –40 to 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. 5-V tolerant inputs are PDN, RST, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL. Maximum pin voltage should not exceed 6 V. DC voltage + peak AC waveform measured at the pin should be below the allowed limit for all conditions. (2) (3) (4) RECOMMENDED OPERATING CONDITIONS MIN NOM MAX xVDD Digital, analog, headphone supply voltage 3 3.3 3.6 V PVDD Half-bridge supply voltage 8 26.4 (1) V VIH High-level input voltage 5-V tolerant VIL Low-level input voltage 5-V tolerant TA Operating ambient temperature range Operating junction temperature range TJ (2) UNIT 2 V 0.8 V 0 85 °C 0 125 °C RSPK (SE, BTL, and PBTL) Minimum Supported Speaker Impedance Output filter: L = 15 μH, C = 330 nF Lo(BTL) Output-filter inductance Minimum output inductance under short-circuit condition RHP Headphone mode load impedance 16 32 Ω RLD Line-diver mode load impedance 0.6 10 kΩ (1) (2) 4 Ω 8 μH 10 For operation at PVDD levels greater than 18 V, the modulation limit must be set to 93.8% via the control port register 0x10. Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. ELECTRICAL CHARACTERISTICS I/O Pin Characteristics PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER VOH High-level output voltage ADR/FAULT and SDA TEST CONDITIONS MIN IOH = –4 mA DVDD = AVDD = 3 V 2.4 TYP MAX V VOL Low-level output voltage IOL = 4 mA DVDD = AVDD = 3 V 0.5 IIL Low-level input current VI < VIL ; DVDD = AVDD = 3.6 V 75 VI > VIH ; DVDD = AVDD = 3.6 V 75 Digital Inputs IIH 8 High-level input current Submit Documentation Feedback UNIT μA Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 I/O Pin Characteristics (continued) PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS IDD 3.3 V supply current 3.3 V supply voltage (DVDD, AVDD) tw(RST) Pulse duration, RST active RST td(I2C_ready) Time before the I2C port is able communicate after RST goes high TYP MAX Normal mode MIN 48 70 Reset (RST = low, PDN = high, DR_SD = low) 21 38 UNIT mA μs 100 12 ms RST tw(RST) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C. T0421-01 NOTE: On power up, it is recommended that the TAS5721 RST be held LOW for at least 100 μs after DVDD has reached 3 V. NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH). Figure 5. Reset Timing Master Clock Characteristics (1) PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER fMCLK tr(MCLK) / tf(MCLK) (1) TEST CONDITIONS MIN MCLK frequency 2.8224 MCLK duty cycle 40% Rise/fall time for MCLK TYP 50% MAX UNIT 24.576 MHz 60% 5 ns For clocks related to the serial audio port, please see Serial Audio Port Timing Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 9 TAS5721 SLOS739 – JULY 2012 www.ti.com I2C Serial Control Port Requirements and Specifications PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 tw(L) Pulse duration, SCL low 1.3 tr Rise time, SCL and SDA 300 ns tf Fall time, SCL and SDA 300 ns tsu1 Setup time, SDA to SCL th1 Hold time, SCL to SDA t(buf) μs μs 100 ns 0 ns Bus free time between stop and start conditions 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs CL Load capacitance for each bus line 400 tw(H) tw(L) pF tf tr SCL tsu1 th1 SDA T0027-01 Figure 6. SCL and SDA Timing SCL t(buf) th2 tsu2 tsu3 SDA Start Condition Stop Condition T0028-01 Figure 7. Start and Stop Conditions Timing 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Serial Audio Port Timing PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). TEST CONDITIONS PARAMETER CL = 30 pF MIN TYP 1.024 MAX UNIT 12.288 MHz fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% SCLK rising edges between LRCLK rising edges kHz 32 64 SCLK edges –1/4 1/4 SCLK period t(edge) LRCLK clock edge with respect to the falling edge of SCLK tr/tf Rise/fall time for SCLK/LRCLK 8 ns LRCLK allowable drift before LRCLK reset 4 MCLK Periods tr tf SCLK (Input) t(edge) th1 tsu1 LRCLK (Input) th2 tsu2 SDIN T0026-04 Figure 8. Serial Audio Port Timing Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 11 TAS5721 SLOS739 – JULY 2012 www.ti.com Speaker Amplifier Characteristics TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER PoSPK (BTL) PoSPK (PBTL) PoSPK (SE) THD+N ICN TEST CONDITIONS Power output per channel of speaker amplifier when used in BTL mode (1) Power output per channel of speaker amplifier when used in PBTL mode (1) Power output per channel of speaker amplifier when used in SE mode (1) Total harmonic distortion + noise Idle channel noise Crosstalk (2) PVDD = 12 V, RSPK = 8Ω, 10% THD+N, 1-kHz input signal 8.8 PVDD = 12 V, RSPK = 8Ω, 7% THD+N, 1-kHz input signal 8.3 PVDD = 8 V, RSPK = 8Ω, 10% THD+N, 1-kHz input signal 4 PVDD = 8 V, RSPK = 8Ω, 7% THD+N, 1-kHz input signal 3.8 PVDD = 12 V, RSPK = 4Ω, 10% THD+N, 1-kHz input signal 10 PVDD = 12 V, RSPK = 4Ω, 7% THD+N, 1-kHz input signal 10 PVDD = 18 V, RSPK = 4Ω, 1-kHz input signal 10 PVDD = 12 V, RSPK = 4 Ω, 10% THD+N, 1-kHz input signal 4.3 PVDD = 24 V, RSPK = 4 Ω, 10% THD+N, 1-kHz input signal 5.5 MAX UNIT W PVDD = 18 V, PO = 1 W 0.07 PVDD = 12 V, PO = 1 W 0.11 PVDD = 8 V, PO = 1 W 0.2 A-weighted 61 μV PO = 1 W, f = 1 kHz (BD Mode), PVDD = 24 V 58 dB PO =1 W, f = 1 kHz (AD Mode), PVDD = 24 V 48 dB 106 dB A-weighted, f = 1 kHz, maximum power at THD < 1% Signal-to-noise ratio fPWM Output switching frequency IPVDD Supply current rDS(on) Drain-to-source resistance (for each of the Low-Side and High- TJ = 25°C, includes metallization resistance Side Devices) RPD Internal pulldown resistor at the Connected when drivers are in the high-impedance output of each half-bridge state to provide bootstrap capacitor charge. 11.025/22.05/44.1-kHz data rate ±2% 48/24/12/8/16/32-kHz data rate ±2% Normal mode 12 TYP 10 SNR (1) (2) MIN PVDD = 18 V, RSPK = 8Ω, 1-kHz input signal No load (PVDD) Reset (RST = low, PDN = high) % 352.8 kHz 384 32 50 5 8 mA 200 mΩ 3 kΩ Power levels are thermally limited. SNR is calculated relative to 0-dBFS input level. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Headphone Amplifier and Line Driver Characteristics TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS PoHP Power output per channel of headphone amplifier DRVDD = 3.3 V (RHP = 32; THD = 1%) AVDR Gain for headphone amplifier and line driver Adjustable through Rin and Rfb SNRHP SNRLD MIN TYP MAX UNIT 50 mW - dB Signal-to-noise ratio (headphone mode) Rhp = 32 101 dB Signal-to-noise ratio (line driver mode) 105 dB 2-VRMS output Protection Characteristics TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application Circuit diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vuvp(fall) Undervoltage protection limit PVDD falling 4 Vuvp(rise) Undervoltage protection limit PVDD rising 4.1 V V OTE Overtemperature error threshold 150 °C ΔOTE Variation in overtemperature detection circuit ±15 °C IOCE Overcurrent limit protection threshold 3.0 A tOCE Overcurrent response time 150 ns THERMAL CHARACTERISTICS TAS5721 THERMAL METRIC (1) DCA UNITS 48 PINS θJA Junction-to-ambient thermal resistance (2) 27.9 θJCtop Junction-to-case (top) thermal resistance (3) 20.7 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) 6.7 (7) 1.1 θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 13 0.3 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 13 TAS5721 SLOS739 – JULY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS SPACER SPACER OUTPUT POWER vs PVDD IN 2.1 MODE SPACER SPACER OUTPUT POWER vs PVDD IN PBTL MODE 8 25 PBTL Mode TA = 25°C 2.1 SE Mode TA = 25°C Output Power (W) Output Power (W) 20 5 8 10 12 14 16 18 Supply Voltage (V) 20 22 10 THD+N = 1%, 4Ω THD+N = 10%, 4Ω THD+N = 1%, 6Ω THD+N = 10%, 6Ω THD+N = 1%, 8Ω THD+N = 10%, 8Ω 5 THD+N = 1%, 2x8+8Ω THD+N = 10%, 2x8+8Ω THD+N = 1%, 2x8+4Ω THD+N = 10%, 2x8+4Ω 0 15 0 24 8 10 12 14 16 18 Supply Voltage (V) 20 22 G002 G003 Figure 9. Figure 10. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN 2.0 MODE WITH PVDD = 12 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY in 2.0 MODE WITH PVDD = 18 V 10 10 2.0 BTL Mode PVDD = 12V PO = 1W TA = 25°C 2.0 BTL Mode PVDD = 18V PO = 1W TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 RL = 4Ω RL = 6Ω RL = 8Ω 0.001 20 100 RL = 4Ω RL = 6Ω RL = 8Ω 1k Frequency (Hz) 10k 20k 0.001 20 100 1k Frequency (Hz) G004 Figure 11. 14 24 10k 20k G005 Figure 12. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN 2.0 MODE WITH PVDD = 24 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FEQUENCY IN 2.1 MODE WITH PVDD = 12 V 10 10 2.0 BTL Mode PVDD = 24V PO = 1W TA = 25°C 2.1 SE Mode PVDD = 12V PO = 1W TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 RL = 2x8+8Ω RL = 2x8+4Ω RL = 2x4+8Ω RL = 2x4+4Ω RL = 4Ω RL = 6Ω RL = 8Ω 0.001 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) 10k G006 G007 Figure 13. Figure 14. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN 2.1 MODE WITH PVDD = 18 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN 2.1 MODE WITH PVDD = 24 V 10 10 2.1 SE Mode PVDD = 18V PO = 1W TA = 25°C 2.1 SE Mode PVDD = 24V PO = 1W TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 RL = 2x8+8Ω RL = 2x8+4Ω RL = 2x4+8Ω RL = 2x4+4Ω 0.001 20k 20 100 RL = 2x8+8Ω RL = 2x8+4Ω RL = 2x4+8Ω 1k Frequency (Hz) 10k 20k 0.001 20 100 1k Frequency (Hz) 10k G009 Figure 15. 20k G009 Figure 16. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 15 TAS5721 SLOS739 – JULY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN PBTL MODE WITH PVDD = 12 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN PBTL MODE WITH PVDD = 18 V 10 10 PBTL Mode PVDD = 12V PO = 1W TA = 25°C PBTL Mode PVDD = 18V PO = 1W TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 RL = 4Ω RL = 6Ω RL = 8Ω 0.001 20 100 RL = 4Ω RL = 6Ω RL = 8Ω 1k Frequency (Hz) 10k 20k 0.001 20 100 1k Frequency (Hz) 10k 20k G010 G011 Figure 17. Figure 18. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY IN PBTL MODE WITH PVDD = 24 V SPACER SPACER 2.0 IDLE CHANNEL NOISE vs PVDD 10 60 2.0 BTL Mode TA = 25°C PBTL Mode PVDD = 24V PO = 1W TA = 25°C 50 Idle Channel Noise (µV) THD+N (%) 1 0.1 40 30 0.01 20 RL = 4Ω RL = 6Ω RL = 8Ω 0.001 20 100 RL = 4Ω RL = 6Ω RL = 8Ω 1k Frequency (Hz) 10k 20k 10 8 10 12 14 16 18 Supply Voltage (V) G012 Figure 19. 16 20 22 24 G013 Figure 20. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER 2.1 IDLE CHANNEL NOISE vs PVDD SPACER SPACER PBTL IDLE CHANNEL NOISE vs PVDD 60 45 2.1 SE Mode TA = 25°C PBTL Mode TA = 25°C 55 40 Idle Channel Noise (µV) Idle Channel Noise (µV) 50 35 30 25 45 40 35 30 20 25 15 10 RL = 2x8+8Ω RL = 2x4+8Ω RL = 2x4+4Ω 8 10 12 14 16 18 Supply Voltage (V) 20 22 20 15 24 RL = 4Ω RL = 8Ω 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 G014 G015 Figure 21. Figure 22. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.0 MODE WITH PVDD = 12 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.0 MODE WITH PVDD = 18 V 10 10 2.0 BTL Mode PVDD = 12V f = 1kHz TA = 25°C 2.0 BTL Mode PVDD = 18V f = 1kHz TA = 25°C THD+N (%) 1 THD+N (%) 1 0.1 0.1 RL = 4Ω RL = 6Ω RL = 8Ω 0.01 0.01 0.1 1 Output Power (W) RL = 4Ω RL = 6Ω RL = 8Ω 10 0.01 0.01 0.1 1 Output Power (W) G016 Figure 23. 10 G017 Figure 24. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 17 TAS5721 SLOS739 – JULY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.0 MODE WITH PVDD = 24 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.1 MODE WITH PVDD = 12 V 10 10 2.0 BTL Mode PVDD = 24V f = 1kHz TA = 25°C 2.1 SE Mode PVDD = 12V f = 1kHz TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 RL = 4Ω RL = 6Ω RL = 8Ω 0.01 0.01 0.1 1 Output Power (W) RL = 2x8+8Ω RL = 2x4+8Ω RL = 2x4+4Ω 0.001 0.01 10 0.1 Output Power (W) 1 5 G018 G019 Figure 25. Figure 26. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.1 MODE WITH PVDD = 18 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN 2.1 MODE WITH PVDD = 24 V 10 10 2.1 SE Mode PVDD = 18V f = 1kHz TA = 25°C 2.1 SE Mode PVDD = 24V f = 1kHz TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 RL = 2x8+8Ω RL = 2x4+8Ω RL = 2x4+4Ω 0.001 0.01 0.1 Output Power (W) 1 RL = 2x8+8Ω RL = 2x4+8Ω 5 0.001 0.01 0.1 Output Power (W) G020 Figure 27. 18 1 5 G021 Figure 28. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN PBTL MODE WITH PVDD = 12 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN PBTL MODE WITH PVDD = 18 V 10 10 PBTL Mode PVDD = 12V f = 1kHz TA = 25°C PBTL Mode PVDD = 18V f = 1kHz TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 RL = 4Ω RL = 6Ω RL = 8Ω 0.001 0.01 0.1 1 Output Power (W) 10 RL = 4Ω RL = 6Ω RL = 8Ω 20 0.001 0.01 0.1 1 Output Power (W) 10 20 G022 G023 Figure 29. Figure 30. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER IN PBTL MODE WITH PVDD = 24 V SPACER SPACER EFFICIENCY vs OUTPUT POWER IN 2.0 MODE 10 100 PBTL Mode PVDD = 24V f = 1kHz TA = 25°C 90 80 1 Efficiency (%) THD+N (%) 70 0.1 60 50 40 30 PVDD = 12V PVDD = 18V PVDD = 24V 0.01 20 RL = 4Ω RL = 6Ω RL = 8Ω 0.001 0.01 0.1 1 Output Power (W) 10 10 20 0 0 5 2.0 BTL Mode RL = 8Ω TA = 25°C All Channels Driven 10 15 Total Output Power (W) G024 20 G025 All channels driven Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 19 TAS5721 SLOS739 – JULY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER EFFICIENCY vs OUTPUT POWER IN 2.1 MODE 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) SPACER SPACER EFFICIENCY vs OUTPUT POWER IN 2.1 MODE 50 40 30 40 30 PVDD = 12V PVDD = 18V PVDD = 24V 20 10 0 50 0 5 2.1 SE Mode RL = 2x8+8Ω TA = 25°C All Channels Driven 10 15 20 Total Output Power (W) 25 PVDD = 12V PVDD = 18V PVDD = 24V 20 10 0 30 0 5 2.1 SE Mode RL = 2x4+8Ω TA = 25°C All Channels Driven 10 15 20 Total Output Power (W) 25 30 G026 G027 All channels driven Figure 33. Figure 34. SPACER SPACER EFFICIENCY vs OUTPUT POWER IN PBTL MODE SPACER SPACER EFFICIENCY vs OUTPUT POWER IN PBTL MODE 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) All channels driven 50 40 30 40 30 PVDD = 12V PVDD = 18V PVDD = 24V 20 10 0 50 0 5 PBTL Mode RL = 8Ω TA = 25°C All Channels Driven 10 15 20 Total Output Power (W) 25 PVDD = 12V PVDD = 18V PVDD = 24V 20 10 30 0 0 5 10 15 20 Total Output Power (W) G029 All channels driven 25 30 G030 All channels driven Figure 35. 20 PBTL Mode RL = 6Ω TA = 25°C All Channels Driven Figure 36. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER CROSSTALK vs FREQUENCY IN 2.0 MODE SPACER SPACER CROSSTALK vs FREQUENCY IN 2.0 MODE 0 0 2.0 BTL Mode PO = 1W PVDD = 12V RL = 4Ω TA = 25°C −10 −20 Right to Left Left to Right −20 Right to Left Left to Right −30 Crosstalk (dB) Crosstalk (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 2.0 BTL Mode PO = 1W PVDD = 12V RL = 8Ω TA = 25°C −10 20 100 1k Frequency (Hz) 10k 20k −100 20 100 1k Frequency (Hz) 10k 20k G032 G033 Figure 37. Figure 38. SPACER SPACER CROSSTALK vs FREQUENCY IN 2.0 MODE SPACER SPACER CROSSTALK vs FREQUENCY IN 2.0 MODE 0 0 2.0 BTL Mode PO = 1W PVDD = 24V RL = 4Ω TA = 25°C −10 −20 Right to Left Left to Right −20 Right to Left Left to Right −30 Crosstalk (dB) Crosstalk (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 2.0 BTL Mode PO = 1W PVDD = 24V RL = 8Ω TA = 25°C −10 20 100 1k Frequency (Hz) 10k 20k −100 20 100 1k Frequency (Hz) 10k G034 Figure 39. 20k G035 Figure 40. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 21 TAS5721 SLOS739 – JULY 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER SPACER CROSSTALK vs FREQUENCY IN 2.1 MODE SPACER SPACER CROSSTALK vs FREQUENCY IN 2.1 MODE 0 0 2.1 SE Mode PO = 1W PVDD = 12V RL = 2x8+8Ω TA = 25°C −10 −20 Right to Left Left to Right −20 Right to Left Left to Right −30 Crosstalk (dB) Crosstalk (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 2.1 SE Mode PO = 1W PVDD = 12V RL =2x4+8Ω TA = 25°C −10 20 100 1k Frequency (Hz) 10k 20k −100 20 100 1k Frequency (Hz) 10k 20k G036 G037 Figure 41. Figure 42. SPACER SPACER CROSSTALK vs FREQUENCY IN 2.1 MODE SPACER SPACER CROSSTALK vs FREQUENCY IN 2.1 MODE 0 0 2.1 SE Mode PO = 1W PVDD = 24V RL = 2x8+8Ω TA = 25°C −10 −20 Right to Left Left to Right −20 Right to Left Left to Right −30 Crosstalk (dB) Crosstalk (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 2.1 SE Mode PO = 1W PVDD = 24V RL =2x4+8Ω TA = 25°C −10 20 100 1k Frequency (Hz) 10k 20k −100 20 100 1k Frequency (Hz) G038 Figure 43. 22 10k 20k G039 Figure 44. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 HEADPHONE TYPICAL CHARACTERISTICS SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY HEADPHONE WITH DRVDD = 3.3 V SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY HEADPHONE WITH DRVDD = 3.3 V 10 10 Driver DRVDD = 3.3V VO = 0.5Vrms TA = 25°C Driver DRVDD = 3.3V VO = 1Vrms TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 RL = 16Ω RL = 32Ω 0.001 20 100 RL = 5kΩ RL = 10kΩ 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) 10k G040 20k G041 Figure 45. Figure 46. SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER HEADPHONE WITH DRVDD = 3.3 V 10 Driver DRVDD = 3.3V f = 1kHz TA = 25°C THD+N (%) 1 0.1 0.01 RL = 16Ω RL = 32Ω 0.001 0.001 0.01 Output Power (W) 0.1 G042 Figure 47. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 23 TAS5721 SLOS739 – JULY 2012 www.ti.com LINE DRIVER TYPICAL CHARACTERISTICS SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE HEADPHONE WITH DRVDD = 3.3 V SPACER SPACER CROSSTALK vs FREQUENCY HEADPHONE WITH DRVDD = 3.3 V 10 0 Driver DRVDD = 3.3V f = 1kHz TA = 25°C Driver VO = 1Vrms DRVDD = 3.3V RL = 5kΩ TA = 25°C −10 −20 1 Right to Left Left to Right Crosstalk (dB) THD+N (%) −30 0.1 −40 −50 −60 −70 0.01 −80 −90 RL = 5kΩ RL = 10kΩ 0.001 0.01 0.1 Output Voltage (V) 1 4 −100 20 100 1k Frequency (Hz) 10k 20k G043 G044 Figure 48. Figure 49. SPACER SPACER CROSSTALK vs FREQUENCY HEADPHONE WITH DRVDD = 3.3 V SPACER SPACER CROSSTALK vs FREQUENCY HEADPHONE WITH DRVDD = 3.3 V 0 0 Driver VO = 1Vrms DRVDD = 3.3V RL = 16Ω TA = 25°C −10 −20 Right to Left Left to Right −20 Right to Left Left to Right −30 Crosstalk (dB) Crosstalk (dB) −30 −40 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 Driver VO = 1Vrms DRVDD = 3.3V RL = 32Ω TA = 25°C −10 20 100 1k Frequency (Hz) 10k 20k −100 20 100 1k Frequency (Hz) G045 Figure 50. 24 10k 20k G046 Figure 51. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES DEFAULT VALUE CONTENTS A u indicates unused bits. 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x00 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section 0xA0 0x04 Serial data interface register 1 Description shown in subsequent section 0x05 0x05 System control register 2 1 Description shown in subsequent section 0x40 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section 0xFF (mute) 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB) 1 Reserved (1) 1 Description shown in subsequent section 1 Reserved (1) 0x0B–0x0D 0x0E Volume configuration register 0x0F 0x10 Modulation limit register 1 Description shown in subsequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC 0x12 IC delay channel 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC 0x14 IC delay channel 4 1 Description shown in subsequent section 0x54 1 Reserved (1) 0x15–0x18 0x19 PWM channel shutdown group register 1 Description shown in subsequent section 0x30 0x1A Start/stop period register 1 Description shown in subsequent section 0x0F 0x1B Oscillator trim register 1 Description shown in subsequent section 0x82 0x1C BKND_ERR register 1 Description shown in subsequent section 0x02 1 Reserved (1) 0x1D–0x1F 0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772 0x21 Ch 4 source select register 4 Description shown in subsequent section 0x0000 4303 4 Reserved (1) 4 Description shown in subsequent section 0x22–0x24 0x25 PWM MUX register 0x26–0x28 0x29 0x2A (1) 0x91 ch1_bq[0] ch1_bq[1] 0x0102 1345 (1) 4 Reserved 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 20 Reserved registers should not be accessed. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 25 TAS5721 SLOS739 – JULY 2012 SUBADDRESS 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 26 www.ti.com REGISTER NAME ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] NO. OF BYTES 20 20 20 20 20 20 20 20 20 CONTENTS DEFAULT VALUE u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SUBADDRESS 0x34 0x35 0x36 SLOS739 – JULY 2012 REGISTER NAME ch2_bq[4] ch2_bq[5] ch2_bq[6] 0x37–0x39 0x3A DRC1 ae (3) NO. OF BYTES 20 20 20 DRC1 aa DRC1 ad DRC2 ae DRC2 aa DRC2 ad 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], (1 – ae)[25:0] 0x0000 0000 u[31:26], aa[25:0] 0x0080 0000 u[31:26], (1 – aa)[25:0] 0x0000 0000 u[31:26], ad[25:0] 0x0080 0000 u[31:26], (1 – ad)[25:0] 0x0000 0000 u[31:26], ae[25:0] 0x0080 0000 u[31:26], (1 – ae)[25:0] 0x0000 0000 u[31:26], aa[25:0] 0x0080 0000 u[31:26], (1 – aa)[25:0] 0x0000 0000 u[31:26], ad[25:0] 0x0080 0000 8 8 8 8 8 DRC2 (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000 0x40 DRC1-T 4 T1[31:0] (9.23 format) 0xFDA2 1490 0x41 DRC1-K 4 u[31:26], K1[25:0] 0x0384 2109 0x42 DRC1-O 4 u[31:26], O1[25:0] 0x0008 4210 0x43 DRC2-T 4 T2[31:0] (9.23 format) 0xFDA2 1490 0x44 DRC2-K 4 u[31:26], K2[25:0] 0x0384 2109 0x45 DRC2-O 4 u[31:26], O2[25:0] 0x0008 4210 0x46 DRC control 4 Description shown in subsequent section 0x0000 0000 4 Reserved (2) 0x47–0x4F 0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000 0x51 Ch 1 output mixer 12 Ch 1 output mix1[2] 0x0080 0000 Ch 1 output mix1[1] 0x0000 0000 0x52 (2) (3) 0x0000 0000 u[31:26], a1[25:0] 0x0080 0000 DRC2 (1 – aa) 0x3F 0x0000 0000 u[31:26], b2[25:0] u[31:26], ae[25:0] DRC 2 (1 – ae) 0x3E u[31:26], b1[25:0] 8 DRC1 (1 – ad) 0x3D 0x0080 0000 Reserved (2) DRC1 (1 – aa) 0x3C u[31:26], b0[25:0] 4 DRC1 (1 – ae) 0x3B DEFAULT VALUE CONTENTS Ch 2 output mixer 12 Ch 1 output mix1[0] 0x0000 0000 Ch 2 output mix2[2] 0x0080 0000 Ch 2 output mix2[1] 0x0000 0000 Ch 2 output mix2[0] 0x0000 0000 Reserved registers should not be accessed. ae stands for ∝ of energy filter, aa stands for ∝ of attack filter and ad stands for ∝ of decay filter and 1- ∝ = ω. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 27 TAS5721 SLOS739 – JULY 2012 SUBADDRESS 0x53 0x54 0x55 REGISTER NAME Ch 1 input mixer Ch 2 input mixer Channel 3 input mixer NO. OF BYTES 16 16 12 CONTENTS DEFAULT VALUE Ch 1 input mixer[3] 0x0080 0000 Ch 1 input mixer[2] 0x0000 0000 Ch 1 input mixer[1] 0x0000 0000 Ch 1 input mixer[0] 0x0080 0000 Ch 2 input mixer[3] 0x0080 0000 Ch 2 input mixer[2] 0x0000 0000 Ch 2 input mixer[1] 0x0000 0000 Ch 2 input mixer[0] 0x0080 0000 Channel 3 input mixer [2] 0x0080 0000 Channel 3 input mixer [1] 0x0000 0000 Channel 3 input mixer [0] 0x0000 0000 0x56 Output post-scale 4 u[31:26], post[25:0] 0x0080 0000 0x57 Output pre-scale 4 u[31:26], pre[25:0] (9.17 format) 0x0002 0000 0x58 ch1 BQ[7] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 28 www.ti.com ch1 BQ[8] Subchannel BQ[0] Subchannel BQ[1] ch2 BQ[7] ch2 BQ[8] pseudo_ch2 BQ[0] 20 20 20 20 20 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SUBADDRESS SLOS739 – JULY 2012 REGISTER NAME NO. OF BYTES 4 Reserved (4) Channel 4 (subchannel) output mixer 8 Ch 4 output mixer[1] 0x0000 0000 Ch 4 output mixer[0] 0x0080 0000 0x61 Channel 4 (subchannel) input mixer 8 Ch 4 input mixer[1] 0x0040 0000 Ch 4 input mixer[0] 0x0040 0000 0x62 IDF post scale 4 Post-IDF attenuation register 0x0000 0080 Reserved (4) 0x0000 0000 0x5F 0x60 0x63–0xF7 0xF8 Device address enable register 4 Write F9 A5 A5 A5 in this register to enable write to device address update (0xF9) 0x0000 0000 0xF9 Device address Update Register 4 u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id (7:1) defines the new device address 0X0000 0036 4 Reserved (4) 0x0000 0000 0xFA–0xFF (4) DEFAULT VALUE CONTENTS Reserved registers should not be accessed. All DAP coefficients are 3.23 format unless specified otherwise. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 29 TAS5721 SLOS739 – JULY 2012 www.ti.com DETAILED REGISTER DESCRIPTIONS CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5721. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of 192 fS and 384 fS only. Table 1. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – Reserved (1) 0 1 0 – – – – – Reserved (1) 0 1 1 – – – – – fS = 44.1/48-kHz sample rate 1 0 0 – – – – – fs = 16-kHz sample rate 1 0 1 – – – – – fs = 22.05/24-kHz sample rate 1 1 0 – – – – – fs = 8-kHz sample rate 1 1 1 – – – – – fs = 11.025/12-kHz sample rate – – – 0 0 0 – – MCLK frequency = 64 × fS – – – 0 0 1 – – MCLK frequency = 128 × fS (3) – – – 0 1 0 – – MCLK frequency = 192 × fS (4) – – – 0 1 1 – – MCLK frequency = 256 × fS – – – 1 0 0 – – MCLK frequency = 384 × fS – – – 1 0 1 – – MCLK frequency = 512 × fS – – – 1 1 0 – – Reserved (1) – – – 1 1 1 – – Reserved (1) – – – – – – 0 – Reserved (1) (2) – – – – – – – 0 Reserved (1) (2) (1) (2) (3) (4) (5) FUNCTION (2) (3) (2) (5) Reserved registers should not be accessed. Default values are in bold. Only available for 44.1-kHz and 48-kHz rates. Rate only available for 32/44.1/48-kHz sample rates Not available at 8 kHz DEVICE ID REGISTER (0x01) The device ID register contains the ID code for the firmware revision Table 2. Device ID Register (0x01) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 30 FUNCTION Identification code Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing. • Frame Slip: LRCLK phase is drifting with respect to internal frame sync. Table 3. Error Status Register (0x02) D7 D6 D5 D4 D3 D2 D1 D0 1 - – – – – – – MCLK error – 1 – – – – – – PLL autolock error – – 1 – – – – – SCLK error – – – 1 – – – – LRCLK error – – – – 1 – – – Frame slip – – – – – 1 – – Clip indicator – – – – – – 1 – Overcurrent, overtemperature, overvoltage or undervoltage errors – – – – – – – 0 Reserved 0 0 0 0 0 0 0 – No errors (1) FUNCTION (1) Default values are in bold. SYSTEM CONTROL REGISTER 1 (0x03) The system control register 1 has several functions: Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter (–3 dB cutoff < 1 Hz) for each channel is enabled (default). Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the same time as the volume ramp defined in register 0x0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp Bits D1–D0: Select de-emphasis Table 4. System Control Register 1 (0x03) D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – PWM high-pass (dc blocking) disabled 1 – – – – – – – PWM high-pass (dc blocking) enabled (1) FUNCTION (1) (1) – 0 – – – – – – Reserved – – 0 – – – – – Soft unmute on recovery from clock error – – 1 – – – – – Hard unmute on recovery from clock error – – – 0 – – – – Reserved – – – – 0 – – – Reserved (1) (1) (1) (1) – – – – – 0 – – Reserved – – – – – – 0 0 No de-emphasis – – – – – – 0 1 De-emphasis for fS = 32 kHz – – – – – – 1 0 De-emphasis for fS = 44.1 kHz – – – – – – 1 1 De-emphasis for fS = 48 kHz (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 31 TAS5721 SLOS739 – JULY 2012 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 5, the TAS5721 supports nine serial data modes. The default is 24-bit, I2S mode, Table 5. Serial Data Interface Control Register (0x04) Format RECEIVE SERIAL DATA INTERFACE FORMAT WORD LENGTH D7–D4 D3 D2 D1 D0 Right-justified 16 0000 0 0 0 0 Right-justified 20 0000 0 0 0 1 Right-justified 24 0000 0 0 1 0 I2S 16 000 0 0 1 1 20 0000 0 1 0 0 24 0000 0 1 0 1 Left-justified 16 0000 0 1 1 0 Left-justified 20 0000 0 1 1 1 Left-justified 24 0000 1 0 0 0 Reserved 0000 1 0 0 1 Reserved 0000 1 0 1 0 Reserved 0000 1 0 1 1 Reserved 0000 1 1 0 0 Reserved 0000 1 1 0 1 Reserved 0000 1 1 1 0 Reserved 0000 1 1 1 1 2 I S I2S (1) 32 (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 6. System Control Register 2 (0x05) D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – Mid-Z ramp disabled 1 – – – – – – – Mid-Z ramp enabled – 0 – – – – – – Exit all-channel shutdown (normal operation) – 1 – – – – – – Enter all-channel shutdown (hard mute) (1) – – – – – 0 – – 2.0 mode [2.0 BTL] – – – – – 1 – – 2.1 mode [2 SE + 1 BTL] – – – – – – 0 – ADR/FAULT pin is configured as to serve as an address input only (1) – – – – – – 1 – ADR/FAULT pin is configured as fault output – – 0 0 0 – – 0 Reserved (1) FUNCTION (1) (1) (1) Default values are in bold. SOFT MUTE REGISTER (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). Table 7. Soft Mute Register (0x06) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 0 0 0 0 0 – – – Reserved – – – – – 0 – – Soft unmute channel 3 – – – – – 1 – – Soft mute channel 3 – – – – – – 0 – Soft unmute channel 2 – – – – – – 1 – Soft mute channel 2 – – – – – – – 0 Soft unmute channel 1 – – – – – – – 1 Soft mute channel 1 (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 33 TAS5721 SLOS739 – JULY 2012 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A) Step size is 0.5 dB Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Channel-3 volume – 0x0A (default is 0 dB) Table 8. Volume Registers (0x07, 0x08, 0x09, 0x0A) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 0 0 0 0 0 24 dB 0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) 1 1 1 1 1 1 1 0 –103 dB 1 1 1 1 1 1 1 1 Soft mute (default for the master volume) (1) (1) FUNCTION (1) Default values are in bold. VOLUME CONFIGURATION REGISTER (0x0E) Bits D2–D0: Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows: Sample Rate (KHz) Approximate Ramp Rate 8/16/32 125 us/step 11.025/22.05/44.1 90.7 us/step 12/24/48 83.3 us/step Table 9. Volume Control Register (0x0E) D7 D6 D5 D4 D3 D2 D1 D0 1 – – 1 0 – – – Reserved – 0 – – – – – – Subchannel (ch4) volume = ch1 volume (2) (1) – 1 – – – – – – Subchannel volume = register 0x0A (2) – – 0 – – – – – Ch3 volume = ch2 volume (1) – – 1 – – – – – Ch3 volume = register 0x0A – – – – – 0 0 0 Volume slew 512 steps (43-ms volume ramp time at 48 kHz) – – – – – 0 0 1 Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) – – – – – 0 1 0 Volume slew 2048 steps (171- ms volume ramp time at 48 kHz) – – – – – 0 1 1 Volume slew 256 steps (21-ms volume ramp time at 48 kHz) – – – – – 1 X X Reserved (1) (2) 34 FUNCTION (1) (1) Default values are in bold. Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)]. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 MODULATION LIMIT REGISTER (0x10) The modulation limit is the maximum duty cycle of the PWM output waveform. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%. Table 10. Modulation Limit Register (0x10) (1) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 98.4% – – – – – 0 1 0 – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.8% 0 0 0 0 0 – – – RESERVED 97.7% (1) Default values are in bold. INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14) Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14. Table 11. Channel Interchannel Delay Register Format SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs 0x11 1 0 1 0 1 1 – – Default value for channel 1 0x12 0 1 0 1 0 1 – – Default value for channel 2 (1) (1) 0x13 1 0 1 0 1 1 – – Default value for channel 1 (1) 0x14 0 1 0 1 0 1 – – Default value for channel 2 (1) RANGE OF VALUES FOR 0x11 - 0x14 (1) 0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles 0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles 1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles 0 0 RESERVED Default values are in bold. The ICD settings have high impact on audio performance (for example, dynamic range, THD+N, crosstalk, and so forth). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown. REGISTER AD MODE BD MODE 0x11 AC B8 0x12 54 60 0x13 AC A0 0x14 54 48 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 35 TAS5721 SLOS739 – JULY 2012 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D6 in the system control register. This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D6 is set to 0 in system control register 2, 0x05). Table 12. Shutdown Group Register D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – Reserved (1) – 0 – – – – – – Reserved (1) – – 1 – – – – – Reserved (1) – – – 1 – – – – Reserved (1) – – – – 0 – – – PWM channel 4 does not belong to shutdown group. – – – – 1 – – – PWM channel 4 belongs to shutdown group. – – – – – 0 – – PWM channel 3 does not belong to shutdown group. – – – – – 1 – – PWM channel 3 belongs to shutdown group. – – – – – – 0 – PWM channel 2 does not belong to shutdown group. – – – – – – 1 – PWM channel 2 belongs to shutdown group. – – – – – – – 0 PWM channel 1 does not belong to shutdown group. – – – – – – – 1 PWM channel 1 belongs to shutdown group. (1) 36 FUNCTION (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability. Table 13. Start/Stop Period Register (0x1A) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 0 – – – – – – – SSTIMER enabled 1 – – – – – – – SSTIMER disabled – 0 0 – – – – – Reserved – – – 0 0 – – – No 50% duty cycle start/stop period – – – 0 1 0 0 0 16.5-ms 50% duty cycle start/stop period – – – 0 1 0 0 1 23.9-ms 50% duty cycle start/stop period – – – 0 1 0 1 0 31.4-ms 50% duty cycle start/stop period – – – 0 1 0 1 1 40.4-ms 50% duty cycle start/stop period – – – 0 1 1 0 0 53.9-ms 50% duty cycle start/stop period – – – 0 1 1 0 1 70.3-ms 50% duty cycle start/stop period – – – 0 1 1 1 0 94.2-ms 50% duty cycle start/stop period – – – 0 1 1 1 1 125.7-ms 50% duty cycle start/stop period (1) – – – 1 0 0 0 0 164.6-ms 50% duty cycle start/stop period – – – 1 0 0 0 1 239.4-ms 50% duty cycle start/stop period – – – 1 0 0 1 0 314.2-ms 50% duty cycle start/stop period – – – 1 0 0 1 1 403.9-ms 50% duty cycle start/stop period – – – 1 0 1 0 0 538.6-ms 50% duty cycle start/stop period – – – 1 0 1 0 1 703.1-ms 50% duty cycle start/stop period – – – 1 0 1 1 0 942.5-ms 50% duty cycle start/stop period – – – 1 0 1 1 1 1256.6-ms 50% duty cycle start/stop period – – – 1 1 0 0 0 1728.1-ms 50% duty cycle start/stop period – – – 1 1 0 0 1 2513.6-ms 50% duty cycle start/stop period – – – 1 1 0 1 0 3299.1-ms 50% duty cycle start/stop period – – – 1 1 0 1 1 4241.7-ms 50% duty cycle start/stop period – – – 1 1 1 0 0 5655.6-ms 50% duty cycle start/stop period – – – 1 1 1 0 1 7383.7-ms 50% duty cycle start/stop period – – – 1 1 1 1 0 9897.3-ms 50% duty cycle start/stop period – – – 1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 37 TAS5721 SLOS739 – JULY 2012 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5721 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. TI recommends a reference resistor value of that shown in the Typical Application Circuit Diagrams. The circuit that uses this resistor should be calibrated or trimmed after each time the device is reset. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory. It is important to note that after writing the value 0x00 to the trim register, the register will repor the value 0xC0, to indicate the trim process is complete. Table 14. Oscillator Trim Register (0x1B) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 1 – – – – – – – Reserved – 0 – – – – – – Oscillator trim not done (read-only) – 1 – – – – – – Oscillator trim done (read only) – – 0 0 0 0 – – Reserved – – – – – – 0 – Select factory trim (Write a 0 to select factory trim; default is 1.) – – – – – – 1 – Factory trim disabled – – – – – – – 0 Reserved (1) (1) (1) (1) (1) Default values are in bold. BKND_ERR REGISTER (0x1C) When a backend error signal is received from the internal power stage, the power stage is reset stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 15 before attempting to restart the power stage. Table 15. BKND_ERR Register (0x1C) (1) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 X Reserved – – – – 0 0 1 0 Set back-end reset period to 299 ms – – – – 0 0 1 1 Set back-end reset period to 449 ms – – – – 0 1 0 0 Set back-end reset period to 598 ms – – – – 0 1 0 1 Set back-end reset period to 748 ms – – – – 0 1 1 0 Set back-end reset period to 898 ms – – – – 0 1 1 1 Set back-end reset period to 1047 ms – – – – 1 0 0 0 Set back-end reset period to 1197 ms – – – – 1 0 0 1 Set back-end reset period to 1346 ms – – – – 1 0 1 X – – – – 1 1 X X (1) (2) 38 FUNCTION (2) Set back-end reset period to 1496 ms This register can be written only with a non-reserved value. Also this register can be only be written once after the device is reset. If a different value is desired, the device must be reset before changing 0x1C again. Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 16. Input Multiplexer Register (0x20) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 - - - 0 (1) Polarity of Ch3 is not inverted 1 Polarity of Ch3 is inverted 0 Polarity of Ch2 is not inverted 1 Polarity of Ch2 is inverted 0 Polarity of Ch1 is not inverted 1 Polarity of Ch1 is inverted D23 D22 D21 D20 D19 D18 D17 D16 0 – – – – – – – Channel-1 AD mode 1 – – – – – – – Channel-1 BD mode – 0 0 0 – – – – SDIN-L to channel 1 – 0 0 1 – – – – SDIN-R to channel 1 – 0 1 0 – – – – Reserved – 0 1 1 – – – – Reserved – 1 0 0 – – – – Reserved – 1 0 1 – – – – Reserved – 1 1 0 – – – – Ground (0) to channel 1 – 1 1 1 – – – – Reserved – – – – 0 – – – Channel 2 AD mode – – – – 1 – – – Channel 2 BD mode – – – – – 0 0 0 SDIN-L to channel 2 – – – – – 0 0 1 SDIN-R to channel 2 – – – – – 0 1 0 Reserved – – – – – 0 1 1 Reserved – – – – – 1 0 0 Reserved – – – – – 1 0 1 Reserved – – – – – 1 1 0 Ground (0) to channel 2 – – – – – 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 0 1 1 1 0 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 - FUNCTION (1) (1) (1) (1) FUNCTION Reserved (1) FUNCTION Sub channel in 2.1 mode, AD modulation 1 0 (1) FUNCTION Reserved Sub channel in 2.1 mode, BD modulation 0 1 0 Reserved (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 39 TAS5721 SLOS739 – JULY 2012 www.ti.com CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 17. Subchannel Control Register (0x21) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION Reserved (1) FUNCTION Reserved (1) Reserved (1) FUNCTION 0 1 0 0 0 0 1 – – – – – – – 0 (L + R)/2 – – – – – – – 1 Left-channel post-BQ D7 D6 D5 D4 D3 D2 D1 D0 0 (1) 0 0 0 0 0 1 1 (1) FUNCTION Reserved (1) Default values are in bold. PWM OUTPUT MUX REGISTER (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin. Bits D21–D20: Selects which PWM channel is output to OUT_A Bits D17–D16: Selects which PWM channel is output to OUT_B Bits D13–D12: Selects which PWM channel is output to OUT_C Bits D09–D08: Selects which PWM channel is output to OUT_D Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03. See for details. Table 18. PWM Output Mux Register (0x25) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 1 D23 D22 D21 D20 D19 D18 D17 D16 0 0 – – – – – – Reserved (1) – – 0 0 – – – – Multiplex PWM 1 to OUT_A – – 0 1 – – – – Multiplex PWM 2 to OUT_A – – 1 0 – – – – Multiplex PWM 3 to OUT_A – – 1 1 – – – – Multiplex PWM 4 to OUT_A – – – – 0 0 – – Reserved – – – – – – 0 0 Multiplex PWM 1 to OUT_B – – – – – – 0 1 Multiplex PWM 2 to OUT_B – – – – – – 1 0 Multiplex PWM 3 to OUT_B – – – – – – 1 1 Multiplex PWM 4 to OUT_B D15 D14 D13 D12 D11 D10 D9 D8 (1) 40 Reserved (1) FUNCTION (1) (1) (1) FUNCTION (1) 0 0 – – – – – – Reserved – – 0 0 – – – – Multiplex PWM 1 to OUT_C – – 0 1 – – – – Multiplex PWM 2 to OUT_C (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Table 18. PWM Output Mux Register (0x25) (continued) – – 1 0 – – – – Multiplex PWM 3 to OUT_C – – 1 1 – – – – Multiplex PWM 4 to OUT_C – – – – 0 0 – – Reserved – – – – – – 0 0 Multiplex PWM 1 to OUT_D – – – – – – 0 1 Multiplex PWM 2 to OUT_D – – – – – – 1 0 Multiplex PWM 3 to OUT_D – – – – – – 1 1 Multiplex PWM 4 to OUT_D D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 (1) (1) FUNCTION Reserved (1) DRC CONTROL (0x46) Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default. Table 19. DRC Control Register D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 (1) FUNCTION Reserved (1) Reserved (1) Reserved (1) (1) FUNCTION FUNCTION 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 – – – – – – Reserved – – 0 – – – – – Disable complementary (1–H) low-pass filter generation – – 1 – – – – – Enable complementary (1–H) low-pass filter generation – – – 0 – – – – – – – 1 – – – – 0 0 FUNCTION Reserved (1) (1) – – – – – – 0 – DRC2 turned OFF – – – – – – 1 – DRC2 turned ON – – – – – – – 0 DRC1 turned OFF – – – – – – – 1 DRC1 turned ON (1) (1) Default values are in bold. BANK SWITCH AND EQ CONTROL (0x50) The bank switching feature is described in detail in section BANK SWITCHING. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 41 TAS5721 SLOS739 – JULY 2012 www.ti.com Table 20. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved (1) – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 3 – – – 1 – – – – 44.1/48 kHz, uses bank 3 – – – – 0 – – – 16 kHz, does not use bank 3 – – – – 1 – – – 16 kHz, uses bank 3 – – – – – 0 – – 22.025/24 kHz, does not use bank 3 – – – – – 1 – – 22.025/24 kHz, uses bank 3 – – – – – – 0 – 8 kHz, does not use bank 3 – – – – – – 1 – 8 kHz, uses bank 3 – – – – – – – 0 11.025 kHz/12, does not use bank 3 – – – – – – – 1 11.025/12 kHz, uses bank 3 D23 D22 D21 D20 D19 D18 D17 D16 0 – – – – – – – 32 kHz, does not use bank 2 1 – – – – – – – 32 kHz, uses bank 2 – 1 – – – – – – Reserved (1) – – 1 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 2 – – – 1 – – – – 44.1/48 kHz, uses bank 2 – – – – 0 – – – 16 kHz, does not use bank 2 – – – – 1 – – – 16 kHz, uses bank 2 – – – – – 0 – – 22.025/24 kHz, does not use bank 2 – – – – – 1 – – 22.025/24 kHz, uses bank 2 – – – – – – 0 – 8 kHz, does not use bank 2 – – – – – – 1 – 8 kHz, uses bank 2 – – – – – – – 0 11.025/12 kHz, does not use bank 2 – – – – – – – 1 11.025/12 kHz, uses bank 2 D15 D14 D13 D12 D11 D10 D9 D8 0 – – – – – – – 32 kHz, does not use bank 1 1 – – – – – – – 32 kHz, uses bank 1 (1) 42 FUNCTION (1) (1) (1) (1) (1) (1) FUNCTION (1) (1) (1) (1) (1) (1) FUNCTION (1) (1) – 0 – – – – – – Reserved – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 1 – – – 1 – – – – 44.1/48 kHz, uses bank 1 – – – – 0 – – – 16 kHz, does not use bank 1 – – – – 1 – – – 16 kHz, uses bank 1 – – – – – 0 – – 22.025/24 kHz, does not use bank 1 – – – – – 1 – – 22.025/24 kHz, uses bank 1 – – – – – – 0 – 8 kHz, does not use bank 1 – – – – – – 1 – 8 kHz, uses bank 1 – – – – – – – 0 11.025/12 kHz, does not use bank 1 – – – – – – – 1 11.025/12 kHz, uses bank 1 (1) (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Table 20. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 1 – – – – – – – EQ OFF (bypass BQ 0-7 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. – – – 0 – – – – L and R can be written independently. – – – 1 – – – – L and R are ganged for EQ biquads; a write to left-channel BQ is also written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also 0x58–0x5B is ganged to 0x5C–0x5F) – – – – 0 – – – Reserved – – – – – 0 0 0 No bank switching. All configuration of the BiQuads are applied directly to the DAP (2) – – – – – 0 0 1 Configure bank 1 (32 kHz by default) – – – – – 0 1 0 Configure bank 2 (44.1/48 kHz by default) – – – – – 0 1 1 Configure bank 3 (other sample rates by default) – – – – – 1 0 0 Automatic bank selection – – – – – 1 0 1 Reserved – – – – – 1 1 X Reserved 0 EQ ON 1 (2) FUNCTION (2) (2) Use bank-mapping in bits D31–D8. (2) (2) Default values are in bold. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 43 TAS5721 SLOS739 – JULY 2012 www.ti.com DETAILED DESCRIPTION AND THEORY OF OPERATION POWER SUPPLY To facilitate system design, the TAS5721 needs only a 3.3-V supply in addition to the PVDD power-stage supply. The required sequencing of the power supplies is shown in the Recommended Use Model section. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. As shown in the Typical Application Circuits section, it is recommended to use ceramic capacitors, for the bootstrap supply pins. These capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD pin is decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in the Typical Application Circuits section. The TAS5721 is fully protected against erroneous power-stage turn-on due to parasitic gate charging. I2C Address Selection and Fault Output ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the Typical Application Circuits section in order to set the I2C address. Pulling this pin HIGH through the resistor results in setting the I2C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the address to 0011010 (0x34). During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to it's default state when register 0x02 is cleared. The device will pull the fault pin low for over-current, overtemperature, over-voltage lock-out, and under-voltage lock-out. DEVICE PROTECTION SYSTEM Overcurrent (OC) Protection With Current Limiting The device has independent, fast reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by a protection system. If the high-current condition situation persists, a protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (HiZ) state. After the power stage enters into this state, the power stage will attempt to restart after a period of time defined in register 0x1C. If the high-current condition persists, the device will begin the shutdown and retry sequence again. The device will return to normal operation once the fault condition is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between halfbridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down. 44 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Overtemperature Protection The TAS5721 has an overtemperature-protection system. If the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the highimpedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. The TAS5721 recovers automatically once the temperature drops approximately 30 °C. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5721 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 4.1 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and ADR/FAULT, if configured as an output, being asserted low. CLOCK, AUTO DETECTION, AND PLL The TAS5721 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control Register section. The TAS5721 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 times the PWM switching frequency. The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register. TAS5721 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to operate in a reduced capacity using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute) by default. If desired, the unmuting process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E). SERIAL DATA INTERFACE Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5721 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats. PWM Section The TAS5721 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs up to three PWM audio output channels. The PWM modulation block has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled. Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. It is important to note that for any applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%. SERIAL INTERFACE CONTROL AND TIMING The I2S mode is set by writing to register 0x04. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 45 TAS5721 SLOS739 – JULY 2012 www.ti.com I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions. 2 2-Channel I S (Philips Format) Stereo Input 32 Clks LRCLK (Note Reversed Phase) 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 52. I2S 64-fS Format 46 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 2 2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) LRCLK 24 Clks 24 Clks Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 3 2 1 0 LSB 23 22 17 16 9 8 5 4 19 18 13 12 5 4 1 0 15 14 9 1 0 3 2 1 20-Bit Mode 19 18 16-Bit Mode 15 14 8 8 T0092-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 53. I2S 48-fS Format 2 2-Channel I S (Philips Format) Stereo Input LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode 15 14 13 12 MSB LSB 11 10 9 8 5 4 3 2 1 0 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 T0266-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 54. I2S 32-fS Format Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 47 TAS5721 SLOS739 – JULY 2012 www.ti.com 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 55. Left-Justified 64-fS Format 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 56. Left-Justified 48-fS Format 48 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 2-Channel Left-Justified Stereo Input 16 Clks 16 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 16-Bit Mode 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 MSB 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 T0266-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 57. Left-Justified 32-fS Format Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 MSB LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 20-Bit Mode 16-Bit Mode T0034-03 Figure 58. Right Justified 64-fS Format Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 49 TAS5721 SLOS739 – JULY 2012 www.ti.com 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 59. Right Justified 48-fS Format Figure 60. Right Justified 32-fS Format 50 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 I2C SERIAL CONTROL INTERFACE The TAS5721 DAP has a bidirectional inter-integrated circuit (I2C) interface that is compatible with the I2C bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation (400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles. General I2C Operation The I2C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock) SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 61. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus. SDA R/ A W 7-Bit Slave Address 7 6 5 4 3 2 1 0 8-Bit Register Address (N) 7 6 5 4 3 2 1 0 8-Bit Register Data For Address (N) A 7 6 5 4 3 2 1 8-Bit Register Data For Address (N) A 0 7 6 5 4 3 2 1 A 0 SCL Start Stop T0035-01 Figure 61. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 61. Pin ADR/FAULT defines the I2C device address. An external 15-kΩ pull down on this pin gives a device address of 0x34 and a 15-kΩ pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010 (0x34). I2C Device Address Change Procedure • Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5. • Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address. • Any writes after that should use the new device address XX. Single- and Multiple-Byte Transfers The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses 0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 51 TAS5721 SLOS739 – JULY 2012 www.ti.com During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0. During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5721 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5721. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded. Single-Byte Write As shown in Figure 62, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5721 internal memory address being accessed. After receiving the address byte, the TAS5721 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5721 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the singlebyte data write transfer. Start Condition Acknowledge A6 A5 A4 A3 A2 A1 A0 Acknowledge R/W ACK A7 A6 A5 2 A4 A3 A2 A1 Acknowledge A0 ACK D7 D6 Subaddress I C Device Address and Read/Write Bit D5 D4 D3 D2 D1 D0 ACK Stop Condition Data Byte T0036-01 Figure 62. Single-Byte Write Transfer Multiple-Byte Write A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 63. After receiving each data byte, the TAS5721 responds with an acknowledge bit. Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 2 I C Device Address and Read/Write Bit A6 A5 A4 A3 Subaddress A1 Acknowledge Acknowledge Acknowledge Acknowledge A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-02 Figure 63. Multiple-Byte Write Transfer 52 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Single-Byte Read As shown in Figure 64, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5721 address and the read/write bit, TAS5721 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5721 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5721 again responds with an acknowledge bit. Next, the TAS5721 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Repeat Start Condition Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 Acknowledge A6 2 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 2 I C Device Address and Read/Write Bit Subaddress I C Device Address and Read/Write Bit Not Acknowledge Acknowledge D1 D0 ACK Stop Condition Data Byte T0036-03 Figure 64. Single-Byte Read Transfer Multiple-Byte Read A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5721 to the master device as shown in Figure 65. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge A6 2 A0 R/W ACK A7 I C Device Address and Read/Write Bit Acknowledge A6 A6 A0 ACK A5 Subaddress 2 Acknowledge Acknowledge Acknowledge Not Acknowledge A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-04 Figure 65. Multiple Byte Read Transfer Output Mode and MUX Selection The TAS5721 is a highly configurable device, capable of operating in 2.0, Single Device 2.1 and parallel bridge tied load (PBTL) configurations. Addtionally, the modulation scheme can be changed for the channels to operate either in AD or BD Modulation mode. While many configurations are possible because of this flexibility, the majority of use cases uses will operate in one of the configurations shown below. For ease of use and reduced complexity, the figure below outlines both the register settings and the output configurations required to set the device up for operation in these various modes. The output configuration quick reference table below highlights the controls that are required to configure the device for various operational modes. Please note that other controls, which are not directly related to the output configuration muxes may also be required. For example, the Inter Channel Delay (ICD) settings will likely need to be modified to optimize for idle channel noise, cross-talk, and distortion performance for each of these considerations, in addition to start and stop time and others. Please consult the respective registers for these controls to optimize for various other peformance parameters and use cases. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 53 TAS5721 SLOS739 – JULY 2012 www.ti.com Table 21. Output Configuration Quick Reference Output Configuration Modulation Mode Register Settings AD for Both Outputs 0x20[23] = 0 0x20[19] = 0 0x20[15:8] = 0x77 0x05[7] = 0 0x05[2] = 0 0x25[23:8] = 0x0213 0x1A[7:0] = 0x0F Block Diagram PWM1 A (L+) PWM2 B (L–) PWM3 C (R+) PWM4 D (R–) CH1_audio CH2_audio B0487-01 2.0 (Stereo BTL) BD for Both Outputs 0x20[23] = 1 0x20[19] = 1 0x20[15:8] = 0x77 0x05[7] = 0 0x05[2] = 0 0x25[23:8] = 0x0213 0x1A[7:0] = 0x0A PWM1 A (L+) PWM2 B (L–) PWM3 C (R+) PWM4 D (R–) CH1_audio CH2_audio B0487-02 Single Device 2.1 (Stereo Single Ended + Mono BTL) Note: In these described configurations, the polarity of the signal being sent to SPK_OUTB is inverted. For this reason, care should be taken to ensure that the speakers are connected as shown in the block diagram. AD for Both SE Outputs AD for Single BTL Output AD for both SE Outputs BD for Single BTL Output AD 1.0 Mono PBTL BD 0x20[23] = 0 0x20[19] = 0 0x20[3] = 0 0x05[7] = 1 0x05[2] = 1 0x25[23:8] = 0x0132 0x1A[7:0] = 0x95 0x20[7:4] = 0x7 0x21[8] = 0 0x20[25] = 1 0x20[23] = 0 0x20[19] = 0 0x20[3] = 1 0x05[7] = 1 0x05[2] = 1 0x25[23:8] = 0x0132 0x1A[7:0] = 0x95 0x20[7:4] = 0x7 0x21[8] = 0 0x20[25] = 1 0x05[7] = 0 0x05[5] = 0 0x05[2] = 0 0x19[7:0] = 0x3A 0x1A[7:0] = 0x0F 0x20[23] = 0 0x20[15:12] = 0x7 0x25[23:8] = 0x0123 0x05[7] = 0 0x05[5] = 0 0x05[2] = 0 0x19[7:0] = 0x3A 0x1A[7:0] = 0x0A 0x20[23] = 1 0x20[15:12] = 0x7 0x25[23:8] = 0x0123 PWM1 A (L+) PWM2 B (R–) PWM3 C (S+) PWM4 D (S–) CH1_audio CH2_audio CH3_audio B0487-03 PWM1 A (L+) PWM2 B (R–) PWM3 C (S+) PWM4 D (S–) CH1_audio CH2_audio CH3_audio B0487-04 CH1_audio PWM1 A (L+) OFF2 B (Off) PWM3 C (L–) OFF4 D (Off) + – B0488-02 CH1_audio PWM1 A (L+) CH2_audio PWM2 B (Off) OFF3 C (R–) OFF4 D (Off) + – + – B0488-01 2.1-Mode Support The TAS5721 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must be set to 1. The SSTIMER pin should be left floating in this mode. 54 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Supply Pumping and Polarity Inversion The high degree of correlation between the left and right channels of a stereo audio signal dictates that, when the left audio signal is positive, the right audio signal tends to be positive as well. When the Class D is configured for single-ended operation (as would be the case for Single Device 2.1 Operation), this results in both outputs drawing current from the supply rail "in phase". Similarly, when the left audio signal is negative, the right audio signal tends to be negative as well. For single-ended operation, both outputs will likewise force current into the ground rail. This can lead to a phenomenon called "supply pumping" in which the capacitances on the PVDD rail begin to store charge- raising the voltage level of PVDD as well. This noise injection onto the rail is in phase with and at a similar frequency of the signal being produced by the amplifier output stage. This phenomenon can cause issues for other devices attached to the PVDD rail. The problem does not occur for BTL outputs since outputs of both polarities are always present for each channel. To combat supply pumping in 2.1 Mode, the device has an integrated speaker-mode volume negation feature, which, essentially introduces a polarity inversion (shift by 180°) to any of the given channels. By setting the correct bit in 0x20[31:24], it is possible to invert the polarity of the DAP channels that drive the PWM modulator blocks. This allows, for instance, the left channel to operate with its default polarity, while the right channel could have its polarity inverted to balance current flow into and out of the supplies. This procedure could have an adverse implication on the stereo imaging of the audio system because, if the speakers in the system are connected in the same manner as they would be connected when being driven by traditional BTL channels, the phase of the signals being sent to the speakers is 180° out of phase. In order to prevent this from occurring, the speaker on the negated channel must be connected "backwards" (i.e. the Class D signal for the negated channel gets connected to the negative speaker terminal and the positive terminal is grounded). In this way, supply pumping is reduced while keeping the effective signal polarity the same. The table above includes register settings which enable the polarity inversion, so care should be taken to adjust the polarity of the speakers if this feature is left enabled. Of course this feature can be left disabled if desired, provided the supply pumping phenomenon doesn't cause any other system level issues PBTL-Mode Support The TAS5721 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected after the LC filter. In order to put the part in PBTL configuration, the PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value of 0x3A. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 55 TAS5721 SLOS739 – JULY 2012 www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subchannel. The DRC input/output diagram is shown in Figure 66. Refer to GDE software tool for more description on T, K, and O parameters. Output Level (dB) K 1:1 Transfer Function O Implemented Transfer Function T Input Level (dB) M0091-02 Professional-quality dynamic range compression automatically adjusts volume to flatten volume level. • Each DRC has adjustable threshold, offset, and compression levels. • Programmable energy, attack, and decay time constants • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging, and decay times can be set slow enough to avoid pumping. Figure 66. Dynamic Range Control Energy Filter Compression Control Attack and Decay Filters a, w T, K, O aa, wa / ad, wd DRC1 0x3A 0x40, 0x41, 0x42 0x3B / 0x3C DRC2 0x3D 0x43, 0x44, 0x45 0x3E / 0x3F Audio Input DRC Coefficient Alpha Filter Structure S a w –1 Z NOTE: w=1–α B0265-01 T = 9.23 format, all other DRC coefficients are 3.23 format Figure 67. DRC Structure 56 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 BANK SWITCHING The TAS5721 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is used in 44.1- or 48-kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5721 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention. An external controller configures bankable locations (0x29-0x36, 0x3A-0x3F, and 0x58-0x5F) for all three banks during the initialization sequence. If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5721 automatically swaps the coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate change. By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5721 automatically swaps banks based on the sample rate. Command sequences for updating DAP coefficients can be summarized as follows: 1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not influenced by subsequent sample rate changes. OR Bank switching enabled: (a) Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients. (b) Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients. (c) Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients. (d) Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50. 26-Bit 3.23 Number Format All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 68 . 2 –23 2 2 –5 –1 Bit Bit Bit 0 2 Bit 1 2 Bit Sign Bit S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx M0125-01 Figure 68. 3.23 Format Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 57 TAS5721 SLOS739 – JULY 2012 www.ti.com The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 68. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 69 applied to obtain the magnitude of the negative number. 1 0 2 Bit 2 Bit 1 2 –1 Bit 2 0 (1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2 –1 –4 Bit 2 + ....... (1 or 0) ´ 2 –4 –23 Bit + ....... (1 or 0) ´ 2 –23 M0126-01 Figure 69. Conversion Weighting Factors—3.23 Format to Floating Point Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 70 Fraction Digit 6 Sign Bit Fraction Digit 1 Integer Digit 1 Fraction Digit 2 Fraction Digit 3 Fraction Digit 4 Fraction Digit 5 u u u u u u S x x. x x x x x x x x x x x x x x x x x x x x x x x 0 Coefficient Digit 8 Coefficient Digit 7 Coefficient Digit 6 Coefficient Digit 5 Coefficient Digit 4 Coefficient Digit 3 Coefficient Digit 2 Coefficient Digit 1 u = unused or don’t care bits Digit = hexadecimal digit M0127-01 2 Figure 70. Alignment of 3.23 Coefficient in 32-Bit I C Word Table 22. Sample Calculation for 3.23 Format dB Linear Decimal 0 1 8,388,608 Hex (3.23 Format) 0080 0000 5 1.7782794 14,917,288 00E3 9EA8 –5 0.5623413 4,717,260 0047 FACC X L = 10(X/20) D = 8,388,608 × L H = dec2hex (D, 8) Table 23. Sample Calculation for 9.17 Format 58 dB Linear Decimal Hex (9.17 Format) 0 1 131,072 2 0000 3 8A3D 5 1.77 231,997 –5 0.56 73,400 1 1EB8 X L = 10(X/20) D = 131,072 × L H = dec2hex (D, 8) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Recommended Use Model Normal Operation Initialization AVDD/DVDD Powerdown Shutdown 3V 3V 0 ns PDN 2 ms 0 ns 2 I C SCL SDA Trim DAP Config Other Config Exit SD Volume and Mute Commands (2)(3) 50 ms 1 ms + 1.3 tstart Enter SD (2) 1 ms + 1.3 tstop 2 ms 0 ns 100 ms RST 13.5 ms tPLL (1) 2 ms 100 μs 10 ms PVDD 8V 6V 8V 6V (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets. (2) tstart/tstop = PWM start/stop time as defined in register 0X1A (3) When Mid-Z ramp is enabled (for 2.1 mode), tstart = 300 ms T0419-07 Figure 71. Recommended Command Sequence Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 59 TAS5721 SLOS739 – JULY 2012 www.ti.com 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RST 2 ms 0 ns 8V PVDD 6V T0420-06 Figure 72. Power Loss Sequence Recommended Command Sequences Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RST = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RST = 1, and wait at least another 13.5 ms. • Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs. 3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms. 4. Configure the DAP via I2C (see Users's Guide for typical values). 5. Configure remaining registers. 6. Exit shutdown (sequence defined below). Normal Operation The following are the only events supported during normal operation: 1. Writes to master/channel volume registers. 2. Writes to soft mute register. 3. Enter and exit shutdown (sequence defined below). Note: Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD powerup ramp (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A). 60 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Shutdown Sequence Enter: 1. Write 0x40 to register 0x05. 2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). 3. If desired, reconfigure by returning to step 4 of initialization sequence. 1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD powerup ramp). 2. Wait at least 1 ms + 1.3 × tstart (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A). 3. Proceed with normal operation. Exit: Power-Down Sequence Use the following sequence to powerdown the device and its supplies: 1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms. 2. Assert RST = 0. 3. Drive digital inputs low and ramp down PVDD supply as follows: 4. • Drive all digital inputs low after RST has been low for at least 2 µs. • Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs. USING HEADPHONE AMPLIFIER OR LINE DRIVER IN TAS5721 This device has a stereo output which can be used as a line driver or a headphone driver that can output 2-Vrms stereo. An audio system can be set up for different applications using this device. USING HEADPHONE AMPLIFIER IN TAS5721 The device can be represented as shown in Figure 73: analog inputs (single-ended) as DR_INA (pin 7) and DR_INB (pin 10) with the outputs DR_OUTA (pin 8) and DR_OUTB (pin 9). R2 R1 VIN DR_INx DR_OUTx VOUT S0490-02 Figure 73. Headphone/Line Driver with Analog Input DR_SD pin can be used to turn ON or OFF the headphone amplifier and line driver. Speaker channels are independent of headphone and line driver in this mode. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 61 TAS5721 SLOS739 – JULY 2012 www.ti.com USING LINE DRIVER AMPLIFIER IN TAS5721 Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 74 illustrates the conventional line driver amplifier connection to the load and output signal. DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal. Conventional Solution 9–12 V VDD + Mute Circuit Co + + OPAMP Output VDD/2 – GND MUTE TAS5721 Solution 3.3 V DirectPath VDD + Mute Circuit Output GND TAS5721 – VSS DR_SD Figure 74. Conventional and DirectPath HP and Line Driver The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail, combining this with the built in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 74 illustrate the ground-referenced headphone and line driver architecture. This is the architecture of the TAS5721. COMPONENT SELECTION Charge Pump The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The capacitor connected to the DR_VSS pin must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µF is typical. Capacitor values that are smaller than 1 µF are not recommended for the DR_VSS pin as they will limit the negative voltage swing when driving low impedance loads. 62 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 TAS5721 www.ti.com SLOS739 – JULY 2012 Decoupling Capacitors The TAS5721 is a DirectPath amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device PVDD leads works best. Placing this decoupling capacitor close to the TAS5721 is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Please refer to the TAS5721 for the recommended layout for these components. Gain Setting Resistors Ranges The gain setting resistors, Rin and Rfb, must be chosen so that noise, stability and input capacitor size of the TAS5721 is kept within acceptable limits. Voltage gain is defined as Rfb divided by Rin. Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise of the amplifier. Table 24 lists the recommended resistor values for different gain settings. Table 24. Recommended Resistor Values INPUT RESISTOR VALUE, Rin FEEDBACK RESISTOR VALUE, Rfb DIFFERENTIAL INPUT GAIN 10 kΩ 10 kΩ 1 V/V –1 V/V 2 V/V 10 kΩ 15 kΩ 1.5 V/V –1.5 V/V 2.5 V/V 10 kΩ 20 kΩ 2 V/V –2 V/V 3 V/V 4.7 kΩ 47 kΩ 10 V/V –10 V/V 11 V/V Cin INVERTING INPUT GAIN NON INVERTING INPUT GAIN Rin –In Rfb – + S0446-01 Figure 75. Inverting Gain Configuration Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the TAS5721. These capacitors block the DC portion of the audio source and allow the TAS5721 inputs to be properly biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1, limiting the DC-offset voltage at the output. These capacitors form a high-pass filter with the input resistor, Rin. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input resistor chosen from Table 24, then the frequency and/or capacitance can be determined when one of the two values is given. 1 1 fc in = Cin = 2p ´ Rin ´ Cin 2p ´ fc in ´ Rin (1) Using the TAS5721 as a Second Order Filter Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible with the TAS5721 as it can be used like a standard OPAMP. Several filter topologies can be implemented, both single ended and differential. In the figure below a Multi Feed Back (MFB), with differential input and single ended input is shown. An AC-coupling capacitor to remove DC-content from the source is shown. It serves to block any DC content from the source and lowers the DC-gain to 1, helping reduce the output dc-offset to a minimum. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 63 TAS5721 SLOS739 – JULY 2012 www.ti.com The component values can be calculated with the help of the TI FilterPro™ program available on the TI website at: focus.ti.com Inverting Input R2 C3 R1 C1 R3 –In – C2 TAS5721 + Figure 76. Second-Order Active Low-Pass Filter The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small size ac-coupling cap. The C2 can be split in two with the midpoint connected to GND; this can increase the common-mode attenuation. Pop-Free Power Up Pop-free power up is ensured by keeping the DR_SD low during power supply ramp up and down. The pin should be kept low until the input AC-coupling capacitors are fully charged before asserting the DR_SD pin high, this way proper precharge of the AC-coupling capacitors is performed and pop-less power up is achieved. Figure 77 illustrates the preferred sequence. Supply Supply Ramp DR_SD Time for AC-Coupling Capacitors to Charge T0463-02 Figure 77. Power Up or Down Sequence 64 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TAS5721 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TAS5721DCA ACTIVE HTSSOP DCA 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5721DCAR ACTIVE HTSSOP DCA 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5721DCAR Package Package Pins Type Drawing SPQ HTSSOP 2000 DCA 48 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5721DCAR HTSSOP DCA 48 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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