www.cadeka.com SPT7851 10-Bit, 20 MSPS, 79mW Analog-to-DIgital Converter Features Description • 10-Bit, 20 MSPS Analog-to-Digital converter • Monolithic CMOS • Internal track-and-hold • Low input capacitance: 1.4 pF • Low power dissipation: 79mW • 2.8 to 3.6V power supply range • TTL-compatible outputs • -40°C to +85°C operation The SPT7851 10-bit, 20 MSPS analog-to-digital converter has a pipelined converter architecture built in a CMOS process. It delivers high performance with a typical power dissipation of only 79mW. With low distortion and high dynamic range, this device offers the performance needed for imaging, multimedia, telecommunications and instrumentation applications. The SPT7851 is available in a 44-lead Thin Quad Flat Pack (TQFP) package in the industrial temperature range (-40°C to +85°C). Applications • CCD imaging cameras and sensors • Medical imaging • RF communications • Document and film scanners • Electro-optics • Transient signal analysis • Handheld equipment Functional Block Diagram ADC + – G=2 DAC D<1…0> Pipeline Stage VIN+ VIN– Stage 1 VREF+ Stage 2 Stage 9 Stage 10 VREF– CLK Clock Driver Digital Delays, Error Correction and Output 10 Digital Output (D0 – D9) REV. 1B October 2003 DATA SHEET SPT7851 Electrical Specifications (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65V, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) Parameter Conditions Test Level Min Typ Max Units DC Accuracy Resolution 10 Bits Differential Linearity V ±0.6 LSB Integral Linearity V ±0.75 LSB No Missing Codes VI Guaranteed Analog Input Input Voltage Range (differential) IV ±0.6 ±1.0 ±1.7 V Common Mode Input Voltage IV 1.2 1.65 1.9 V Input Capacitance V 1.4 pF Input Bandwidth (large signal) V 120 MHz V ±1.0 %FSR V 0.3 %FSR Offset (mid-scale) VIN+ = VIN- = VCM Gain Error Reference Voltages Reference Input Voltage Range IV 0.6 1.0 1.7 V Negative Reference Voltage (VREF–) IV 0.9 1.0 1.3 V Positive Reference Voltage (VREF+) IV 1.9 2.0 2.9 V VI 1.3 1.65 1.8 V Common Mode Output Voltage (VCM) VREF+ – VREF– IO = -1µA VREF+ Current V 35 µA VREF– Current V -25 µA Switching Performance Maximum Conversion Rate VI 20 MHz Pipeline Delay (see Figure 1) IV 7.5 CLK Aperture Delay Time (TAP) V 5 ns Aperture Jitter Time V 10 ps-rms 58 dB 58 dB 9.3 Bits Bits Dynamic Performance Signal-To-Noise Ratio ƒIN = 5MHz VI ƒIN = 10MHz V ƒIN = 5MHz VI ƒIN = 10MHz V 9.0 ƒIN = 5MHz VI -68 ƒIN = 10MHz V -60 dB ƒIN = 5MHz VI 58 dB ƒIN = 10MHz V 56 dB ƒIN = 5MHz VI 70 dB ƒIN = 10MHz V 61 dB Differential Phase V 0.2 deg Differential Gain V 0.5 % Effective Number of Bits Total Harmonic Distortion Signal-To-Noise and Distortion Spurious Free Dynamic Range 2 57 9.0 56 62 -61 dB REV. 1B October 2003 SPT7851 DATA SHEET Electrical Specifications (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65V, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) Parameter Conditions Test Level Min Typ Max Units Logic 1 Voltage VI 80% VDD Logic 0 Voltage VI 20% VDD Digital Inputs Maximum Input Current Low VIN = GND VI ±1 µA Maximum Input Current High VIN = VDD VI ±1 µA Input Capacitance V 1.8 pF 90% VDD V Digital Outputs Logic 1 Voltage IO = -2mA VI Logic 0 Voltage IO = +2mA VI CLK to Output Delay Time (tD) 85% VDD 0.1 0.4 V IV 4 8 12 ns Supply Voltage (VDD1, VDD2, VDD3) IV 2.8 3.3 3.6 V Supply Current (IDD) VI 24 30 mA Power Dissipation VI 79 100 mW Power Supply Rejection Ratio V 67 Power Supply Requirements dB TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL IV V VI TEST PROCEDURE Parameter is guaranteed (but not tested) by design or characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25°C. Parameter is guaranteed over specified temperature range. Absolute Maximum Ratings (beyond which the device may be damaged) Parameter Min Max Units -0.5 +6 V Analog and Digital Input -0.5 VDD +0.5 V VREF+, VREF–, CLK -0.5 VDD +0.5 V Operating Temperature Range -40 +85 °C Storage Temperature Range -65 +125 °C Supply Voltages VDD1, VDD2,VDD3 Input Voltages Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. REV. 1B October 2003 3 DATA SHEET SPT7851 Typical Performance Characteristics (TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65, ƒCLK = 20 MSPS, Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted) THD, SNR, SINAD vs. Input Frequency THD, SNR, SINAD vs. Sample Rate 80 70 SNR THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 80 THD 60 SINAD 50 40 30 70 THD SNR 60 SINAD 50 40 30 NOTE: Bias1 and Bias2 currents optimized for each sample rate 20 20 100 101 100 102 101 Input Frequency (MHz) THD, SNR, SINAD vs. Temperature Power Dissipation vs. Sample Rate 150 68 Power Dissipation (mW) THD, SNR, SINAD (dB) 70 THD 66 64 62 60 SNR 58 125 100 75 50 25 NOTE: Bias1 and Bias2 currents optimized for each sample rate SINAD 56 0 -40 -25 0 25 50 70 100 85 101 Temperature ( °C) Bias1 Voltage vs. Bias1 Current Bias2 Voltage vs. Bias2 Current 0.90 3.0 VBias1 2.19 2.53 2.79 3 3.22 IBias2 3 6 9 12 15 0.85 VBias2 (V) IBias1 30 60 90 120 150 3.2 VBias1 (V) 102 Sample Rate (MSPS) 3.4 2.8 2.6 2.4 0.80 VBias2 0.6975 0.7535 0.796 0.8295 0.8595 0.75 0.70 0.65 2.2 0.60 2.0 0 30 60 90 120 IBIAS1 (µA) 4 102 Sample Rate (MSPS) 150 180 0 3 6 9 12 15 18 IBIAS2 (µA) REV. 1B October 2003 SPT7851 DATA SHEET Sampling Points N N-1 N+1 N+2 tAP N+6 N+7 N+8 AIN CLK tD DOUT N-2 N-1 N Figure 1: Timing Diagram General Description Typical Interface Circuit The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC. It has a pipelined architecture and incorporates digital error correction of all 10 bits. This error correction ensures good linearity performance for input frequencies up to Nyquist. The inputs are fully differential, making the device insensitive to system-level noise. This device can also be used in a single-ended mode. (See analog input section.) With the power dissipation roughly proportional to the sampling rate, this device is ideal for very low power applications in the range of 1 to 20 MSPS. The SPT7851 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7851 in normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to consider for achieving the optimal device performance. +3.3V 4.7 µF Ref- In 10 µF + .01 µF + CLKIN (3V Logic) (+1.15 V) +3.3V Ref+ In (+2.15 V) .01 µF + GND CLK N/C VDD3 VDD2 VDD2 VDD1 VDD1 VDD3 44 DNC N/C DNC Bias1 Bias2 .01 µF D0 U1 SPT7851 D3 D4 51Ω D6 VIN- D7 GND (MSB) 23 AGND D8 GND D9 22 Minicircuit T1-6T D5 VIN+ 68 pF Interfacing 3V Logic D2 GND RFIN (LSB) D1 VCM (+1.65 V) Decoupling Cap N/C GND 9.5 µA VDD1 90 µA VRef+ N/C 1 VRef- 4.7 µF .01 µF 11 12 +3.3V Digital 0.1 µF 34 33 FB DGND Note: 1. All VDD1, VDD2 and VDD3 should be tied together. 2. FB = Ferrite Bead; must be placed as close to U1 as possible. Figure 2: Typical Interface Circuit REV. 1B October 2003 5 DATA SHEET SPT7851 Analog Input References The input of the SPT7851 can be configured in various ways depending on if a single-ended or differential, AC- or DCcoupled input is desired. The SPT7851 has a differential analog input. The voltages applied to the VREF+ and VREF– pins determine the input voltage range and are equal to ±(VREF+ – VREF–). This voltage range will be symmetrical about the common mode voltage. Externally generated reference voltages must be connected to these pins. (See figure 2, Typical Interface Circuit.) For best performance, these voltages should be symmetrical about the midpoint of the supply voltage. Common Mode Voltage The AC coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the VCM pin as shown in Figure 2. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the inputs attenuates kickback noise from the internal sample and hold. Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a a DC-coupled single-ended input is desired. The selection criteria of the buffer op-amps is as follows: • Open loop gain > 75dB • Gain bandwidth product > 50MHz • Total Harmonic Distortion ≤ –75dB • Signal-to-Noise Ratio > 75dB R3 R – + R 51Ω – (R3)/2 Input Voltage (±0.5V) + R2 15pF R2 VIN+ ADC VIN- 51Ω The bias currents suggested (Bias 1 and Bias 2 in figure 2) optimize device performance for the stated sample rate of 20 MSPS. To achieve the best dynamic performance when operating the device at sample rates other than 20 MSPS, the bias current levels should be adjusted. Table I shows the settings for Bias 1 and Bias 2 for selected sample rates. The “Bias Voltage vs Bias Current” graphs on page 4 show the relationship between the bias current and the bias voltage. Please refer to the application note for more information. 51Ω + – Table I – Sample Rate Settings R R The SPT7851 has an on-board common mode voltage reference circuit (VCM). It is typically one-half of the supply voltage and can drive loads of up to 20 µA. This circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Bias Current Circuits R3 VCM Reference Circuit R Sample Rate (MHz) Bias1 (µA) Bias2 (µA) 1 30 3.0 5 50 6.0 Power Supplies and Grounding 10 70 7.5 The SPT7851 is operated from a single power supply in the range of 2.8 to 3.6 volts. Nominal operation is suggested to be 3.3 volts. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. 20 90 9.5 Figure 3: DC-coupled single-ended to differential conversion (power supplies/bypassing not shown) 6 REV. 1B October 2003 SPT7851 DATA SHEET Clock The SPT7851 accepts a low voltage CMOS logic level at the CLK input. The duty cycle of the clock should be kept as close to 50% as possible. Because consecutive stages in the ADC are clocked in opposite phase to each other, a non-50% duty cycle reduces the settling time available for every other stage and thus could potentially cause a degradation of dynamic performance. For optimal performance at high input frequencies, the clock should have low jitter and fast edges. The rise/fall times should be kept shorter than 2ns. Overshoot and undershoot should be avoided. Clock jitter causes the noise floor to rise proportional to the input frequency. Because jitter can be caused by crosstalk on the PC board, it is recommended that the clock trace be kept as short as possible and standard transmission line practices be followed. Digital Outputs The digital output data appears in an offset binary code at 3.3V CMOS logic levels. A negative full scale input results in an all zeros output code (000…0). A positive full scale input results in an all 1’s code (111…1). The output data is available 7.5 clock cycles after the data is sampled. The input signal is sampled on the high to low transition of the input clock. Output data should be latched on the low to high clock transition as shown in figure 1, the Timing Diagram. The output data is invalid for the first 20 clock cycles after the device is powered up. Evaluation Board The EB7851 Evaluation Board is available to aid designers in demonstrating the full performance capability of the SPT7851. The board includes an on-board clock driver, adjustable voltage references, adjustable bias current circuits, single-to-differential input buffers with adjustable levels, a single-to-differential transformer (1:1), digital output buffers and 3.3/5 V adjustable logic outputs. An application note (AN7851) is also available which describes the operation of the evaluation board and provides an example of the recommended power and ground layout and signal routing. Contact the factory for price and availability. Pin Assignments Pin Configuration Pin Name VDD3 DNC DNC D0 (LSB) D1 D2 D3 D4 D5 D6 D7 44 43 42 41 40 39 38 37 36 35 34 GND Description VIN+, VIN– Analog Inputs VREF+, VREF– External Reference Inputs CLK Input Clock 1 33 D8 CLK 2 32 D9 (MSB) N/C 3 31 GND VCM Common Mode Output Voltage (1.65V typ) VDD3 4 30 GND Bias1 Bias Current (90µA typ) VDD2 5 29 GND VDD2 6 28 GND VDD1 7 27 GND VDD1 8 26 VDD1 Bias2 Bias Current (9.5µA typ) D0 – D9 Digital Outputs (D0 = LSB) GND GND Analog Ground VDD1 Analog Power Supply VDD2 Digital Power Supply VDD3 Digital Output Power Supply N/C No connect DNC Do not connect pins; leave floating 9 25 GND VREF– 10 24 GND VREF+ 11 23 GND 22 21 20 19 18 17 16 15 14 13 12 VIN– GND VIN+ GND VCM Bias 2 Bias 1 N/C N/C N/C N/C REV. 1B October 2003 7 DATA SHEET SPT7851 Package Dimensions TQFP-44 A B Pin 1 Index C E D F G K I H J Inches Millimeters Symbol Min 8 Max Min Max A 0.472 Typ 12.00 Typ B 0.394 Typ 10.00 Typ C 0.394 Typ 10.00 Typ D 0.472 Typ 12.00 Typ E 0.031 Typ 0.80 Typ F 0.012 0.018 0.300 0.45 G 0.053 0.057 1.35 1.45 H 0.002 0.006 0.05 0.15 I 0.018 0.030 0.450 0.750 J 0.039 Typ 1.00 Typ K 0-7° 0-7° REV. 1B October 2003 SPT7851 DATA SHEET Ordering Information Model Part Number Package Container Pack Qty SPT7851 SPT7851SIT 44-pin TQFP Tray - Temperature range for all parts: -40°C to +85°C.