TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier Check for Samples: TLV320DAC3100 1 INTRODUCTION 1.1 Features • Stereo Audio DAC with 95-dB SNR • Supports 8-kHz to 192-kHz Sample Rates • Mono Class-D BTL Speaker Driver (2.5 W Into 4-Ω or 1.6 W Into 8-Ω) • Two Single-Ended Inputs With Mixing and Output Level Control • Stereo Headphone/Lineout and Mono Class-D Speaker Outputs Available • Microphone Bias • Headphone Detection • 25 Built-in Digital Audio Processing Blocks (PRB_P1 – PRB_P25) Providing Biquad and FIR Filters, DRC, and 3-D Structures • Digital Mixing Capability • Pin Control or Register Control for DigitalPlayback Volume-Control Settings • Digital Sine-Wave Generator for Beeps and Key Clicks (PRB_P25) • Programmable PLL for Flexible Clock Generation • I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces • I2C™ Control With Register Auto-Increment • Full Power-Down Control • Power Supplies: – Analog: 2.7 V–3.6 V – Digital Core: 1.65 V–1.95 V – Digital I/O: 1.1 V–3.6 V – Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD) • 5-mm × 5-mm 32-QFN Package 1234 1.2 • • • Applications Portable Audio Devices Mobile Internet Devices eBooks 1.3 Description The TLV320DAC3100 is a low-power, highly integrated, high-performance stereo audio DAC with 24-bit stereo playback and digital audio processing blocks. The device integrates headphone drivers and speaker drivers. The mono speaker driver can drive loads down to 4 Ω. The TLV320DAC3100 has a suite of built-in processing blocks for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ can be supported by the programmable digital signalprocessing block. An on-chip PLL provides the highspeed clock needed by the digital signal-processing block. The volume level can be controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus. The TLV320DAC3100 has a programmable digital sine-wave generator and is available in a 32-pin QFN package. TEXT ADDED FOR ALIGNMENT 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP B.V. MATLAB is a trademark of The MathWorks, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVSS AVDD HPVSS HPVDD SPKVSS SPKVSS SPKVDD SPKVDD P0/R116 7-Bit Vol ADC VOL/MICDET Audio Output Stage Power Management Left and Right Volume-Control Register P0/R117 P1/R33–R34 GPIO1 GPIO SDA SCL De-Pop and Soft Start 2 I C RC CLK AIN1 AIN2 Note: Normally, MCLK is PLL input; however, BCLK or GPIO1 can also be P0/R63/D5–D4 PLL input. L Data R Data PLL (L+R)/2 Data MCLK Left DAC Analog Attenuation 0 dB to –78 dB and Mute (0.5-dB Steps) Mono Class-D Speaker Driver P1/R38 P1/R42 AIN1 6 dB to 24 dB (6-dB Steps) S DAC P0/R64 SPKP SPKP SPKM SPKM Analog Class A/B Attenuation Headphone/Lineout Driver 0 dB to –78 dB and Mute 0 dB to 9 dB (0.5-dB Steps) (1-dB Steps) WCLK DIN BCLK P1/R36 Serial Interface and Clocks RESET Process- Digital Vol ing 24 dB to Blocks Mute HPL MIXER P1/R35 P0/R63/D3–D2 DAC P0/R64–R66 P1/R46 Analog Attenuation 0 dB to –78 dB and Mute (0.5-dB Steps) Class-A/B Headphone/Lineout Driver 0 dB to 9 dB (1-dB Steps) P1/R37 P1/R41 Right DAC L Data R Data (L+R)/2 Data MICBIAS P1/R40 AIN2 S HPR P0/R64 2 V/2.5 V/AVDD IOVSS IOVDD DVSS DVDD B0360-03 Figure 1-1. Functional Block Diagram NOTE This data manual is designed using PDF document-viewing features that allow quick access to information. For example, performing a global search on "page 0 / register 27" produces all references to this page and register in a list. This makes it easy to traverse the list and find all information related to a page and register. Note that the search string must be of the indicated format. Also, this document includes document hyperlinks to allow the user to find a document reference quickly. To come back to the original page, click the green left arrow near the PDF page number at the bottom of the file. The hot-key for this function is alt-left arrow on the keyboard. Another way to find information quickly is to use the PDF bookmarks. 2 INTRODUCTION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320DAC3100 QFN-32 RHB –40°C to 85°C 2.2 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLV320DAC3100IRHBT Tape and reel, 250 TLV320DAC3100IRHBR Tape and reel, 3000 Device Information SPKP SPKVDD SPKVSS SPKM DVSS AVDD SPKVDD 24 25 SPKVSS SPKM RHB Package (Top View) 23 22 21 20 19 18 17 16 AVSS SPKP 26 15 NC 14 AIN2 HPL 27 HPVDD 28 13 AIN1 HPVSS 29 12 MICBIAS HPR 30 11 VOL/MICDET RESET 31 10 SCL 9 SDA 32 1 2 3 4 5 6 7 8 IOVDD DVDD NC DIN WCLK BCLK MCLK GPIO1 IOVSS TLV320DAC3100 P0048-16 Table 2-1. TERMINAL FUNCTIONS TERMINAL NAME NO. AIN1 13 AIN2 AVDD I/O DESCRIPTION I Analog input #1 routed to output mixer 14 I Analog input #2 routed to output mixer 17 – Analog power supply AVSS 16 – Analog ground BCLK 7 I/O DIN 5 I Audio serial data input DVDD 3 – Digital power – digital core DVSS 18 – Digital ground GPIO1 32 I/O General-purpose input/output and multifunction pin HPL 27 O Left-channel headphone/line driver output HPR 30 O Right-channel headphone/line driver output HPVDD 28 – Headphone/line driver and PLL power HPVSS 29 – Headphone/line driver and PLL ground IOVDD 2 – Interface power IOVSS 1 – Interface ground MCLK 8 I Exterrnal master clock Audio serial bit clock Copyright © 2010–2012, Texas Instruments Incorporated PACKAGE AND SIGNAL DESCRIPTIONS Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 3 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. MICBIAS I/O DESCRIPTION 12 – Microphone bias for external microphone 4, 15 I No connecton RESET 31 I Device reset SCL 10 I/O I2C control bus clock input SDA 9 I/O I2C control bus data input SPKM 19, 23 O Cass-D speaker driver inverting output SPKP 22, 26 O Class-D speaker driver noninverting output SPKVDD 21, 24 – Class-D speaker driver power supply SPKVSS 20, 25 – Class-D speaker driver power-supply ground VOL/MICDET 11 I Volume control or headphone detection. Note that microphone detection is also available on devices that have an ADC. WCLK 6 I/O NC Audio serial word clock 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT AVDD to AVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V HPVDD to HPVSS –0.3 to 3.9 V –0.3 to 6 V –0.3 to 3.9 V Digital input voltage IOVSS – 0.3 to IOVDD + 0.3 V Analog input voltage AVSS – 0.3 to AVDD + 0.3 V Operating temperature range –40 to 85 °C Storage temperature range –55 to 150 °C 105 °C SPKVDD to SPKVSS IOVDD to IOVSS Junction temperature (TJ Max) Power dissipation RθJA thermal impedance (with thermal pad soldered to board) (1) (TJ Max – TA)/RθJA W 35 °C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 3-1. System Thermal Characteristics (1) (1) 4 Power Rating at 25°C Derating Factor Power Rating at 70°C Power Rating at 85°C 2.3 W 28.57 mW/°C 1W 0.6 W This data was taken using 2-oz. (0.071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer 3-in. × 3in. (7.62-cm × 7.62-cm) PCB. ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 3.2 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX AVDD (1) (2) 2.7 3.3 3.6 Referenced to DVSS(2) 1.65 1.8 1.95 Referenced to HPVSS(2) 2.7 3.3 3.6 Referenced to SPKVSS(2) 2.7 Referenced to AVSS DVDD Power-supply voltage range HPVDD SPKVDD (1) (2) IOVDD Referenced to IOVSS VI Resistance applied across class-D output pins (BTL) Headphone impedance AC-coupled to RL Analog audio full-scale input voltage AVDD = 3.3 V, single-ended Stereo line output load impedance AC coupled to RL MCLK (3) Master clock frequency IOVDD = 3.3 V fSCL SCL clock frequency TA Operating free-air temperature (1) (2) (3) 1.1 Speaker impedance UNIT V 5.5 3.3 3.6 4 Ω 16 Ω 0.70 7 VRMS 10 –40 kΩ 50 MHz 400 kHz 85 °C To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level. All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS. The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock. 3.3 Electrical Characteristics At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL OSCILLATOR—RC_CLK Oscillator frequency 8.2 MHz VOLUME CONTROL PIN (ADC); VOL/MICDET PIN ENABLED Input voltage range VOL/MICDET pin configured as volume control (page 0 / register 116, bit D7 = 1 and page 0 / register 67, bit D7 = 0) 0.5 × AVDD 0 Input capacitance 2 Volume control steps V pF 128 Steps Microphone Bias Page 1 / register 46, bits D1–D0 = 10 2.25 2.5 2.75 Voltage output V Page 1 / register 46, bits D1–D0 = 01 2 At 4-mA load current, page 1 / register 46, bits D1–D0 = 10 (MICBIAS = 2.5 V) 5 At 4-mA load current, page 1 / register 46, bits D1–D0 = 01 (MICBIAS = 2 V) 7 Voltage regulation mV AUDIO DAC DAC Headphone Output, AC-Coupled Load = 16 Ω (Single-Ended), Driver Gain = 0 dB, Parasitic Capacitance = 30 pF Full-scale output voltage (0 dB) Output common-mode setting = 1.65 V SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted (1) 0.707 THD Total harmonic distortion 0-dBFS input –85 –65 dB THD+N Total harmonic distortion + noise 0-dBFS input –82 –60 dB (2) 80 Mute attenuation Vrms 95 dB 87 dB –62 dB DAC Headphone Output, AC-Coupled Load = 16 Ω (Single-Ended), Driver Gain = 0 dB, Parasitic Capacitance = 30 pF (Continued) PSRR PO (1) (2) (3) Power-supply rejection ratio (3) Maximum output power Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz RL = 32 Ω, THD+N ≤ –60 dB 20 RL = 16 Ω, THD+N ≤ –60 dB 60 mW Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × log( ΔVHPL / ΔVHPVDD). ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 5 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Lineout (HP Driver in Lineout Mode) SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted 95 dB THD Total harmonic distortion 0-dBFS input, 0-dB gain –86 dB THD+N Total harmonic distortion + noise 0-dBFS input, 0-dB gain –82 dB DAC Digital Interpolation Filter Characteristics See Section 5.5.1.4 for DAC interpolation filter characteristics. DAC Output to Class-D SPEAKER OUTPUT; Load = 4 Ω (Differential), 50 pF SPKVDD = 3.6 V, BTL measurement, DAC input = 0 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD ≤ –16.5 dB 2.3 SPKVDD = 3.6 V, BTL measurement, DAC input = –2 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD ≤ –20 dB 2.1 Output, common-mode SPKVDD = 3.6 V, BTL measurement, DAC input = mute, class-D gain = 6 dB 1.8 V SNR Signal-to-noise ratio SPKVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.3 Vrms) 88 dB THD Total harmonic distortion SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB –65 dB THD+N Total harmonic distortion + noise SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB –63 dB PSRR Power-supply rejection ratio SPKVDD = 3.6 V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 1 kHz –44 dB 110 dB Output voltage Vrms Mute attenuation PO Maximum output power SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% 1 SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% 1.5 SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% 2.5 W DAC Output to Class-D Speaker Output; Load = 8 Ω (Differential), 50 pF SPKVDD = 3.6 V, BTL measurement, DAC input = 0 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD ≤ –16.5 dB 2.2 SPKVDD = 3.6 V, BTL measurement, DAC input = –2 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD ≤ –20 dB 2.1 Output, common-mode SPKVDD = 3.6 V, BTL measurement, DAC input = mute, class-D gain = 6 dB 1.8 V SNR Signal-to-noise ratio SPKVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.2 Vrms) 87 dB THD Total harmonic distortion SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB –67 dB THD+N Total harmonic distortion + noise SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB –66 dB PSRR Power-supply rejection ratio (1) SPKVDD = 3.6 V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 1 kHz –44 dB 110 dB Output voltage Vrms Mute attenuation SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% PO Maximum output power Output-stage leakage current for direct battery connection 0.7 SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% 1 SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% 1.6 SPKVDD = 4.3 V, device is powered down (power-up-reset condition) 80 W nA DAC POWER CONSUMPTION For DAC power consumption based per selected processing block, see Section 5.3. DIGITAL INPUT/OUTPUT Logic family VIH VIL Logic level CMOS IIH = 5 μA, IOVDD ≥ 1.6 V 0.7 × IOVDD IIH = 5 μA, IOVDD < 1.6 V IOVDD IIL = 5 μA, IOVDD ≥ 1.6 V –0.3 IOH = two TTL loads VOL IOL = two TTL loads V 0 0.8 × IOVDD V 0.1 × IOVDD Capacitive load 6 0.3 × IOVDD IIL = 5 μA, IOVDD < 1.6 V VOH (1) V 10 V pF DAC to speaker-out PSRR is a differential measurement calculated as PSRR = 20 × log( ΔVSPK(P + M) / ΔVSPKVDD) . ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 3.4 3.4.1 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tr td(WS) BCLK tf tS(DI) th(DI) DIN T0145-10 PARAMETER td(WS) ts(DI) th(DI) tr tf WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 6 6 10 10 UNIT ns ns ns ns ns Figure 3-1. I2S/LJF/RJF Timing in Master Mode ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 7 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com I2S/LJF/RJF Timing in Slave Mode 3.4.2 All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tr th(WS) tS(WS) tH(BCLK) BCLK tL(BCLK) tS(DI) tf DIN th(DI) T0145-11 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 35 35 8 8 8 8 4 4 IOVDD = 3.3 V MIN MAX 35 35 6 6 6 6 4 4 UNIT ns ns ns ns ns ns ns ns Figure 3-2. I2S/LJF/RJF Timing in Slave Mode 8 ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 3.4.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK td(WS) td(WS) tf BCLK tr tS(DI) DIN th(DI) T0146-09 PARAMETER td(WS) ts(DI) th(DI) tr tf WCLK delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 8 8 25 25 IOVDD = 3.3 V MIN MAX 20 8 8 10 10 UNIT ns ns ns ns ns Figure 3-3. DSP Timing in Master Mode ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 9 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 3.4.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK tS(WS) tS(WS) th(WS) th(WS) tf tL(BCLK) BCLK tS(DI) tH(BCLK) tr DIN th(DI) T0146-10 PARAMETER tH(BCLK) tL(BCLK) ts(WS) th(WS) ts(DI) th(DI) tr tf BCLK high period BCLK low period WCLK setup WCLK hold DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 35 35 8 8 8 8 4 4 IOVDD = 3.3 V MIN MAX 35 35 8 8 8 8 4 4 UNIT ns ns ns ns ns ns ns ns Figure 3-4. DSP Timing in Slave Mode 10 ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 3.4.5 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time, (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time: for I2C bus devices Data set-up time SDA and SCL rise time SDA and SCL fall time Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Standard Mode MIN TYP 0 MAX 100 Fast Mode MIN TYP 0 MAX 400 UNIT kHz 4 0.8 μs 4.7 4 1.3 0.6 μs μs 4.7 0.8 μs 0 250 3.45 4 0 100 20 + 0.1Cb 20 + 0.1Cb 0.8 4.7 1.3 1000 300 400 0.9 300 300 μs ns ns ns μs μs 400 pF Figure 3-5. I2C Interface Timing ELECTRICAL SPECIFICATIONS Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 11 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 4 TYPICAL PERFORMANCE 4.1 DAC Performance Added Text for Spacing AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −40 Amplitude − dBFS −40 Amplitude − dBFS AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 15 20 f − Frequency − kHz G001 Figure 4-1. FFT - DAC to Line Output TEXT ADDED FOR SPACING G002 Figure 4-2. FFT - DAC to Headphone Output TEXT ADDED FOR SPACING TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − dB 0 −10 HPVDD = 2.7 V CM = 1.35 V −20 −30 −40 HPVDD = 3 V CM = 1.5 V −50 HPVDD = 3.3 V CM = 1.65 V −60 HPVDD = 3.6 V CM = 1.8 V −70 IOVDD = 3.3 V DVDD = 1.8 V Driver Gain = 9 dB RL = 16 Ω −80 −90 −100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 PO − Output Power − W 0.14 G003 Figure 4-3. Headphone Output Power 12 TYPICAL PERFORMANCE Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 4.2 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Class-D Speaker Driver Performance Added Text for Spacing TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 0 AVDD = HPVDD = 3.3 V IOVDD = 3.3 V SPKVDD = 5.5 V DVDD = 1.8 V RL = 4 Ω −10 −20 THD+N − Total Harmonic Distortion + Noise − dB THD+N − Total Harmonic Distortion + Noise − dB 0 Driver Gain = 24 dB −30 Driver Gain = 18 dB −40 Driver Gain = 12 dB −50 Driver Gain = 6 dB −60 −70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 PO − Output Power − W −10 −20 SPKVDD = 3.6 V −30 SPKVDD = 4.3 V SPKVDD = 5.5 V −40 AVDD = 3.3 V HPVDD = 3.3 V IOVDD = 3.3 V DVDD = 1.8 V Driver Gain = 18 dB RL = 4 Ω −50 −60 −70 0.0 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 PO − Output Power − W G004 G005 Figure 4-4. Max Class-D Speaker-Driver Output Power (RL = 4 Ω) Added Text for Spacing Figure 4-5. Class-D Speaker-Driver Output Power (RL = 4 Ω) Added Text for Spacing TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 0 −10 −20 0 AVDD = HPVDD = 3.3 V IOVDD = 3.3 V SPKVDD = 5.5 V DVDD = 1.8 V RL = 8 Ω Driver Gain = 18 dB −30 −40 Driver Gain = 24 dB Driver Gain = 12 dB −50 Driver Gain = 6 dB −60 −70 0.0 THD+N − Total Harmonic Distortion + Noise − dB THD+N − Total Harmonic Distortion + Noise − dB SPKVDD = 3.3 V 0.5 1.0 1.5 PO − Output Power − W 2.0 2.5 SPKVDD = 3.3 V −10 −20 SPKVDD = 3.6 V −30 SPKVDD = 4.3 V SPKVDD = 5.5 V −40 AVDD = 3.3 V HPVDD = 3.3 V IOVDD = 3.3 V DVDD = 1.8 V Driver Gain = 18 dB RL = 8 Ω −50 −60 −70 0.0 0.5 G006 Figure 4-6. Max Class-D Speaker-Driver Output Power (RL = 8 Ω) 1.0 1.5 2.0 2.5 PO − Output Power − W 3.0 G007 Figure 4-7. Class-D Speaker-Driver Output Power (RL = 8 Ω) TYPICAL PERFORMANCE Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 13 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 4.3 www.ti.com Analog Bypass Performance Added Text for Spacing AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −40 Amplitude − dBFS −40 Amplitude − dBFS AVDD = HPVDD = 3.3 V IOVDD = SPKVDD = 3.3 V DVDD = 1.8 V −20 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 G008 Figure 4-8. FFT - Line In Bypass to Line Output 4.4 15 20 f − Frequency − kHz G009 Figure 4-9. FFT - Line In Bypass to Headphone Output MICBIAS Performance Added Text for Spacing VOLTAGE vs CURRENT 3.5 3.0 Micbias = AVDD (3.3 V) V − Voltage − V 2.5 Micbias = 2.5 V 2.0 Micbias = 2 V 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I − Current − mA G010 Figure 4-10. MICBIAS 14 TYPICAL PERFORMANCE Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration +3.3VA SVDD 0.1 mF IOVDD 22 mF 0.1 mF 22 mF 0.1 mF 0.1 mF 10 mF 10 mF Rp ´ 2 SPKVDD SPKVDD HPVDD AVDD SPKVSS SPKVSS AVSS HPVSS SDA HOST PROCESSOR SCL GPIO1 MCLK SPKP SPKP SPKM SPKM WCLK DIN BCLK 8-W or 4-W Speaker TLV320DAC3100 RESET To External MIC Circuitry Analog In MICBIAS HPL AIN1 HPR Stereo Headphone Out AIN2 AVDD 34.8 kW 25 kW VOL/MICDET 1 mF 9.76 kW AVSS DVDD DVSS +1.8VD 0.1 mF IOVDD IOVSS IOVDD 10 mF 0.1 mF 10 mF S0400-08 Figure 5-1. Typical Circuit Configuration 5.2 Overview The TLV320DAC3100 is a highly integrated stereo audio DAC for portable computing, communication, and entertainment applications. A register-based architecture eases integration with microprocessor-based systems through standard serial-interface buses. This device supports the two-wire I2C bus interface, which provides full register access. All peripheral functions are controlled through registers and the onboard state machines. The TLV320DAC3100 consists of the following blocks: • Stereo audio DAC • Dynamic range compressor (DRC) APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 15 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 • • • • • • • • www.ti.com Digital sine-wave generator for clicks and beeps Stereo headphone/lineout amplifier Class-D mono amplifier capable of driving 4-Ω speakers Pin-controlled or register-controlled volume level Power-down de-pop and power-up soft start Analog inputs I2C control interface Power-down control block Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C interface is used to write to the control registers to configure the device. The I2C address assigned to the TLV320DAC3100 is 001 1000. This device always operates in an I2C slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device autoincrements to support sequential addressing and can be used with I2C fast mode. Once the device is reset, all appropriate registers are updated by the host processor to configure the device as needed by the user. 5.2.1 Device Initialization 5.2.1.1 Reset The TLV320DAC3100 internal logic must be initialized to a known condition for proper device function. To initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low. The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the device. 5.2.1.2 Device Start-Up Lockout Times After the TLV320DAC3100 is initialized through hardware reset at power up or software reset, the internal memories are initialized to default values. This initialization takes place within 1 ms after pulling the RESETsignal high. During this initialization phase, no register-read or register-write operation should be performed on DAC coefficient buffers. Also, no block within the codec should be powered up during the initialization phase. 5.2.1.3 PLL Start-Up Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up command of the PLL and before the clocks are available to the codec. This delay is to ensure stable operation of the PLL and clock-divider logic. 5.2.1.4 Power-Stage Reset The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has occurred. Using this reset re-enables the output stage without resetting all of the registers in the device. Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is performed by setting page 1/ register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPKP and SPKM. 16 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 5.2.1.5 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Software Power Down By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit block can be controlled by writing to the appropriate control register. This approach allows the lowest power-supply current for the functionality required. However, when a block is powered down, all of the register settings are maintained as long as power is still being applied to the device. 5.2.2 Audio Analog I/O The TLV320DAC3100 has a stereo audio DAC. It supports a wide range of analog interfaces to support different headsets and analog outputs. The TLV320DAC3100 has features to interface output drivers (8-Ω, 16-Ω, 32-Ω). A special circuit has also been included in the TLV320DAC3100 to insert a short key-click sound into the stereo audio output. The key-click sound is used to provide feedback to the user when a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and amplitude. See Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25), Section 5.5.7. 5.3 Digital Processing Low-Power Modes The TLV320DAC3100 device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The choice of processing blocks, PRB_P1 to PRB_P25 for stereo playback, also influences the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice among configurations having a different balance of power optimization and signal-processing capabilities. 5.3.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.28 mW Table 5-1. PRB_P7 Alternative Processing Blocks, 24.28 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.34 PRB_P2 A 2.86 PRB_P3 A 2.11 PRB_P8 B 1.18 PRB_P9 B 0.53 PRB_P10 B 1.89 PRB_P11 B 0.87 PRB_P23 A 1.48 PRB_P24 A 2.89 PRB_P25 A 3.23 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 17 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 24.5 mW Table 5-2. PRB_P7 Alternative Processing Blocks, 24.5 mW 5.3.2 Processing Block Filter Estimated Power Change (mW) PRB_P1 A 1.17 PRB_P2 A 2.62 PRB_P3 A 2 PRB_P8 B 0.99 PRB_P9 B 0.5 PRB_P10 B 1.46 PRB_P11 B 0.66 PRB_P23 A 1.43 PRB_P24 A 2.69 PRB_P25 A 2.92 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.4 mW Table 5-3. PRB_P12 Alternative Processing Blocks, 15.4 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.57 PRB_P5 A 1.48 PRB_P6 A 1.08 PRB_P13 B 0.56 PRB_P14 B 0.27 PRB_P15 B 0.89 PRB_P16 B 0.31 DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.54 mW Table 5-4. PRB_P12 Alternative Processing Blocks, 15.54 mW 18 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.37 PRB_P5 A 1.23 PRB_P6 A 1.15 PRB_P13 B 0.43 PRB_P14 B 0.13 PRB_P15 B 0.85 PRB_P16 B 0.21 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 5.3.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.44 mW Table 5-5. PRB_P7 Alternative Processing Blocks, 22.44 mW Processing Block Filter Estimated Power Change (mW) PRB_P1 A 0.02 PRB_P2 A 0.31 PRB_P3 A 0.23 PRB_P8 B 0.28 PRB_P9 B –0.03 PRB_P10 B 0.14 PRB_P11 B 0.05 PRB_P23 A 0.29 PRB_P24 A 0.26 PRB_P25 A 0.47 DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 22.83 mW Table 5-6. PRB_P7 Alternative Processing Blocks, 22.83 mW 5.3.4 Processing Block Filter Estimated Power Change (mW) PRB_P1 A 0.27 PRB_P2 A 0.4 PRB_P3 A 0.34 PRB_P8 B 0.2 PRB_P9 B 0.08 PRB_P10 B 0.24 PRB_P11 B 0.12 PRB_P23 A 0.23 PRB_P24 A 0.42 PRB_P25 A 0.46 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.49 mW Table 5-7. PRB_P12 Alternative Processing Blocks, 14.49 mW Processing Block Filter Estimated Power Change (mW) PRB_P4 A –0.04 PRB_P5 A 0.2 PRB_P6 A –0.01 PRB_P13 B 0.1 PRB_P14 B 0.05 PRB_P15 B –0.03 PRB_P16 B 0.07 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 19 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 14.42 mW Table 5-8. PRB_P12 Alternative Processing Blocks, 14.42 mW 5.3.5 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.16 PRB_P5 A 0.3 PRB_P6 A 0.2 PRB_P13 B 0.15 PRB_P14 B 0.07 PRB_P15 B 0.18 PRB_P16 B 0.09 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C) Power consumption = 27.05 mW Table 5-9. PRB_P17 Alternative Processing Blocks, 27.05 mW 5.3.6 Processing Block Filter Estimated Power Change (mW) PRB_P18 C 5.28 PRB_P19 C 1.98 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B) Power consumption = 12.85 mW 5.4 Analog Signals The TLV320DAC3100 analog signals consist of: • Microphone bias (MICBIAS) • Analog inputs AIN1 and AIN2 • Analog outputs, class-D speaker driver and headphone/lineout driver, providing output capability for the DAC, AIN1, AIN2 or a mix of the three 5.4.1 MICBIAS The TLV320DAC3100 includes a microphone bias circuit which can source up to 4 mA of current and is programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 / register 46, bits D1–D0. This functionality is shown in Table 5-10. Table 5-10. MICBIAS Settings 20 D1 D0 0 0 MICBIAS output is powered down. FUNCTIONALITY 0 1 MICBIAS output is powered to 2 V. 1 0 MICBIAS output is powered to 2.5 V. 1 1 MICBIAS output is powered to AVDD. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the model of microphone that is selected, optimal performance might be obtained at another setting, so the performance at a given setting should be verified. The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current consumption occurs when MICBIAS is set at AVDD. The highest current consumption occurs when MICBIAS is set a 2 V. 5.4.2 Analog Inputs AIN1 and AIN2 AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 / register 35 provides control signals for determining the signals routed through the output mixer. The output of the output mixer then can be attenuated or gained through the class-D and/or headphone/lineout drivers. 5.5 Audio DAC and Audio Analog Outputs Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital delta-sigma modulator, and an analog reconstruction filter. The DAC high oversampling ratio (normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include stereo headphone/lineouts and mono class-D speaker outputs. 5.5.1 DAC The TLV320DAC3100 stereo audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320DAC3100 allows the system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates. The TLV320DAC3100 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on required frequency response, group delay, and sampling rate. DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6. 5.5.1.1 DAC Processing Blocks The TLV320DAC3100 implements signal-processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they use and which interpolation filter is applied. The choices among these processing blocks allow the system designer to balance power conservation and signal-processing flexibility. Table 5-11 gives an overview of all available processing blocks of the DAC channel and their properties. The resource-class column gives an approximate indication of power consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog power consumption of the drivers (HPVDD) may differ. The signal processing blocks available are: • First-order IIR • Scalable number of biquad filters APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 21 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 • • www.ti.com 3D effect Digital sine-wave (beep) generator The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal-processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. Table 5-11. Overview – DAC Predefined Processing Blocks Processing Block No. Interpolation Filter Channel First-Order IIR Available Number of Biquads DRC 3D Beep Generator Resource Class PRB_P1 A Stereo No 3 No No No 8 PRB_P2 A Stereo Yes 6 Yes No No 12 PRB_P3 A Stereo Yes 6 No No No 10 PRB_P4 A Left No 3 No No No 4 PRB_P5 A Left Yes 6 Yes No No 6 PRB_P6 A Left Yes 6 No No No 6 PRB_P7 B Stereo Yes 0 No No No 6 PRB_P8 B Stereo No 4 Yes No No 8 PRB_P9 B Stereo No 4 No No No 8 PRB_P10 B Stereo Yes 6 Yes No No 10 PRB_P11 B Stereo Yes 6 No No No 8 PRB_P12 B Left Yes 0 No No No 3 PRB_P13 B Left No 4 Yes No No 4 PRB_P14 B Left No 4 No No No 4 PRB_P15 B Left Yes 6 Yes No No 6 PRB_P16 B Left Yes 6 No No No 4 PRB_P17 C Stereo Yes 0 No No No 3 PRB_P18 C Stereo Yes 4 Yes No No 6 PRB_P19 C Stereo Yes 4 No No No 4 PRB_P20 C Left Yes 0 No No No 2 PRB_P21 C Left Yes 4 Yes No No 3 PRB_P22 C Left Yes 4 No No No 2 PRB_P23 A Stereo No 2 No Yes No 8 PRB_P24 A Stereo Yes 5 Yes Yes No 12 PRB_P25 A Stereo Yes 5 Yes Yes Yes 12 5.5.1.2 DAC Processing Blocks – Signal Chain Details 5.5.1.2.1 Three Biquads, Filter A BiQuad A from Interface BiQuad B BiQuad C Interp. Filter A ´ to Modulator Digital Volume Ctrl Figure 5-2. Signal Chain for PRB_P1 and PRB_P4 22 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F HPF ´ to Modulator Digital Volume Ctrl DRC Figure 5-3. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15 5.5.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F to Modulator ´ Digital Volume Ctrl Figure 5-4. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16 5.5.1.2.4 IIR, Filter B or C Interp. Filter B,C IIR from Interface ´ to Modulator Digital Volume Ctrl Figure 5-5. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20 5.5.1.2.5 Four Biquads, DRC, Filter B from Interface BiQuad A BiQuad B BiQuad C Interp. Filter B BiQuad D HPF ´ to Modulator Digital Volume Ctrl DRC Figure 5-6. Signal Chain for PRB_P8 and PRB_P13 5.5.1.2.6 Four Biquads, Filter B BiQuad A from Interface BiQuad B BiQuad C BiQuad D Interp. Filter B ´ to Modulator Digital Volume Ctrl Figure 5-7. Signal Chain for PRB_P9 and PRB_P14 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 23 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C BiQuad A IIR BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to Modulator from Interface HPF Digital Volume Ctrl DRC Figure 5-8. Signal Chain for PRB_P18 and PRB_P21 5.5.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-9. Signal Chain for PRB_P19 and PRB_P22 5.5.1.2.9 Two Biquads, 3D, Filter A From LeftChannel Interface + Biquad BL + Biquad CL Interp. Filter A ´ To Modulator + Digital Volume Ctrl + From RightChannel Interface Biquad AL + – Biquad AR 3D PGA + – + Biquad BR Biquad CR Interp. Filter A ´ To Modulator Digital Volume Ctrl NOTE: AL means biquad A of the left channel, and similarly, BR means biquad B of the right channel. Figure 5-10. Signal Chain for PRB_P23 24 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.2.10 Five Biquads, DRC, 3D, Filter A IIR from Left Left Channel Interface + BiQuad CL BiQuad BL + BiQuad DL BiQuad EL BiQuad FL Interp. Filter A to Modulator ´ + HPF + BiQuad AL + - Digital Volume Ctrl DRC 3D PGA BiQuad AR from Right Channel Interface IIR Right + BiQuad BR + BiQuad CR BiQuad DR BiQuad ER BiQuad FR HPF Interp. Filter A to Modulator ´ Digital Volume Ctrl DRC Figure 5-11. Signal Chain for PRB_P24 5.5.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A From LeftChannel Interface IIR Left + Biquad BL + Biquad CL Biquad DL Biquad EL Biquad FL Interp. Filter A HPF DRC + ´ + + + – Biquad AL Biquad AR 3D PGA To Modulator Digital Volume Ctrl Beep Volume Ctrl ´ Beep Volume Ctrl ´ Beep Gen. From RightChannel Interface – IIR Right + + Biquad BR Biquad CR Biquad DR Biquad ER Biquad FR Interp. Filter A HPF DRC ´ + To Modulator Digital Volume Ctrl Figure 5-12. Signal Chain for PRB_P25 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 25 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.3 www.ti.com DAC User-Programmable Filters Depending on the selected processing block, different types and orders of digital filtering are available. Up to six biquad sections are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched in real time. When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed for either read or write. However, the TLV320DAC3100 offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients can be updated through the host and activated without stopping and restarting the DAC. This enables advanced adaptive filtering applications. In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At the same time, page 8 / register 1, bit D1 toggles. The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use. Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use. While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless of the buffer to which the coefficients have been written. Table 5-12. Adaptive-Mode Filter-Coefficient Buffer Switching DAC Running? Page 8, Reg 1, Bit D1 No 0 None Coefficient Buffer in Use Buffer A Writing to Buffer A Updates No 0 None Buffer B Buffer B Yes 0 Buffer A Buffer A Buffer B Yes 0 Buffer A Buffer B Buffer B Yes 1 Buffer B Buffer A Buffer A Yes 1 Buffer B Buffer B Buffer A The user-programmable coefficients for the DAC processing blocks are defined on page 8 and page 9 for buffer A and page 12 and page 13 for buffer B. The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 5-13. 2 –15 2 2 –4 –1 Bit Bit Largest Positive Number: = 0.111111111111111111 = 0.999969482421875 = 1.0 – 1 LSB Bit Largest Negative Number: = 1.000010000100001000 = 0x8000 = –1.0 (by definition) Fraction Point Sign Bit S...xxxxxxxxxxxxxxxxxx Figure 5-13. 1.15 2s-Complement Coefficient Format 26 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.1.3.1 First-Order IIR Section The IIR is of first order and its transfer function is given by H(z) = N0 + N1z -1 215 - D1z -1 (1) The frequency response for the first-order IIR section with default coefficients is flat. Table 5-13. DAC IIR Filter Coefficients Filter Coefficient Left DAC Channel Right DAC Channel First-order IIR N0 Page 9 / register 2 and page 9 / register 3 Page 9 / register 8 and page 9 / register 9 0x7FFF (decimal 1.0 – LSB value) Default (Reset) Value N1 Page 9 / register 4 and page 9 / register 5 Page 9 / register 10 and page 9 / register 11 0x0000 D1 Page 9 / register 6 and page 9 / register 7 Page 9 / register 12 and page 9 / register 13 0x0000 5.5.1.3.2 Biquad Section The transfer function of each of the biquad filters is given by H(z) = N0 + 2 ´ N1z -1 + N2 z -2 215 - 2 ´ D1z -1 - D2 z -2 (2) Table 5-14. DAC Biquad Filter Coefficients Filter Biquad A Biquad B Biquad C Coefficient Left DAC Channel N0 Page 8 / register 2 and page 8 / register 3 Page 8 / register 66 and page 8 / register 67 Right DAC Channel 0x7FFF (decimal 1.0 – LSB value) Default (Reset) Value N1 Page 8 / register 4 and page 8 / register 5 Page 8 / register 68 and page 8 / register 69 0x0000 N2 Page 8 / register 6 and page 8 / register 7 Page 8 / register 70 and page 8 / register 71 0x0000 D1 Page 8 / register 8 and page 8 / register 9 Page 8 / register 72 and page 8 / register 73 0x0000 D2 Page 8 / register 10 and page 8 / register 11 Page 8 / register 74 and page 8 / register 75 0x0000 N0 Page 8 / register 12 and page 8 / register 13 Page 8 / register 76 and page 8 / register 77 0x7FFF (decimal 1.0 – LSB value) N1 Page 8 / register 14 and page 8 / register 15 Page 8 / register 78 and page 8 / register 79 0x0000 N2 Page 8 / register 16 and page 8 / register 17 Page 8 / register 80 and page 8 / register 81 0x0000 D1 Page 8 / register 18 and page 8 / register 19 Page 8 / register 82 and page 8 / register 83 0x0000 D2 Page 8 / register 20 and page 8 / register 21 Page 8 / register 84 and page 8 / register 85 0x0000 N0 Page 8 / register 22 and page 8 / register 23 Page 8 / register 86 and page 8 / register 87 0x7FFF (decimal 1.0 – LSB value) N1 Page 8 / register 24 and page 8 / register 25 Page 8 / register 88 and page 8 / register 89 0x0000 N2 Page 8 / register 26 and page 8 / register 27 Page 8 / register 90 and page 8 / register 91 0x0000 D1 Page 8 / register 28 and page 8 / register 29 Page 8 / register 92 and page 8 / register 93 0x0000 D2 Page 8 / register 30 and page 8 / register 31 Page 8 / register 94 and page 8 / register 95 0x0000 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 27 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-14. DAC Biquad Filter Coefficients (continued) Filter Coefficient Biquad D Biquad E Biquad F 5.5.1.4 Left DAC Channel Right DAC Channel Default (Reset) Value N0 Page 8 / register 32 and page 8 / register 33 Page 8 / register 96 and page 8 / register 97 0x7FFF (decimal 1.0 – LSB value) N1 Page 8 / register 34 and page 8 / register 35 Page 8 / register 98 and page 8 / register 99 0x0000 N2 Page 8 / register 36 and page 8 / register 37 Page 8 / register 100 and page 8 / register 101 0x0000 D1 Page 8 / register 38 and page 8 / register 39 Page 8 / register 102 and page 8 / register 103 0x0000 D2 Page 8 / register 40 and page 8 / register 41 Page 8 / register 104 and page 8 / register 105 0x0000 N0 Page 8 / register 42 and page 8 / register 43 Page 8 / register 106 and page 8 / register 107 0x7FFF (decimal 1.0 – LSB value) N1 Page 8 / register 44 and page 8 / register 45 Page 8 / register 108 and page 8 / register 109 0x0000 N2 Page 8 / register 46 and page 8 / register 47 Page 8 / register 110 and page 8 / register 111 0x0000 D1 Page 8 / register 48 and page 8 / register 49 Page 8 / register 112 and page 8 / register 113 0x0000 D2 Page 8 / register 50 and page 8 / register 51 Page 8 / register 114 and page 8 / register 115 0x0000 N0 Page 8 / register 52 and page 8 / register 53 Page 8 / register 116 and page 8 / register 117 0x7FFF (decimal 1.0 – LSB value) N1 Page 8 / register 54 and page 8 / register 55 Page 8 / register 118 and page 8 / register 119 0x0000 N2 Page 8 / register 56 and page 8 / register 57 Page 8 / register 120 and page 8 / register 121 0x0000 D1 Page 8 / register 58 and page 8 / register 59 Page 8 / register 122 and page 8 / register 123 0x0000 D2 Page 8 / register 60 and page 8 / register 61 Page 8 / register 124 and page 8 / register 125 0x0000 DAC Interpolation Filter Characteristics 5.5.1.4.1 Interpolation Filter A Filter A is designed for an fS up to 48 ksps with a flat pass band of 0 kHz–20 kHz. Table 5-15. Specification for DAC Interpolation Filter A Parameter Condition Value (Typical) Unit Filter-gain pass band 0 … 0.45 fS ±0.015 dB Filter-gain stop band 0.55 fS … 7.455 fS –65 dB 21/fS s Filter group delay 28 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DAC Channel Response for Interpolation Filter A (Red Line Corresponds to –65 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 1 2 5 6 3 4 Frequency Normalized to fS 7 Figure 5-14. Frequency Response of DAC Interpolation Filter A 5.5.1.4.2 Interpolation Filter B Filter B is specifically designed for an fS up to 96 ksps. Thus, the flat pass-band region easily covers the required audio band of 0 kHz–20 kHz. Table 5-16. Specification for DAC Interpolation Filter B Parameter Condition Value (Typical) Unit Filter-gain pass band 0 … 0.45 fS ±0.015 dB Filter-gain stop band 0.55 fS … 3.45 fS –58 dB 18/fS s Filter group delay DAC Channel Response for Interpolation Filter B (Red Line Corresponds to –58 dB) 0 Magnitude – dB –10 –20 –30 –40 –50 –60 –70 –80 0.5 1 1.5 2 2.5 Frequency Normalized to fS 3 3.5 Figure 5-15. Frequency Response of Channel Interpolation Filter B 5.5.1.4.3 Interpolation Filter C Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × fS (corresponds to 80 kHz), more than sufficient for audio applications. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 29 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-17. Specification for DAC Interpolation Filter C Parameter Condition Value (Typical) Unit Filter-gain pass band 0 … 0.35 fS ±0.03 dB Filter-gain stop band 0.6 fS … 1.4 fS –43 dB 13/fS s Filter group delay DAC Channel Response for Interpolation Filter C (Red Line Corresponds to –43 dB) 0 Magnitude – dB –10 –20 –30 –40 –50 –60 –70 0 0.2 0.4 0.6 0.8 1 1.2 Frequency Normalized to fS 1.4 Figure 5-16. Frequency Response of DAC Interpolation Filter C 5.5.2 DAC Digital-Volume Control The DAC has a digital volume-control block which implements programmable gain. Each channel has an independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The left-channel DAC volume can be controlled by writing to page 0 / register 65, bits D7–D0. The right-channel DAC volume can be controlled by writing to page 0 / register 66, bits D7–D0. DAC muting and setting up a master gain control to control both channels is done by writing to page 0 / register 64, bits D3–D0. The gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples by writing to page 0 / register 63, bits D1–D0. Note that the default source for volume-control level settings is control by register writes (page 0 / register 65 and page 0 / register 66 to control volume). Use of the VOL/MICDET pin to control the DAC volume is ignored until the volume control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This functionality is shown in Figure 1-1. During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This may be important if the host must mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host via a readonly register, page 0 / register 38, bit D4 for the left channel and bit D0 for the right channel. This information alerts the host when the device has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled by writing to page 0 / register 63, bits D1–D0. If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an internal oscillator.) 30 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 5.5.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Volume-Control Pin The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63, bits D1–D0. When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and updates the digital volume control. (It overwrites the current value of the volume control.) The new volume setting which has been applied due to a change of voltage on the volume control pin can be read on page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source can be selected on page 0 / register 116, bit D6. The update rate can be programmed on page 0 / register 116, bits D2–D0 for this 7bit SAR ADC. The VOL/MICDET pin gainmapping is shown in Table 5-18. Table 5-18. VOL/MICDET Pin Gain Mapping VOL/MICDET PIN SAR OUTPUT DIGITAL GAIN APPLIED 0 18 dB 1 17.5 dB 2 17 dB : : 35 0.5 dB 36 0.0 dB 37 –0.5 dB : : 89 –26.5 dB 90 –27 dB 91 –28 dB : : 125 –62 dB 126 –63 dB 127 Mute APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 31 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com The VOL/MICDET pin connection and functionality are shown in Figure 5-17. 24 dB to Mute Digital DAC_L D-S DAC Vol Ctl Processing Blocks 24 dB to Mute AVDD Digital VREF IN R1 AVDD VOL/ MICDET DAC_R Vol Ctl D-S DAC Processing Blocks 18 dB to Mute P1 7- Bit ADC R2 CVOL Tone Generator and Mixer Are NOT Shown 24 dB to Mute Volume Level Register Controlled AVSS B0210-08 Figure 5-17. Digital Volume Controls for Beep Generator and DAC Play Data As shown in Table 5-18, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB, and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied to the VOL/MICDET pin. This can be done by increasing the value of R2 relative to the value of (P1 + R1), so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed AVDD/2 (see Figure 5-17). The recommended values for R1, R2, and P1 for several maximum gains are shown in Table 5-19. Table 5-19. VOL/MICDET Pin Gain Scaling 5.5.4 R1 (kΩ) P1 (kΩ) R2 (kΩ) ADC VOLTAGE for AVDD = 3.3 V (V) DIGITAL GAIN RANGE (dB) 25 25 0 0 V to 1.65 V 18 dB to –63 dB 33 25 7.68 0.386 V to 1.642 V 3 dB to –63 dB 34.8 25 9.76 0.463 V to 1.649 V 0 dB to –63 dB Dynamic Range Compression Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome this problem, dynamic range conpression (DRC) in the TLV320DAC3101 continuously monitors the output of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear, as well as sounding louder during nominal periods. The DRC functionality in the TLV320DAC3101 is implemented by a combination of processing blocks in the DAC channel as described in Section 5.5.1.2. DRC can be disabled by writing to page 0 / register 68, bits D6–D5. 32 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 DRC typically works on the filtered version of the input signal. The input signals have no audio information at dc and extremely low frequencies; however, they can significantly influence the energy estimation function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is concentrated in the low-frequency region of the input signal. To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the DRC low-pass filter. These filters are implemented as first-order IIR filters given by HHPF (z) = HLPF (z) = N0 + N1z -1 215 - D1z -1 N0 + N1z (3) -1 215 - D1z -1 (4) The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable through register write as given in Table 5-20. Table 5-20. The DRC HPF and LPF Coefficients Coefficient Location HPF N0 C71 page 9 / register 14 and page 9 / register 15 HPF N1 C72 page 9 / register 16 and page 9 / register 17 HPF D1 C73 page 9 / register 18 and page 9 / register 19 LPF N0 C74 page 9 / register 20 and page 9 / register 21 LPF N1 C75 page 9 / register 22 and page 9 / register 23 LPF D1 C76 page 9 / register 24 and page 9 / register 25 The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_fS, and a low-pass filter with a cutoff at 0.00033 × DAC_fS. The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The absolute value of the DRC LPF filter is used for energy estimation within the DRC. The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66. When the DRC is enabled, the applied gain is a function of the digital volume-control register setting and the output of the DRC. The DRC parameters are described in sections that follow. 5.5.4.1 DRC Threshold DRC threshold represents the level of the DAC playback signal at which the gain compression becomes active. The output of the digital volume control in the DAC is compared with the set threshold. The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the output signal. The recommended DRC threshold value is –24 dB. When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44, bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits D3–D2. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 33 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 5.5.4.2 www.ti.com DRC Hysteresis DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be programmed to represent values between 0 dB and 3 dB in steps of 1 dB. DRC hysteresis provides a programmable window around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled, or the enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC hysteresis is set to 3 dB, then if the gain compression in the DRC is inactive, the output of the DAC digital volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly, when the gain compression in the DRC is active, the output of the DAC digital volume control must fall below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature prevents the rapid activation and de-activation of gain compression in the DRC in cases when the output of the DAC digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By programming the DRC hysteresis as 0 dB, the hysteresis action is disabled. The recommended value of DRC hysteresis is 3 dB. 5.5.4.3 DRC Hold Time DRC hold time is intended to slow the start of decay for a specified period of time in response to a decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0 through programming page 0 / register 69, bits D6–D3 = 0000. 5.5.4.4 DRC Attack Rate When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4. Attack rates can be programmed from 4-dB gain change per sample period to 1.2207e–5-dB gain change per sample period. Attack rates should be programmed such that before the output of the DAC digital volume control can clip, the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and tooslow attack rates may not be able to prevent the input signal from clipping. The recommended DRC attack rate value is 1.9531e–4 dB per sample period. 5.5.4.5 DRC Decay Rate When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from 1.5625e–3 dB per sample period to 4.7683e–7 dB per sample period. If the decay rates are programmed too fast, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, then the output may be perceived as too low for a long time after the peak signal has passed. The recommended value of DRC decay rate is 2.4414e–5 dB per sample period. 34 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 5.5.4.6 • • • • • • SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Example Setup for DRC Digital Vol gain = 12 dB Threshold = –24 dB Hysteresis = 3 dB Hold time = 0 ms Attack rate = 1.9531e–4 dB per sample period Decay rate = 2.4414e–5 dB per sample period Script # Select Page 0 w 30 00 00 # DAC => 12 db gain left w 30 41 18 # DAC => 12 db gain right w 30 42 18 # DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB w 30 44 7F # DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' w 30 45 00 # Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame w 30 46 B6 # Select Page 9 w 30 00 09 # DRC HPF w 30 0E 7F AB 80 55 7F 56 # DRC LPF W 30 14 00 11 00 11 7F DE 5.5.5 Headphone Detection The TLV320DAC3100 includes capability to monitor a headphone jack to determine if a plug has been inserted into the jack. Figure 5-18 shows the circuit configuration to enable this feature. HPR HPL VOL/MICDET MICBIAS Micdet Micbias Figure 5-18. Jack Connections for Headphone Detection APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 35 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com This feature is enabled by programming page 0 / register 67, bit D1. In order to avoid false detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms to 512 ms is provided. This can be programmed via page 0 / register 67, bits D4–D2. For improved button-press detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register 67, bits D1–D0. The TLV320DAC3100 also provides feedback to the user through register-readable flags, as well as an interrupt on the I/O pins when a button press or a headset insertion/removal event is detected. The value in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion. Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected. Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320DAC3100 also provides an interrupt feature, whereby events can trigger the INT1 and/or INT2 interrupts. These interrupt events can be routed to one of the digital output pins. See Section 5.5.6 for details. The TLV320DAC3101 not only detects a headset insertion event, but also is able to distinguish between the different headsets inserted, such as stereo headphones or cellular headphones. After the headsetdetection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of headset inserted. Table 5-21. Headset-Detection Block Registers Register Description Page 0 / register 67, bits D4–D2 Debounce programmability for headset detection Page 0 / register 67, bits D1–D0 Debounce programmability for button press Page 0 / register 67, bits D6–D5 Flags for type of headset detected Page 0/ register 46, bit D5 Status flag for button-press event Page 0 / register 46, bit D4 Status flag for headset insertion and removal Page 0 / register 44, bit D5 Sticky flag for button-press event Page 0 / register 44, bit D4 Sticky flag for headset-insertion or -removal event The headset detection block requires AVDD to be powered. The headset detection feature in the TLV320DAC3101 is achieved with very low power overhead, requiring less than 20 μA of additional current from the AVDD supply. 5.5.6 Interrupts Some specific events in the TLV320DAC3100, which may require host processor intervention, can be used to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The TLV320DAC3101 has two defined interrupts, INT1 and INT2, that can be configured by programming page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be triggered by one or many events, such as: • Headset detection • Button press • DAC DRC signal exceeding threshold • Overcurrent condition in headphone drivers/speaker drivers • Data overflow in the DAC processing blocks and filters Each of these INT1 and INT2 interrupts can be routed to pin GPIO1. These interrupt signals can either be configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and page 0 / register 49, bit D0. If the user configures the interrupts as a series of pulses, the events trigger the start of pulses that stop when the flag registers in page 0 / register 44 page 0 / register 45, and page 0 / register 50 are read by the user to determine the cause of the interrupt. 36 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 5.5.7 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) A special algorithm has been included in the digital signal processing block PRB_P25 for generating a digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the beep generator in this document. This functionality is intended for generating key-click sounds or beeps for user feedback. The sine-wave generator is very flexible (see Table 5-22) and is completely register programmable. Programming page 0 / register 71 through page 0 / register 79 (8 bits each) completely controls the functionality of this generator and allows for differentiating sounds. The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of sine wave in the audio band to be generated, up to fS/2. The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through page 0 / register 75. The resolution (bit) in the registers of the sine-burst length is one sample time, so this allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports 16,777,215 sample times. (For example, if fS is set at 48 kHz, and the register value equals 96,000d (01 7700h), then the sine burst lasts exactly 2 seconds.) The default settings for the tone generator, based on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five cycles (5 ms). Table 5-22. Beep Generator Register Locations (Page 0x00) REGISTER LEFT BEEP CONTROL RIGHT BEEP CONTROL BEEP LENGTH SINE COSINE MSB MID LSB MSB LSB MSB LSB 71 72 73 74 75 76 77 78 79 Table 5-23. Example Beep-Generator Settings for a 1000-Hz Tone BEEP FREQUENCY (1) BEEP LENGTH (Cycles = 5) SINE COSINE SAMPLE RATE Hz MSB (hex) MID (hex) LSB (hex) MSB (hex) LSB (hex) MSB (hex) LSB (hex) Hz 1000 (1) 0 0 F0 10 B5 7E E8 48,000 These are the default settings. Two registers are used to control the left sine-wave volume and the right sine-wave volume independently. The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right channels of the beep generator can be set up by writing to page 0 / register 72, bits D7–D6. The default volume control setting is 2 dB, which provides the maximum tone-generator output level. For generating other tones, the three tone-generator coefficients can be found by running the following script using MATLAB™ : Sine = dec2hex(round(sin(2*pi*Fin/Fs)*2^15)) Cosine = dec2hex(round(cos(2*pi*Fin/Fs)*2^15)) Beep Length = dec2hex(floor(Fs*Cycles/Fin)) where, fin = Beep frequency desired fS = Sample rate Cycles= Number of beep (sine wave) cycles that are needed dec2hex = Decimal to hexadecimal conversion function APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 37 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com NOTES: 1. fin should be less than fS/4. 2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused MSBs must be written as 0s. 3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs must be written as 0s. Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has already been set by the DAC volume control. Therefore, once the key-click volume level is set, the keyclick volume is not affected by the DAC volume control, which is the main control available to the end user. This functionality is shown in Figure 1-1. Following the DAC, the signal can be further scaled by the analog output volume control and poweramplifier level control. The beep generator is used for the key-click function. A single beep is generated by writing to page 0 / register 71, bit D7. After the programmed beep length has finished, register 71, bit D7 is reset back to zero. 5.5.8 Programming DAC Digital Filter Coefficients The digital filter coefficients must be programmed through the I2C interface. All digital filtering for the DAC signal path must be loaded into the RAM before the DAC is powered on. (Note that default ALLPASS filter coefficients for programmable biquads are located in boot ROM. The boot ROM automatically loads the default values into the RAM following a hardware reset (toggling the RESET pin) or after a software reset. After resetting the device, loading boot ROM coefficients into the digital filters requires 100 μs of programming time. During this time, reading or writing to page 8 through page 15 for updating DAC filter coefficient values is not permitted. (The DAC should not be powered up until after all of the DAC configurations have been initialized by the system microprocessor.) 5.5.9 Updating DAC Digital Filter Coefficients During PLAY When it is required to update the DAC digital filter coefficients or beep generator during play, care must be taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the DAC coefficients are updated without following the proper update sequence. The correct sequence is shown in Figure 5-19. The values for times listed in Figure 5-19 are conservative and should be used for software purposes. There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For details, see Section 5.5.1.3. 38 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Play - Paused Volume Ramp Down Soft Mute DAC Volume Ramp Down WAIT Time (A) Wait (A) ms For fS = 32 kHz ® Wait 25 ms (min) For fS = 48 kHz ® Wait 20 ms (min) DAC Power Down Update Digital Filter Coefficients DAC Volume Ramp Up Time (B) For fS = 32 kHz ® 25 ms For fS = 48 kHz ® 20 ms DAC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 5-19. Example Flow for Updating DAC Digital Filter Coefficients During Play 5.5.10 Digital Mixing and Routing The TLV320DAC3101 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the digital audio data. This arrangement of digital mixers allows independent volume control for both the playback data and the key-click sound. The first set of mixers can be used to make monaural signals from left and right audio data, or they can even be used to swap channels to the DAC. This function is accomplished by selecting left audio data for the right DAC input, and right data for the left DAC input. The second set of mixers provides mixing of the audio data stream and the key-click sound. The digital routing can be configured by writing to page 0 / register 63, bits D5–D4 for the left channel and bits D3–D2 for the right channel. Because the key-click function uses the digital signal-processing block, the CODEC_CLKIN, DAC, analog volume control, and output driver must be powered on for the key-click sound to occur. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 39 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.11 Analog Audio Routing The TLV320DAC3100 has the capability to route the DAC output to either the headphone or the speaker output. If desirable, both output drivers can be operated at the same time while playing at different volume levels. The TLV320DAC3100 provides various digital routing capabilities, allowing digital mixing or even channel swapping in the digital domain. All analog outputs other than the selected ones can be powered down for optimal power consumption. 5.5.11.1 Analog Output Volume Control The output volume control can be used to fine-tune the level of the mixer amplifier signal supplied to the headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels for each of the four output drivers. This volume control can also be used as part of the output pop-noisereduction scheme. This feature is available even if the DAC is powered down. 5.5.11.2 Headphone Analog Output Volume Control For the headphone outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, which is shown in Table 5-24. This volume control includes softstepping logic. Routing the left-channel DAC output signal to the left-channel analog volume control is done by writing to page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the rightchannel analog volume control is done by writing to page 1 / register 35, bit D2. Changing the left-channel analog volume for the headphone is controlled by writing to page 1 / register 36, bits D6–D0. Changing the right-channel analog volume for the headphone is controlled by writing to page 1 / register 37, bits D6–D0. Routing the signal from the output of the left-channel analog volume control to the input of the left-channel headphone power amplifier is done by writing to page 1 / register 36, bit D7. Routing the signal from the output of the right-channel analog volume control to the input of the right-channel headphone power amplifier is done by writing to page 1 / register 37, bit D7. The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0. 40 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-24. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) Register Value (D6–D0) (1) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) Register Value (D6–D0) Analog Gain (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.0 34 –17.0 64 –32.1 94 –47.4 5 –2.5 35 –17.5 65 –32.6 95 –47.9 6 –3.0 36 –18.1 66 –33.1 96 –48.2 7 –3.5 37 –18.6 67 –33.6 97 –48.7 8 –4.0 38 –19.1 68 –34.1 98 –49.3 9 –4.5 39 –19.6 69 –34.6 99 –50.0 10 –5.0 40 –20.1 70 –35.2 100 –50.3 11 –5.5 41 –20.6 71 –35.7 101 –51.0 12 –6.0 42 –21.1 72 –36.2 102 –51.4 13 –6.5 43 –21.6 73 –36.7 103 –51.8 14 –7.0 44 –22.1 74 –37.2 104 –52.2 15 –7.5 45 –22.6 75 –37.7 105 –52.7 16 –8.0 46 –23.1 76 –38.2 106 –53.7 17 –8.5 47 –23.6 77 –38.7 107 –54.2 18 –9.0 48 –24.1 78 –39.2 108 –55.3 19 –9.5 49 –24.6 79 –39.7 109 –56.7 20 –10.0 50 –25.1 80 –40.2 110 –58.3 21 –10.5 51 –25.6 81 –40.7 111 –60.2 22 –11.0 52 –26.1 82 –41.2 112 –62.7 23 –11.5 53 –26.6 83 –41.7 113 –64.3 24 –12.0 54 –27.1 84 –42.1 114 –66.2 25 –12.5 55 –27.6 85 –42.7 115 –68.7 26 –13.0 56 –28.1 86 –43.2 116 –72.2 27 –13.5 57 –28.6 87 –43.8 117–127 –78.3 28 –14.0 58 –29.1 88 –44.3 29 –14.5 59 –29.6 89 –44.8 Mute when D7 = 0 and D6–D0 = 127 (0x7F). 5.5.11.3 Class-D Speaker Analog Output Volume Control For the mono speaker outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for most of the useful range plus mute, as seen in Table 5-24. The implementation includes softstepping logic. Routing the left-channel DAC output signal to the left-channel analog volume control is done by writing to page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the right-channel analog volume control is done by writing to page 1 / register 35, bit D2. Changing the left-channel analog volume for the speaker is controlled by writing to page 1 / register 38, bits D6–D0. Changing the right-channel analog volume for the speaker is controlled by writing to page 1 / register 39, bits D6–D0. Routing the signal from the output of the left-channel analog volume control to the input of the mono speaker amplifier is done by writing to page 1 / register 38, bit D7. The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 41 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.12 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, Figure 1-1. 5.5.12.1 Headphone Drivers The TLV320DAC3100 features a stereo headphone driver (HPL and HPR) that can deliver up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load. The headphones are used in a single-ended configuration where an ac-coupling (dc-blocking) capacitor is connected between the device output pins and the headphones. The headphone driver also supports 32-Ω and 10-kΩ loads without changing any control register settings. The headphone drivers can be configured to optimize the power consumption in the lineout-drive mode by writing 11 to page 1 / register 44, bits D2–D1. The output common mode of the headphone/lineout drivers can be programmed to 1.35 V, 1.5 V, 1.65 V, or 1.8 V by setting page 1 / register 31, bits D4–D3. The common-mode voltage should be set ≤ AVDD/2. The left headphone driver can be powered on by writing to page 1 / register 31, bit D7. The right headphone driver can be powered on by writing to page 1 / register 31, bit D6. The left-output driver gain can be controlled by writing to page 1 / register 40, bits D6–D3, and it can be muted by writing to page 1 / register 40, bit D2. The right-output driver gain can be controlled by writing to page 1 / register 41, bits D6–D3, and it can be muted by writing to page 1 / register 41, bit D2. The TLV320DAC3100 has a short-circuit protection feature for the headphone drivers, which is always enabled to provide protection. The output condition of the headphone driver during short circuit can be programmed by writing to page 1 / register 31, bit D1. If D1 = 0 when a short circuit is detected, the device limits the maximum current to the load. If D1 = 1 when a short circuit is detected, the device powers down the output driver. The default condition for headphones is the current-limiting mode. In case of a short circuit on either channel, the output is disabled and a status flag is provided as read-only bits on page 1 / register 31, bit D0. If shutdown mode is enabled, then as soon as the short circuit is detected, page 1 / register 31, bit D7 (for HPL) and/or page 1 / register 31, bit D6 (for HPR) clears automatically. Next, the device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated headphone power-stage reset can also be used to re-enable the output stage, and that keeps all of the other device settings. The headphone power-stage reset is done by setting page 1 / register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for HPR. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended, as this could lead to overheating. 5.5.12.2 Speaker Drivers The TLV320DAC3100 has an integrated class-D mono speaker driver (SPKP/SPKM) capable of driving a 4-Ω or an 8-Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolute-maximum voltage of 6 V. The speaker driver is capable of supplying 2.5 W with a 5.5-V power supply (4-Ω load). Through the use of digital mixing, the device can connect one or both digital audio playback data channels to the speaker driver. The mono class-D speaker driver can be powered on by writing to page 1 / register 32, bit D7. The mono output-driver gain can be controlled by writing to page 1 / register 42, bits D4–D3, and it can be muted by writing to page 1 / register 42, bit D2. 42 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The TLV320DAC3100 has a short-circuit protection feature for the speaker driver that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker-driver output stage.) In case of a short circuit, the output is disabled and a status flag is provided as a read-only bit on page 1 / register 32, bit D0. If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires either toggling the RESETpin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The speaker power-stage reset is done by setting page 1 / register 32, bit D7 for SPKP and SPKM. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended, as this could lead to overheating. To minimize battery current leakage, the SPKVDD and SPKVDD voltage levels should not be less than the AVDD voltage level. The TLV320DAC3100 has a thermal protection (OTP) feature for the speaker drivers which is always enabled to provide protection. If the device is overheated, then the output stops switching. When the device cools down, the device resumes switching. An overtemperature status flag is provided as a readonly bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die temperature can be controlled at the system/board level, then overtemperature does not occur. 5.5.13 Audio Output-Stage Power Configurations After the device has been configured (following a RESET) and the circuitry has been powered up, the audio output stage can be powered up and powered down by register control. These functions soft-start automatically. By using these register controls, it is possible to control these three output-stage configurations independently. See Table 5-25 for register control of audio output-stage power configurations. Table 5-25. Audio-Output Stage-Power Configurations Audio Output Pins Desired Function Page 1 / Register, Bit Values Power down HPL driver Page 1 / register 31, bit D7 = 0 Power up HPL driver Page 1 / register 31, bit D7 = 1 Power down HPR driver Page 1 / register 31, bit D6 = 0 Power up HPR driver Page 1 / register 31, bit D6 = 1 Power down mono class-D driver Page 1 / register 32, bit D7 = 0 Power up mono class-D driver Page 1 / register 32, bit D7 = 1 HPL HPR SPKP / SPKM 5.5.14 DAC Setup The following paragraphs are intended to guide a user through the steps necessary to configure the TLV320DAC3101. Step 1 The system clock source (master clock) and the targeted DAC sampling frequency must be identified. Depending on the targeted performance, the decimation filter type (A, B, or C) and DOSR value can be determined: • Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8. • Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4. • Filter C should be used for up to 192-kHz operations; DOSR must be a multiple of 2. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 43 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com In all cases, DOSR is limited in its range by the following condition: 2.8 MHz < DOSR × DAC_fS < 6.2 MHz Based on the identified filter type and the required signal-processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25). Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock-divider values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of flexibility. In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate, DAC_fS. The CODEC_CLKIN clock signal is shared with the DAC clock-generation block. CODEC_CLKIN = NDAC × MDAC × DOSR × DAC_fS To a large degree, NDAC and MDAC can be chosen independently in the range of 1 to 128. In general, NDAC should be as large as possible as long as the following condition can still be met: MDAC × DOSR / 32 ≥ RC RC is a function of the chosen processing block and is listed in Table 5-11. The common-mode voltage setting of the device is determined by the available analog power supply. At this point, the following device-specific parameters are known: PRB_Rx, DOSR, NDAC, MDAC, input and output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined as well. Step 2 Setting up the device via register programming: The following list gives an example sequence of items that must be executed in the time between powering the device up and reading data from the device. Note that there are other valid sequences, depending on which features are used. 1. Define starting point: (a) Power up applicable external power supplies (b) Set register page to 0 (c) Initiate SW reset 2. Program clock settings (a) Program PLL clock dividers P, J, D, and R (if PLL is used) (b) Power up PLL (if PLL is used) (c) Program and power up NDAC (d) Program and power up MDAC (e) Program OSR value (f) Program I2S word length if required (16, 20, 24, or 32 bits) (g) Program the processing block to be used (h) Micellaneous page 0 controls 44 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 3. Program analog blocks (a) Set register page to 1 (b) Program common-mode voltage (c) Program headphone-specific de-pop settings (in case headphone driver is used) (d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker) (e) Unmute and set gain of output drivers (f) Power up output drivers 4. Apply waiting time determined by the de-pop settings and the soft-stepping settings of the driver gain, or poll page 1 / register 63 5. Power up DAC (a) Set register page to 0 (b) Power up DAC channels and set digital gain (c) Unmute digital volume control A detailed example can be found in Section 5.5.15. 5.5.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs A typical EVM I2C register control script follows to show how to set up the TLV320DAC3101 in playback mode with fS = 44.1 kHz and MCLK = 11.2896 MHz. # Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY # # ==> comment delimiter # # The following list gives an example sequence of items that must be executed in the time # between powering the # device up and reading data from the device. Note that there are # other valid sequences depending on which features are used. # 1. Define starting point: # (a) Power up applicable external hardware power supplies # (b) Set register page to 0 # w 30 00 00 # # (c) Initiate SW reset (PLL is powered off as part of reset) # w 30 01 01 # # 2. Program clock settings # (a) Program PLL clock dividers P, J, D, R (if PLL is used) # # PLL_clkin = MCLK,codec_clkin = PLL_CLK w 30 04 03 # J = 8 w 30 06 08 # D = 0000, D(13:8) = 0, D(7:0) = 0 w 30 07 00 00 # # (b) Power up PLL (if PLL is used) # PLL Power up, P = 1, R = 1 # w 30 05 91 # # (c) Program and power up NDAC # # NDAC is powered up and set to 8 w 30 0B 88 # # (d) Program and power up MDAC # # MDAC is powered up and set to 2 w 30 0C 82 # # (e) Program OSR value APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 45 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com # # DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128 w 30 0D 00 80 # # (f) Program I2S word length if required (16, 20, 24, 32 bits) # and master mode (BCLK and WCLK are outputs) # # mode is i2s, wordlength is 16, slave mode w 30 1B 00 # (g) Program the processing block to be used # # Select Processing Block PRB_P11 w 30 3C 0B w 30 00 08 w 30 01 04 w 30 00 00 # # (h) Miscellaneous page 0 controls # # DAC => volume control thru pin disable w 30 74 00 # 3. Program analog blocks # # (a) Set register page to 1 # w 30 00 01 # # (b) Program common-mode voltage (defalut = 1.35 V) # w 30 1F 04 # # (c) Program headphone-specific depop settings (in case headphone driver is used) # # De-pop, Power on = 800 ms, Step time = 4 ms w 30 21 4E # # (d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker) # # LDAC routed to HPL out, RDAC routed to HPR out w 30 23 44 # # (e) Unmute and set gain of output driver # # Unmute HPL, set gain = 0 db w 30 28 06 # Unmute HPR, set gain = 0 dB w 30 29 06 # Unmute Class-D, set gain = 18 dB w 30 2A 1C # # (f) Power up output drivers # # HPL and HPR powered up w 30 1F C2 # Power-up Class-D driver w 30 20 86 # Enable HPL output analog volume, set = -9 dB w 30 24 92 # Enable HPR output analog volume, set = -9 dB w 30 25 92 # Enable Class-D output analog volume, set = -9 dB w 30 26 92 # # 4. Apply waiting time determined by the de-pop settings and the soft-stepping settings # of the driver gain or poll page 1 / register 63 # # 5. Power up DAC # (a) Set register page to 0 # w 30 00 00 # # (b) Power up DAC channels and set digital gain # 46 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com # w # # w # w # # # # w 5.6 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Powerup DAC left and right channels (soft step enabled) 30 3F D4 DAC Left gain = -22 dB 30 41 D4 DAC Right gain = -22 dB 30 42 D4 (c) Unmute digital volume control Unmute DAC left and right channels 30 40 00 CLOCK Generation and PLL The TLV320DAC3100 supports a wide range of options for generating clocks for the DAC section as well as interface and other control blocks, as shown in Figure 5-20. The clocks for the DAC require a source reference clock. This clock can be provided on variety of device pins, such as the MCLK, BCLK, or GPIO1 pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0 / register 4, bits D1–D0. CODEC_CLKIN can then be routed through highly-flexible clock dividers, shown in Figure 5-20, to generate the various clocks required for the DAC. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the TLV320DAC3100 also provides the option of using the on-chip PLL, which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TLV320DAC3100 provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 47 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com BCLK MCLK DIN GPIO1 PLL_CLKIN PLL ´ (R ´ J.D)/P BCLK MCLK GPIO1 PLL_CLK CODEC_CLKIN ¸ NDAC To DAC MAC NDAC = 1, 2, ..., 127, 128 DAC_CLK ¸ MDAC MDAC = 1, 2, ..., 127, 128 DAC_MOD_CLK ¸ DOSR DOSR = 1, 2, ..., 1023, 1024 DAC_fS B0357-04 Figure 5-20. Clock Distribution Tree DAC _ MOD _ CLK = DAC _ fS = CODEC _ CLKIN NDAC ´ MDAC CODEC _ CLKIN NDAC ´ MDAC ´ DOSR (5) Table 5-26. CODEC CLKIN Clock Dividers Divider 48 Bits NDAC Page 0 / register 11, bits D6–D0 MDAC Page 0 / register 12, bits D6–D0 DOSR Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel, DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 / register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence, the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 / register 37, bit D3. When both the flags indicate power-down, the MDAC divider may be powered down, followed by the NDAC divider. In general, for proper operation, all the root clock dividers should be powered down only after the child clock dividers have been powered down. The TLV320DAC3100 also has options for routing some of the internal clocks to the GPIO1 pin to be used as general-purpose clocks in the system. The feature is shown in Figure 5-22. DAC_CLK DAC_MOD_CLK BDIV_CLKIN ÷N N = 1, 2, ..., 127, 128 BCLK B0362-01 Figure 5-21. BCLK Output Options In the mode when the TLV320DAC3100 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed in page 0 / register 30, bits D6–D0 from 1 to 128. BDIV_CLKIN can itself be configured to be one of DAC_CLK (DAC processing clock), DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-purpose clock can be driven out on GPIO1. This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. CDIV_CLKIN can itself be programmed as one of the clocks among the list shown in Figure 5-22. This can be controlled by programming the multiplexer in page 0 / register 25, bits D2–D0. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 49 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com PLL_CLK MCLK BCLK DIN DAC_MOD_CLK DAC_CLK CDIV_CLKIN M = 1, 2, ..., 127, 128 ÷M GPIO1 (CLKOUT) B0363-01 Figure 5-22. General-Purpose Clock Output Options Table 5-27. Maximum TLV320DAC3100 Clock Frequencies DVDD ≥ 1.65 V Clock CODEC_CLKIN ≤ 110 MHz DAC_CLK (DAC processing clock) ≤ 49.152 MHz DAC_MAC_CLK ≤ 49.152 MHz with DRC disabled ≤ 48 MHz with DRC enabled DAC_MOD_CLK 6.758 MHz DAC_fS 0.192 MHz BDIV_CLKIN 55 MHz CDIV_CLKIN 100 MHz when M is odd 110 MHz when M is even 5.6.1 PLL For lower power consumption, it is best to derive the internal audio processing clocks using the simple dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing clocks, then it is necessary to use the onboard PLL. The TLV320DAC3100 fractional PLL can be used to generate an internal master clock used to produce the processing clocks needed by the DAC. The programmability of this PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable generation of the required sampling rates with fine resolution. The PLL can be turned on by writing to page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by the following equation: PLL_CLKIN ´ R ´ J.D PLL_CLK = P (6) where R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1) J = 1, 2,3, … , 63, (page 0 / register 6, default value = 4) D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0) P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1) 50 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 / register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0, and the LSB portion is programmed via page 0 / register 8, bits D7–D0. For proper update of the D divider value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. Unless the write to page 0 / register 8 is completed, the new value of D does not take effect. When the PLL is enabled, the following conditions must be satisfied: • When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN: PLL _ CLKIN 512 kHz £ £ 20 MHz P 80 MHz ≤ (PLL_CLKIN × J.D × R/P)≤ 110 MHz 4 ≤ R × J ≤ 259 (7) When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN: PLL _ CLKIN 10 MHz £ £ 20 MHz P • 80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz R=1 (8) The PLL can be powered up independently from the DAC block, and can also be used as a generalpurpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms. The clock for the codec and various signal processing blocks, CODEC_CLKIN, can be generated from the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0). If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last. Table 5-28 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to achieve a sample rate fS of either 44.1 kHz or 48 kHz. Table 5-28. PLL Example Configurations PLL_CLKIN (MHz) PLLP PLLR PLLJ 2.8224 1 3 10 5.6448 1 3 5 12 1 1 13 1 1 16 1 19.2 48 PLLD MDAC NDAC DOSR 0 3 5 128 0 3 5 128 7 560 3 5 128 6 3504 6 3 104 1 5 2920 3 5 128 1 1 4 4100 3 5 128 4 1 7 560 3 5 128 2.048 1 3 14 0 7 2 128 3.072 1 4 7 0 7 2 128 4.096 1 3 7 0 7 2 128 6.144 1 2 7 0 7 2 128 8.192 fS = 44.1 kHz fS = 48 kHz 1 4 3 0 4 4 128 12 1 1 7 1680 7 2 128 16 1 1 5 3760 7 2 128 19.2 1 1 4 4800 7 2 128 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 51 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-28. PLL Example Configurations (continued) PLL_CLKIN (MHz) PLLP PLLR PLLJ PLLD MDAC NDAC DOSR 4 1 7 1680 7 2 128 fS = 44.1 kHz 48 5.6.2 Timer The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce logics and interrupts. The MCLK divider must be set such a way that the divider output is ~1 MHz for the timers to be closer to the programmed value. Powered on if internal oscillator is selected Internal Oscillator ÷8 0 Interval timers MCLK Programmable Divider Used for de-bounce time for headset detection logic, various power up timers and for generation of interrupts 1 P3/R16, Bits D6-D0 P3/R16, Bit D7 Figure 5-23. Interval Timer Clock Selection 5.7 5.7.1 Digital Audio and Control Interface Digital Audio Interface Audio data is transferred between the host processor and the TLV320DAC3100 via the digital audio data serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified data options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus-clock line, and the ability to communicate directly with multiple devices within a system. The audio bus of the TLV320DAC3100 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the DAC sampling frequency. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 / register 30 (see Figure 5-20). The number of bit-clock pulses in a frame may need adjustment to accommodate various word lengths, as well as to support the case when multiple TLV320DAC3101s may share the same audio bus. 52 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 The TLV320DAC3101 also includes a feature to offset the position of start-of-data-transfer with respect to the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page 0 / register 28. The TLV320DAC3101 also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3. By default, when the word clocks and bit clocks are generated by the TLV320DAC3101, these clocks are active only when the DAC is powered up within the device. This is done to save power. However, it also supports a feature whereby both the word clocks and bit clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word clocks or bit clocks are used in the system as general-purpose clocks. 5.7.1.1 Right-Justified Mode The audio interface of the TLV320DAC3101 can be put into the right-justified mode by programming page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. 1/fS WCLK BCLK Right Channel Left Channel DIN 0 n–1 n–2 n–3 MSB 2 1 0 n–1 n–2 n–3 2 1 0 LSB T0149-05 Figure 5-24. Timing Diagram for Right-Justified Mode For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. 5.7.1.2 Left-Justified Mode The audio interface of the TLV320DAC3100 can be put into left-justified mode by programming page 0 / register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 53 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 3 LD(n) 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 5-25. Timing Diagram for Left-Justified Mode WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 0 N N N - - 1 2 3 LD(n) 3 2 1 0 RD(n) LD(n) = n'th sample of left channel data N N N - - 1 2 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-26. Timing Diagram for Left-Justified Mode With Offset = 1 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 0 RD(n) LD(n) = n'th sample of left channel data N N N - - 1 2 3 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-27. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock For the left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data. 5.7.1.3 I2S Mode The audio interface of the TLV320DAC3100 can be put into I2S mode by programming page 0 / register 27, bits D7–D6 = 00. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. 54 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-28. Timing Diagram for I2S Mode WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N 1 DATA 5 4 3 2 1 N 1 0 5 4 LD(n) 3 2 1 N 1 0 RD(n) LD(n) = n'th sample of left channel data 5 LD (n+1) RD(n) = n'th sample of right channel data 2 Figure 5-29. Timing Diagram for I S Mode With Offset = 2 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data 2 Figure 5-30. Timing Diagram for I S Mode With Offset = 0 and Bit Clock Inverted For I2S mode, the number of bit clocks per channel should be greater than or equal to the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data. 5.7.1.4 DSP Mode The audio interface of the TLV320DAC3100 can be put into DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 55 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 0 N N N - - 1 2 3 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD (n+1) RD(n) = n'th sample of right channel data Figure 5-31. Timing Diagram for DSP Mode WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 3 2 1 0 N N N - - 1 2 3 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 5-32. Timing Diagram for DSP Mode With Offset = 1 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK N N N - - 1 2 3 DATA 2 3 1 0 N N N - - 1 2 3 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) 3 LD(n+1) Figure 5-33. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the programmed word length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least the programmed word length of the data. 5.7.2 Primary and Secondary Digital Audio Interface Selection The audio serial interface on the TLV320DAC3100 has extensive I/O control to allow communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections. Table 5-29 shows the primary and secondary audio interface selection and registers. Figure 5-34 is a high-level diagram showing the general signal flow and multiplexing for the primary and secondary audio interfaces. Table 5-29. Primary and Secondary Audio Interface Selection Desired Pin Function Primary WCLK (OUT) 56 Possible Pins WCLK Page 0 Registers Comment R27/D2 = 1 Primary WCLK is output from codec R33/D5–D4 Select source of primary WCLK (DAC_fs or secondary WCLK) APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-29. Primary and Secondary Audio Interface Selection (continued) Desired Pin Function Primary WCLK (IN) Possible Pins WCLK Primary BCLK (OUT) BCLK Primary BCLK (IN) BCLK Primary DIN (IN) Secondary WCLK (OUT) DIN GPIO1 Secondary WCLK (IN) GPIO1 Secondary BCLK (OUT) GPIO1 Secondary BCLK (IN) Secondary DIN (IN) GPIO1 GPIO1 Page 0 Registers Comment R27/D2 = 0 Primary WCLK is input to codec R27/D3 = 1 Primary BCLK is output from codec R33/D7 Select source of primary WCLK (internal BCLK or secondary BCLK) R27/D3 = 0 Primary BCLK is input to codec R32/D0 Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN) R31/D4–D2 = 000 Secondary WCLK obtained from GPIO1 pin R51/D5–D2 = 1001 GPIO1 = secondary WCLK output R33/D3–D2 Select source of secondary WCLK (DAC_fs, or primary WCLK) R31/D4–D2 = 000 Secondary WCLK obtained from GPIO1 pin R51/D5–D2 = 0001 GPIO1 enabled as secondary input R31/D7–D5 = 000 Secondary BCLK obtained from GPIO1 pin R51/D5–D2 = 1000 GPIO1 = secondary BCLK output R33/D6 Select source of secondary BCLK (primary BCLK or internal BCLK) R31/D7–D5 = 000 Secondary BCLK obtained from GPIO1 pin R51/D5–D2 = 0001 GPIO1 enabled as secondary input R31/D1–D0 = 00 Secondary DIN obtained from GPIO1 pin R51/D5–D2 = 0001 GPIO1 enabled as secondary input APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 57 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com S_BCLK BCLK BCLK BCLK BCLK_OUT BCLK_INT S_BCLK WCLK S_WCLK WCLK WCLK DAC_fS Primary Audio Processor DAC_WCLK_INT S_WCLK Audio Digital Serial Interface DIN DOUT DIN DIN_INT S_DIN DIN BCLK2 GPIO1 S_BCLK BCLK BCLK BCLK_OUT WCLK2 GPIO1 S_WCLK WCLK WCLK BCLK_OUT DAC_fS Secondary Audio Processor GPIO1 DAC_fS Clock Generation S_DIN DOUT DIN B0375-01 Figure 5-34. Audio Serial Interface Multiplexing 5.7.3 Control Interface The TLV320DAC3100 control interface supports the I2C communication protocol. 5.7.3.1 I2C Control Mode The TLV320DAC3100 supports the I2C control protocol and responds to the I2C address of 0011 000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. 58 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320DAC3100 can only act as a slave device. An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is 0, whereas a HIGH indicates the bit is 1). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line clocks the SDA bit into the receiver shift register. The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start communication on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH. After the master issues a START condition, it sends a byte that selects the slave device for communication. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it is to read from or write to the slave device. Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (Remember that the master always drives the clock line.) A not-acknowledge is performed simply by leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line LOW. When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition. The TLV320DAC3100 can also respond to and acknowledge a general call, which consists of the master issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be enabled via page 0 / register 34, bit D5. SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) RA(0) 8-bit Register Address (M) D(7) Slave Ack (S) D(0) 8-bit Register Data (M) Slave Ack (S) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-35. I2C Write APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 59 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) DA(6) RA(0) 8-bit Register Address (M) Slave Ack (S) Repeat Start (M) DA(0) 7-bit Device Address (M) D(7) Read (M) Slave Ack (S) 8-bit Register Data (S) D(0) Master No Ack (M) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-36. I2C Read In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register. Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for the next eight clocks the data of the next incremental register. 60 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 6 REGISTER MAP 6.1 TLV320DAC3100 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are available for reading only. The TLV320DAC3100 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device. The pages defined for the TLV320DAC3100 are 0, 1, 3, 8–9, 12–13 (DAC coefficient pages). Page 0 is the default home page after RESET. Page control is done by writing a new page value into register 0 of the current page. The control registers for the TLV320DAC3100 are described in detail as follows. All registers are 8 bits in width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit. Pages 0, 1, 3, 8–9, and 12–13 are available for use; however, all other pages and registers are reserved. Do not read from or write to reserved pages and registers. Also, do not write other than the reset values for the reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure can occur. Note that the page and register numbers are shown in decimal format. For use in microcode, these decimal values may require conversion to hexadecimal format. For convienience, the register numbers are shown in both formats, whereas the page numbers are shown only in decimal format. Table 6-1. Summary of Register Map Page Number 6.2 Description 0 Page 0 is the default page on power up. Configuration for serial interface, digital I/O, etc. 1 Configuration for DAC, output drivers, volume controls, etc. 3 Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection-block clock. 8–9 DAC filter and DRC coefficients (buffer A) 12–13 DAC filter and DRC coefficients (buffer B) Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs Page 0 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected Page 0 / Register 1 (0x01): Software Reset BIT D7–D1 D0 READ/ WRITE R/W R/W RESET VALUE 0000 000 0 READ/ WRITE R RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only zeros to these bits. 0: Don't care 1: Self-clearing software reset for control register Page 0 / Register 2 (0x02): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not write to this register. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 61 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 3 (0x03): OT FLAG D7–D2 D1 READ/ WRITE R R RESET VALUE XXXX XX 1 D0 R X BIT DESCRIPTION Reserved. Do not write to these bits. 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation Reserved. Do not write to this bit. Page 0 / Register 4 (0x04): Clock-Gen Muxing (1) D7–D4 D3–D2 READ/ WRITE R/W R/W RESET VALUE 0000 00 D1–D0 R/W 00 BIT (1) DESCRIPTION Reserved. Write only zeros to these bits. 00: PLL_CLKIN = MCLK (device pin) 01: PLL_CLKIN = BCLK (device pin) 10: PLL_CLKIN = GPIO1 (device pin) 11: PLL_CLKIN = DIN (can be used for a system where DAC is not used) 00: CODEC_CLKIN = MCLK (device pin) 01: CODEC_CLKIN = BCLK (device pin) 10: CODEC_CLKIN = GPIO1 (device pin) 11: CODEC_CLKIN = PLL_CLK (generated on-chip) See Section 5.6 for more details on clock-generation mutiplexing and dividers. Page 0 / Register 5 (0x05): PLL P and R Values D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 001 D3–D0 R/W 0001 READ/ WRITE R/W R/W RESET VALUE 00 00 0100 BIT DESCRIPTION 0: PLL is powered down. 1: PLL is powered up. 000: PLL divider P = 8 001: PLL divider P = 1 010: PLL divider P = 2 ... 110: PLL divider P = 6 111: PLL divider P = 7 0000: PLL multiplier R = 16 0001: PLL multiplier R = 1 0010: PLL multiplier R = 2 ... 1110: PLL multiplier R = 14 1111: PLL multiplier R = 15 Page 0 / Register 6 (0x06): PLL J Value BIT D7–D6 D5–D0 DESCRIPTION Reserved. Write only zeros to these bits. 00 0000: Do not use (reserved) 00 0001: PLL multiplier J = 1 00 0010: PLL multiplier J = 2 ... 11 1110: PLL multiplier J = 62 11 1111: PLL multiplier J = 63 Page 0 / Register 7 (0x07): PLL D-Value MSB (1) BIT D7–D6 D5–D0 (1) 62 READ/ WRITE R/W R/W RESET VALUE 00 00 0000 DESCRIPTION Reserved. Write only zeros to these bits. PLL fractional multiplier D-value MSBs D[13:8] Note that this register is updated only when page 0 / register 8 is written immediately after page 0 / register 7. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 8 (0x08): PLL D-Value LSB (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION PLL fractional multiplier D-value LSBs D[7:0] Note that page 0 / register 8 must be written immediately after page 0 / register 7. Page 0 / Register 9 (0x09) and Page 0 / Register 10 (0x0B): Reserved READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 11 (0x0B): DAC NDAC_VAL BIT DESCRIPTION 0: DAC NDAC divider is powered down. 1: DAC NDAC divider is powered up. 000 0000: DAC NDAC divider = 128 000 0001: DAC NDAC divider = 1 000 0010: DAC NDAC divider = 2 ... 111 1110: DAC NDAC divider = 126 111 1111: DAC NDAC divider = 127 Page 0 / Register 12 (0x0C): DAC MDAC_VAL BIT DESCRIPTION 0: DAC MDAC divider is powered down. 1: DAC MDAC divider is powered up. 000 0000: DAC MDAC divider = 128 000 0001: DAC MDAC divider = 1 000 0010: DAC MDAC divider = 2 ... 111 1110: DAC MDAC divider = 126 111 1111: DAC MDAC divider = 127 Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB BIT D7–D2 D1–D0 READ/ WRITE R/W R/W RESET VALUE 0000 00 00 DESCRIPTION Reserved DAC OSR Value DOSR(9:8) Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB (1) BIT D7–D0 (1) (2) READ/ WRITE R/W RESET VALUE 1000 0000 (2) DESCRIPTION DAC OSR Value DOSR(7:0) 0000 0000: DAC OSR(7:0) = 1024 (MSB page 0 / register 13, bits D1–D0 = 00) 0000 0001: Reserved. 0000 0010: DAC OSR(7:0) = 2 (MSB page 0 / register 13, bits D1–D0 = 00) ... 1111 1110: DAC OSR(7:0) = 1022 (MSB page 0 / register 13, bits D1–D0 = 11) 1111 1111: DAC OSR(7:0) = Reserved. Do not use. DOSR must be a multiple of 2 when using filter type A, a multiple of 4 when using filter type B, and a multiple of 8 when using filter type C. Note that page 0 / register 14 must be written to immediately after writing to page 0 / register 13. Page 0 / Register 15 (0x0F) Through Page 0 / Register 24 (0x18): Reserved BIT D7–D0 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Do not write to these registers. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 63 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 25 (0x19): CLKOUT MUX BIT D7–D3 D2–D0 READ/ WRITE R/W R/W RESET VALUE 0000 0 000 DESCRIPTION Reserved 000: CDIV_CLKIN = MCLK (device pin) 001: CDIV_CLKIN = BCLK (device pin) 010: CDIV_CLKIN = DIN (can be used for systems where the DAC is not required) 011: CDIV_CLKIN = PLL_CLK (generated on-chip) 100: CDIV_CLKIN = DAC_CLK (generated on-chip) 101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 110: Reserved 111: Reserved Page 0 / Register 26 (0x1A): CLKOUT M_VAL D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D4 R/W 00 D3 R/W 0 D2 R/W 0 D1–D0 R/W 00 READ/ WRITE R/W RESET VALUE 0000 0000 BIT DESCRIPTION 0: CLKOUT M divider is powered down. 1: CLKOUT M divider is powered up. 000 0000: CLKOUT divider M = 128 000 0001: CLKOUT divider M = 1 000 0010: CLKOUT divider M = 2 ... 111 1110: CLKOUT divider M = 126 111 1111: CLKOUT divider M = 127 Page 0 / Register 27 (0x1B): Codec Interface Control 1 BIT DESCRIPTION 2 00: Codec interface = I S 01: Codec Interface = DSP 10: Codec interface = RJF 11: Codec interface = LJF 00: Codec interface word length = 16 01: Codec interface word length = 20 10: Codec interface word length = 24 11: Codec interface word length = 32 0: BCLK is input. 1: BCLK is output. 0: WCLK is input. 1: WCLK is output. Reserved bits bits bits bits Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability BIT D7–D0 64 DESCRIPTION Offset (Measured With Respect to WCLK Rising Edge in DSP Mode) 0000 0000: Offset = 0 BCLKs 0000 0001: Offset = 1 BCLK 0000 0010: Offset = 2 BCLKs ... 1111 1110: Offset = 254 BCLKs 1111 1111: Offset = 255 BCLKs REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 29 (0x1D): Codec Interface Control 2 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 0 D2 R/W 0 D1–D0 R/W 00 BIT DESCRIPTION Reserved 0: BCLK is not inverted (valid for both primary and secondary BCLK). 1: BCLK is inverted (valid for both primary and secondary BCLK). BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary BCLK) 0: Disabled 1: Enabled 00: BDIV_CLKIN = DAC_CLK (generated on-chip) 01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 10: Reserved 11: Reserved Page 0 / Register 30 (0x1E): BCLK N_VAL D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D2 R/W 000 D1–D0 R/W 00 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 0 D2 R/W 0 D1 D0 R/W R/W 0 0 BIT DESCRIPTION 0: BCLK N-divider is powered down. 1: BCLK N-divider is powered up. 000 0000: BCLK divider N = 128 000 0001: BCLK divider N = 1 000 0010: BCLK divider N = 2 ... 111 1110: BCLK divider N = 126 111 1111: BCLK divider N = 127 Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1 BIT DESCRIPTION 000: Secondary BCLK is obtained from the GPIO1 pin. 001: Secondary BCLK is not obtained from the GPIO1 pin. 010–111: Reserved 000: Secondary WCLK is obtained from the GPIO1 pin. 001: Secondary WCLK is not obtained from the GPIO1 pin. 010–111: Reserved 00: Secondary DIN is obtained from the GPIO1 pin. 01: Secondary DIN is not obtained from the GPIO1 pin. 10–11: Reserved Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2 BIT DESCRIPTION Reserved 0: Primary BCLK is fed to codec serial-interface and ClockGen blocks. 1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks. 0: Primary WCLK is fed to codec serial-interface block. 1: Secondary WCLK is fed to codec serial-interface block. Reserved 0: Primary DIN is fed to codec serial-interface block. 1: Secondary DIN is fed to codec serial-interface block. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 65 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3–D2 R/W 00 D1–D0 R/W 00 BIT DESCRIPTION 0: Primary BCLK output = internally generated BCLK clock 1: Primary BCLK output = secondary BCLK 0: Secondary BCLK output = primary BCLK 1: Secondary BCLK output = internally generated BCLK clock 00: Primary WCLK output = internally generated DAC_fS 01: Reserved 10: Primary WCLK output = secondary WCLK 11: Reserved 00: Secondary WCLK output = primary WCLK 01: Secondary WCLK output = internally generated DAC_fS clock 10: Reserved 11: Reserved Reserved Page 0 / Register 34 (0x22): I2C Bus Condition D7–D6 D5 READ/ WRITE R/W R/W RESET VALUE 00 0 D4–D0 R/W 0 0000 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R RESET VALUE 0 D6 D5 R R X 0 D4 R 0 D3 R 0 D2 D1 R R X 0 D0 R 0 BIT DESCRIPTION Reserved. Write only the reset value to these bits. 0: I2C general-call address is ignored. 1: Device accepts I2C general-call address. Reserved. Write only zeros to these bits. Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 37 (0x25): DAC Flag Register BIT DESCRIPTION 0: Left-channel DAC powered down 1: Left-channel DAC powered up Reserved 0: HPL driver powered down 1: HPL driver powered up 0: Left-channel class-D driver powered down 1: Left-channel class-D driver powered up 0: Right-channel DAC powered down 1: Right-channel DAC powered up Reserved 0: HPR driver powered down 1: HPR driver powered up 0: Right-channel class-D driver powered down 1: Right-channel class-D driver powered up Page 0 / Register 38 (0x26): DAC Flag Register D7–D5 D4 READ/ WRITE R R RESET VALUE XXX 0 D3–D1 D0 R R XXX 0 BIT 66 DESCRIPTION Reserved 0: Left-channel DAC PGA applied gain ≠ programmed gain 1: Left-channel DAC PGA applied gain = programmed gain Reserved 0: Right-channel DAC PGA applied gain ≠ programmed gain 1: Right-channel DAC PGA applied gain = programmed gain REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 39 (0x27): Overflow Flags D7 (1) READ/ WRITE R RESET VALUE 0 D6 (1) R 0 D5 (1) R 0 D4–D0 R 0 0000 BIT (1) DESCRIPTION Left-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. Right-Channel DAC Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. DAC Barrel Shifter Output Overflow Flag 0: Overflow has not occurred. 1: Overflow has occurred. Reserved Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs again. Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved READ/ WRITE R RESET VALUE XXXX XXXX READ/ WRITE R RESET VALUE 0 D6 (1) R 0 D5 (1) R X D4 (1) R X D3 (1) R 0 D2 (1) R 0 D1–D0 R 00 BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits) BIT D7 (1) (1) DESCRIPTION 0: No short circuit is detected at HPL/left class-D driver. 1: Short circuit is detected at HPL/left class-D driver. 0: No short circuit is detected at HPR/right class-D driver. 1: Short circuit is detected at HPR/right class-D driver. 0: No headset button pressed 1: Headset button pressed 0: No headset insertion/removal is detected. 1: Headset insertion/removal is detected. 0: Left DAC signal power is ≤ the signal threshold of DRC. 1: Left DAC signal power is > the signal threshold of DRC. 0: Right DAC signal power is ≤ the signal threshold of DRC. 1: Right DAC signal power is > the signal threshold of DRC. Reserved Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs again. Page 0 / Register 45 (0x2D): Reserved BIT D7–D0 READ/ WRITE R RESET VALUE 0000 0000 DESCRIPTION Reserved. Do not use. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 67 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 46 (0x2E): DAC Interrupt Flags D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 R X D4 R X D3 R 0 D2 R 0 D1–D0 R 00 READ/ WRITE R/W RESET VALUE 0000 0000 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 D3 R/W R/W 0 0 D2 R/W 0 D1 D0 R/W R/W 0 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 D3 R/W R/W 0 0 D2 R/W 0 D1 D0 R/W R/W 0 0 BIT DESCRIPTION 0: No short circuit detected at HPL/left class-D driver 1: Short circuit detected at HPL/left class-D driver 0: No short circuit detected at HPR/right class-D driver 1: Short circuit detected at HPR/right class-D driver 0: No headset button pressed 1: Headset button pressed 0: Headset removal detected 1: Headset insertion detected 0: Left DAC signal power is ≤ the signal threshold of the DRC. 1: Left DAC signal power is > the signal threshold of the DRC. 0: Right DAC signal power is ≤ the signal threshold of the DRC. 1: Right DAC signal power is > the signal threshold of the DRC. Reserved Page 0 / Register 47 (0x2F): Reserved BIT D7–D0 DESCRIPTION Reserved. Write only the reset value to these bits. Page 0 / Register 48 (0x30): INT1 Control Register BIT DESCRIPTION 0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt. 0: Button-press detect interrupt is not used in the generation of INT1 interrupt. 1: Button-press detect interrupt is used in the generation of INT1 interrupt. 0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt. 1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt. Reserved 0: Short-circuit interrupt is not used in the generation of INT1 interrupt. 1: Short-circuit interrupt is used in the generation of INT1 interrupt. 0: DAC data overflow does not result in an INT1 interrupt. 1: DAC data overflow results in an INT1 interrupt. Reserved 0: INT1 is only one pulse (active-high) of typical 2-ms duration. 1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 / register 44 is read by the user. Page 0 / Register 49 (0x31): INT2 Control Register BIT 68 DESCRIPTION 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt. 0: Button-press detect interrupt is not used in the generation of INT2 interrupt. 1: Button-press detect interrupt is used in the generation of INT2 interrupt. 0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt. 1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt. Reserved 0: Short-circuit interrupt is not used in the generation of INT2 interrupt. 1: Short-circuit interrupt is used in the generation of INT2 interrupt. 0: DAC data overflow does not result in an INT2 interrupt. 1: DAC data overflow results in an INT2 interrupt. Reserved 0: INT2 is only one pulse (active-high) of typical 2-ms duration. 1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 / register 44 is read by the user. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 50 (0x32): Reserved READ/ WRITE R RESET VALUE 0000 0000 D7–D6 D5–D2 READ/ WRITE R/W R/W RESET VALUE XX 0000 D1 D0 R R/W X 0 READ/ WRITE R RESET VALUE XXXX XXXX READ/ WRITE R RESET VALUE 0000 0000 D7–D3 D2–D1 READ/ WRITE R/W R/W RESET VALUE 0000 0 01 D0 R X READ/ WRITE R RESET VALUE XXXX XXXX BIT D7-D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 51 (0x33): GPIO1 In/Out Pin Control BIT DESCRIPTION Reserved. Do not write any value other than reset value. 0000: GPIO1 disabled (input and output buffers powered down) 0001: GPIO1 is in input mode (can be used as secondary BCLK input, secondary WCLK input, secondary DIN input, or in ClockGen block). 0010: GPIO1 is used as general-purpose input (GPI). 0011: GPIO1 output = general-purpose output 0100: GPIO1 output = CLKOUT output 0101: GPIO1 output = INT1 output 0110: GPIO1 output = INT2 output 0111: Reserved 1000: GPIO1 output = secondary BCLK output for codec interface 1001: GPIO1 output = secondary WCLK output for codec interface 1010–1111: Reserved GPIO1 input buffer value 0: GPIO1 general-purpose output value = 0 1: GPIO1 general-purpose output value = 1 Page 0 / Register 52 (0x34): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 53 (0x35): Reserved BIT D7–D0 DESCRIPTION Reserved Page 0 / Register 54 (0x36): DIN (IN Pin) Control BIT DESCRIPTION Reserved 00: DIN disabled (input buffer powered down) 01: DIN enabled (can be used as DIN for codec interface, Dig_Mic_In or in ClockGen block) 10: DIN is used as general-purpose input (GPI) 11: Reserved DIN input-buffer value Page 0 / Register 55 (0x37) Through Page 0 / Register 59 (0x3B): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not write to these bits. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 69 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 60 (0x3C): DAC Processing Block Selection READ/ WRITE R/W R/W RESET VALUE 000 0 0001 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 01 D3–D2 R/W 01 D1–D0 R/W 00 D7–D4 D3 READ/ WRITE R/W R/W RESET VALUE 0000 1 D2 R/W 1 D1–D0 ( R/W 00 BIT D7–D5 D4–D0 DESCRIPTION Reserved. Write only default value. 0 0000: Reserved. Do not use. 0 0001: DAC signal processing block PRB_P1 0 0010: DAC signal processing block PRB_P2 0 0011: DAC signal processing block PRB_P3 0 0100: DAC signal processing block PRB_P4 ... 1 1000: DAC signal processing block PRB_P24 1 1001: DAC signal processing block PRB_P25 1 1010–1 1111: Reserved. Do not use. Page 0 / Register 61 (0x3D) Through Page 0 / Register 62: Reserved BIT D7–D0 DESCRIPTION Reserved. Do not write. Page 0 / Register 63 (0x3F): DAC Data-Path Setup BIT DESCRIPTION 0: Left-channel DAC is powered down. 1: Left-channel DAC is powered up. 0: Right-channel DAC is powered down. 1: Right-channel DAC is powered up. 00: Left-channel DAC data path = off 01: Left-channel DAC data path = left data 10: Left-channel DAC data path = right data 11: Left-channel DAC data path = left-channel and right-channel data [(L + R)/2] 00: Right-channel DAC data path = off 01: Right-channel DAC data path = right data 10: Right-channel DAC data path = left data 11: Right-channel DAC data path = left-channel and right-channel data [(L + R)/2] 00: DAC channel volume control soft-stepping is enabled for one step per sample period. 01: DAC channel volume control soft-stepping is enabled for one step per two sample periods. 10: DAC channel volume control soft-stepping is disabled. 11: Reserved. Do not write this sequence to these bits. Page 0 / Register 64 (0x40): DAC VOLUME CONTROL BIT 1) (1) 70 DESCRIPTION Reserved. Write only zeros to these bits. 0: Left-channel DAC not muted 1: Left-channel DAC muted 0: Right-channel DAC not muted 1: Right-channel DAC muted 00: Left and right channels have independent volume control. 01: Left-channel volume control is the programmed value of right-channel volume control. 10: Right-channel volume control is the programmed value of left-channel volume control. 11: Same as 00 When DRC is enabled, left and right channel volume controls are always independent. Program bits D1–D0 to 00. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 65 (0x41): DAC Left Volume Control READ/ WRITE R/W RESET VALUE 0000 0000 READ/ WRITE R/W RESET VALUE 0000 0000 D7 READ/ WRITE R/W RESET VALUE 0 D6–D5 R XX D4–D2 R/W 000 D1–D0 R/W 00 BIT D7–D0 DESCRIPTION Left DAC Channel Digital Volume Control Setting 0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: Digital volume control = –63 dB 1000 0001: Digital volume control = –63.5 dB 1000 0000: Reserved Page 0 / Register 66 (0x42): DAC Right Volume Control BIT D7–D0 DESCRIPTION Right DAC Channel Digital Volume Control Setting 0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: Digital volume control = –63 dB 1000 0001: Digital volume control = –63.5 dB 1000 0000: Reserved Page 0 / Register 67 (0x43): Headset Detection BIT (1) DESCRIPTION 0: Headset detection disabled 1: Headset detection enabled 00: No headset detected 01: Headset without microphone is detected 10: Reserved 11: Headset with microphone is detected Debounce Programming for Glitch Rejection During Headset Detection (1) 000: 16 ms (sampled with 2-ms clock) 001: 32 ms (sampled with 4-ms clock) 010: 64 ms (sampled with 8-ms clock) 011: 128 ms (sampled with 16-ms clock) 100: 256 ms (sampled with 32-ms clock) 101: 512 ms (sampled with 64-ms clock) 110: Reserved 111: Reserved Debounce Programming for Glitch Rejection During Headset Button-Press Detection 00: 0 ms 01: 8 ms (sampled with 1-ms clock) 10: 16 ms (sampled with 2-ms clock) 11: 32 ms (sampled with 4-ms clock) Note that these times are generated using the 1-MHz reference clock which is defined in page 3 / register 16. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 71 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 68 (0x44): DRC Control 1 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5 R/W 0 D4–D2 R/W 011 D1–D0 R/W 11 D7 D6–D3 READ/ WRITE R R/W RESET VALUE 0 0111 D2–D0 R 000 READ/ WRITE R/W RESET VALUE 0000 BIT DESCRIPTION Reserved. Write only the reset value to these bits. 0: DRC disabled for left channel 1: DRC enabled for left channel 0: DRC disabled for right channel 1: DRC enabled for right channel 000: DRC threshold = –3 dB 001: DRC threshold = –6 dB 010: DRC threshold = –9 dB 011: DRC threshold = –12 dB 100: DRC threshold = –15 dB 101: DRC threshold = –18 dB 110: DRC threshold = –21 dB 111: DRC threshold = –24 dB 00: DRC hysteresis = 0 dB 01: DRC hysteresis = 1 dB 10: DRC hysteresis = 2 dB 11: DRC hysteresis = 3 dB Page 0 / Register 69 (0x45): DRC Control 2 BIT DESCRIPTION Reserved. Write only the reset value to these bits. DRC Hold Programmability 0000: DRC hold disabled 0001:DRC hold time = 32 DAC word clocks 0010: DRC hold time = 64 DAC word clocks 0011: DRC hold time = 128 DAC word clocks 0100: DRC hold time = 256 DAC word clocks 0101: DRC hold time = 512 DAC word clocks ... 1110: DRC hold time = 4 × 32,768 DAC word clocks 1111: DRC hold time = 5 × 32,768 DAC word clocks Reserved. Write only the reset value to these bits. Page 0 / Register 70 (0x46): DRC Control 3 BIT D7–D4 D3–D0 72 R/W 0000 DESCRIPTION 0000: 0001: 0010: ... 1110: 1111: 0000: 0001: 0010: ... 1110: 1111: DRC attack rate = 4 dB per DAC word clock DRC attack rate = 2 dB per DAC word clock DRC attack rate = 1 dB per DAC word clock DRC DRC DRC DRC DRC attack rate = 2.4414e–5 attack rate = 1.2207e–5 decay rate = 1.5625e–2 decay rate = 7.8125e–3 decay rate = 3.9062e–3 dB per dB per dB per dB per dB per DAC DAC DAC DAC DAC word word word word word clock clock clock clock clock DRC decay rate = 9.5367e–7 dB per DAC word clock DRC decay rate = 4.7683e–7 dB per DAC word clock REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 71 (0x47): Left Beep Generator D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D0 R/W R/W 0 00 0000 BIT (1) (1) DESCRIPTION 0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration). Reserved. Write only reset value. 00 0000: Left-channel beep volume control = 2 dB 00 0001: Left-channel beep volume control = 1 dB 00 0010: Left-channel beep volume control = 0 dB 00 0011: Left-channel beep volume control = –1 dB ... 11 1110: Left-channel beep volume control = –60 dB 11 1111: Left-channel beep volume control = –61 dB The beep generator is only available in PRB_P25 DAC processing mode. Page 0 / Register 72 (0x48): Right Beep Generator (1) D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D0 R/W 00 0000 BIT (1) DESCRIPTION 00: Left and right channels have independent beep volume control. 01: Left-channel beep volume control is the programmed value of right-channel beep volume control. 10: Right-channel beep volume control is the programmed value of left-channel beep volume control. 11: Same as 00 00 0000: Right-channel beep volume control = 2 dB 00 0001: Right-channel beep volume control = 1 dB 00 0010: Right-channel beep volume control = 0 dB 00 0011: Right-channel beep volume control = –1 dB ... 11 1110: Right-channel beep volume control = –60 dB 11 1111: Right-channel beep volume control = –61 dB The beep generator is only available in PRB_P25 DAC processing mode. Page 0 / Register 73 (0x49): Beep Length MSB BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 8 MSBs out of 24 bits for the number of samples for which the beep must be generated. Page 0 / Register 74 (0x4A): Beep Length Middle Bits BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 READ/ WRITE R/W RESET VALUE 1110 1110 READ/ WRITE R/W RESET VALUE 0001 0000 DESCRIPTION 8 middle bits out of 24 bits for the number of samples for which the beep must be generated. Page 0 / Register 75 (0x4B): Beep Length LSB BIT D7–D0 DESCRIPTION 8 LSBs out of 24 bits for the number of samples for which beep need to be generated. Page 0 / Register 76 (0x4C): Beep Sin(x) MSB BIT D7–D0 DESCRIPTION 8 MSBs out of 16 bits for sin(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate. Page 0 / Register 77 (0x4D): Beep Sin(x) LSB BIT D7–D0 READ/ WRITE R/W RESET VALUE 1101 1000 READ/ WRITE R/W RESET VALUE 0111 1110 DESCRIPTION 8 LSBs out of 16 bits for sin(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate. Page 0 / Register 78 (0x4E): Beep Cos(x) MSB BIT D7–D0 DESCRIPTION 8 MSBs out of 16 bits for cos(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 73 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 79 (0x4F): Beep Cos(x) LSB READ/ WRITE R/W RESET VALUE 1110 0011 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3 D2–D0 R/W R/W 0 000 READ/ WRITE R R RESET VALUE 0 XXX XXXX BIT D7–D0 DESCRIPTION 8 LSBs out of 16 bits for cos(2π × fin/fS), where fin is the beep frequency and fS is the DAC sample rate. Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC – Volume Control BIT DESCRIPTION 0: DAC volume control is controlled by control register (7-bit Vol ADC is powered down). 1: DAC volume control is controlled by pin. 0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control. 1: MCLK is used for the 7-bit Vol ADC for pin volume control. 00: No hysteresis for volume control ADC output 01: Hysteresis of ±1 bit 10: Hysteresis of ±2 bits 11: Reserved. Do not write this sequence to these bits. Reserved. Write only reset value. Throughput of the 7-bit Vol ADC for pin volume control, frequency based on MCLK or internal oscillator. MCLK = 12 MHz Internal Oscillator Source 000: Throughput = 15.625 Hz 10.68 Hz 001: Throughput = 31.25 Hz 21.35 Hz 010: Throughput = 62.5 Hz 42.71 Hz 011: Throughput = 125 Hz 8.2 Hz 100: Throughput = 250 Hz 170 Hz 101: Throughput = 500 Hz 340 Hz 110: Throughput = 1 kHz 680 Hz 111: Throughput = 2 kHz 1.37 kHz Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale according to the actual oscillator frequency. Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain BIT D7 D6–D0 DESCRIPTION Reserved. Write only zero to this bit. 000 0000: Gain applied by pin volume control 000 0001: Gain applied by pin volume control 000 0010: Gain applied by pin volume control ... 010 0011: Gain applied by pin volume control 010 0100: Gain applied by pin volume control 010 0101: Gain applied by pin volume control ... 101 1001: Gain applied by pin volume control 101 1010: Gain applied by pin volume control 101 1011: Gain applied by pin volume control ... 111 1101: Gain applied by pin volume control 111 1110: Gain applied by pin volume control 111 1111: Reserved = 18 dB = 17.5 dB = 17 dB = 0.5 dB = 0 dB = –0.5 dB = –26.5 dB = –27 dB = –28 dB = –62 dB = –63 dB Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved BIT D7–D0 74 READ/ WRITE R RESET VALUE XXXX XXXX DESCRIPTION Reserved. Do not use. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 6.3 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 1: DAC, Power-Controls and MISC Logic-Related Programmabilities Page 1 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected Page 1 / Register 1 (0x01) Through Page 1 / Register 29 (0x1D): Reserved READ/ WRITE R RESET VALUE XXXX XXXX D7–D2 D1 READ/ WRITE R/W R/W RESET VALUE 0000 00 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 D4–D3 R/W R/W 0 0 D2 D1 R/W R/W 1 0 D0 R 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D1 D0 R/W R 000 011 0 BIT D7–D0 DESCRIPTION Reserved. Do not use. Page 1 / Register 30 (0x1E): Headphone and Speaker Amplifier Error Control BIT DESCRIPTION Reserved 0: Reset HPL and HPR power-up control bits on short-circuit detection if page 1 / register 31, D1 = 1. 1: HPL and HPR power-up control bits remain unchanged on short-circuit detection. 0: Reset SPK power-up control bits on short-circuit detection. 1: SPK power-up control bits remain unchanged on short-circuit detection. Page 1 / Register 31 (0x1F): Headphone Drivers BIT DESCRIPTION 0: HPL output driver is powered down. 1: HPL output driver is powered up. 0: HPR output driver is powered down. 1: HPR output driver is powered up. Reserved. Write only zero to this bit. 00: Output common-mode voltage = 1.35 V 01: Output common-mode voltage = 1.5 V 10: Output common-mode voltage = 1.65 V 11: Output common-mode voltage = 1.8 V Reserved. Write only 1 to this bit. 0: If short-circuit protection is enabled for headphone driver and short circuit is detected, device limits the the maximum current to the load. 1: If short-circuit protection is enabled for headphone driver and short circuit is detected, device powers down the output driver. 0: Short circuit is not detected on the headphone driver. 1: Short circuit is detected on the headphone driver. Page 1 / Register 32 (0x20): Class-D Speaker Amplifier BIT DESCRIPTION 0: Class-D output driver is powered down. 1: Class-D output driver is powered up. Reserved. Write only the reset value to these bits. 0: Short circuit is not detected on the class-D driver. Valid only if class-D amplifier is powered up. For short-circuit flag sticky bit, see page 0 / register 44. 1: Short circuit is detected on the class-D driver. Valid only if class-D amplifier is powered up. For shortcircuit flag sticky bit, see page 0 / register 44. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 75 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings D7 READ/ WRITE R/W RESET VALUE 0 D6–D3 R/W 0111 D2–D1 R/W 11 D0 R/W 0 D7 D6–D4 READ/ WRITE R/W R/W RESET VALUE 0 000 D3–D0 R/W 0000 BIT DESCRIPTION 0: If power-down sequence is activated by device software, power down using page 1 / register 46, bit D7, then power down the DAC simultaneously with the HP and SP amplifiers. 1: If power-down sequence is activated by device software, power down using page 1 / register 46, bit D7, then power down DAC only after HP and SP amplifiers are completely powered down. This is to optimize power-down POP. 0000: Driver power-on time = 0 μs 0001: Driver power-on time = 15.3 μs 0010: Driver power-on time = 153 μs 0011: Driver power-on time = 1.53 ms 0100: Driver power-on time = 15.3 ms 0101: Driver power-on time = 76.2 ms 0110: Driver power-on time = 153 ms 0111: Driver power-on time = 304 ms 1000: Driver power-on time = 610 ms 1001: Driver power-on time = 1.22 s 1010: Driver power-on time = 3.04 s 1011: Driver power-on time = 6.1 s 1100–1111: Reserved. Do not write these sequences to these bits. NOTE: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency. 00: Driver ramp-up step time = 0 ms 01: Driver ramp-up step time = 0.98 ms 10: Driver ramp-up step time = 1.95 ms 11: Driver ramp-up step time = 3.9 ms NOTE: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual oscillator frequency. 0: Weakly driven output common-mode voltage is generated from resistor divider of the AVDD supply. 1: Reserved. Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control BIT 76 DESCRIPTION Reserved. Write only the reset value to this bit. Speaker Power-Up Wait Time (Duration Based on Using Internal Oscillator) 000: Wait time = 0 ms 001: Wait time = 3.04 ms 010: Wait time = 7.62 ms 011: Wait time = 12.2 ms 100: Wait time = 15.3 ms 101: Wait time = 19.8 ms 110: Wait time = 24.4 ms 111: Wait time = 30.5 ms NOTE: These values are based on typical oscillator frequency of 8.2 MHz. The values scale according to the actual oscillator frequency. Reserved. Write only the reset value to these bits. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing D7–D6 READ/ WRITE R/W RESET VALUE 00 D5 R/W 0 BIT D4 0 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 DESCRIPTION 00: DAC_L is not routed anywhere. 01: DAC_L is routed to the left-channel mixer amplifier. 10: DAC_L is routed directly to the HPL driver. 11: Reserved 0: AIN1 input is not routed to the left-channel mixer amplifier. 1: AIN1 input is routed to the left-channel mixer amplifier. 0: AIN2 input is not routed to the left-channel mixer amplifier. 1: AIN2 input is routed to the left-channel mixer amplifier. 00: DAC_R is not routed anywhere. 01: DAC_R is routed to the right-channel mixer amplifier. 10: DAC_R is routed directly to the HPR driver. 11: Reserved 0: AIN2 input is not routed to the right-channel mixer amplifier. 1: AIN2 input is routed to the right-channel mixer amplifier. 0: HPL driver output is not routed to the HPR driver. 1: HPL driver output is routed to the HPR driver input (used for differential output mode). Page 1 / Register 36 (0x24): Left Analog Vol to HPL BIT DESCRIPTION 0: Left-channel analog volume control is not routed to HPL output driver. 1: Left-channel analog volume control is routed to HPL output driver. Left-channel analog volume control gain (non-linear) for the HPL output driver, 0 dB to –78 dB. See Table 5-24. Page 1 / Register 37 (0x25): Right Analog Vol to HPR D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 READ/ WRITE R RESET VALUE 0111 1111 BIT DESCRIPTION 0: Right-channel analog volume control is not routed to HPR output driver. 1: Right-channel analog volume control is routed to HPR output driver. Right-channel analog volume control gain (non-linear) for the HPR output driver, 0 dB to –78 dB. See Table 5-24. Page 1 / Register 38 (0x26): Left Analog Vol to SPK BIT DESCRIPTION 0: Left-channel analog volume control output is not routed to class-D output driver. 1: Left-channel analog volume control output is routed to class-D output driver. Left-channel analog volume control output gain (non-linear) for the class-D output driver, 0 dB to –78 dB. See Table 5-24. Page 1 / Register 39 (0x27): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not use. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 77 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 40 (0x28): HPL Driver D7 D6–D3 READ/ WRITE R/W R/W RESET VALUE 0 0000 D2 R/W 0 D1 R/W 1 D0 R 0 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0000: HPL driver PGA = 0 dB 0001: HPL driver PGA = 1 dB 0010: HPL driver PGA = 2 dB ... 1000: HPL driver PGA = 8 dB 1001: HPL driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. 0: HPL driver is muted. 1: HPL driver is not muted. 0: HPL driver is weakly driven to a common mode during power down. (1) 1: HPL driver is high-impedance during power down. 0: Not all programmed gains to HPL have been applied yet. 1: All programmed gains to HPL have been applied. If D1 is programmed as 0, Page 1 / Register 33 D0 must be set to 0. Page 1 / Register 41 (0x29): HPR Driver D7 D6–D3 READ/ WRITE R/W R/W RESET VALUE 0 0000 D2 R/W 0 D1 R/W 1 D0 R 0 BIT (1) DESCRIPTION Reserved. Write only zero to this bit. 0000: HPR driver PGA = 0 dB 0001: HPR driver PGA = 1 dB 0010: HPR driver PGA = 2 dB ... 1000: HPR driver PGA = 8 dB 1001: HPR driver PGA = 9 dB 1010–1111: Reserved. Do not write these sequences to these bits. 0: HPR driver is muted. 1: HPR driver is not muted. 0: HPR driver is weakly driven to a common mode during power down. (1) 1: HPR driver is high-impedance during power down. 0: Not all programmed gains to HPR have been applied yet. 1: All programmed gains to HPR have been applied. If D1 is programmed as 0, Page 1 / Register 33 D0 must be set to 0. Page 1 / Register 42 (0x2A): Class-D Speaker (SPK) Driver D7–D5 D4–D3 READ/ WRITE R/W R/W RESET VALUE 000 00 D2 R/W 0 D1 D0 R/W R 0 0 READ/ WRITE R RESET VALUE 0000 0000 BIT DESCRIPTION Reserved. Write only zeros to these bits. 00: Cass-D driver output stage gain = 6 dB 01: Class-D driver output stage gain = 12 dB 10: Class-D driver output stage gain = 18 dB 11: Class-D driver output stage gain = 24 dB 0: Class-D driver is muted. 1: Class-D driver is not muted. Reserved. Write only zero to this bit. 0: Not all programmed gains to class-D driver have been applied yet. 1: All programmed gains to class-D driver have been applied. Page 1 / Register 43 (0x2B): Reserved BIT D7–D0 78 DESCRIPTION Reserved. Do not use. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 44 (0x2C): HP Driver Control D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D3 R/W 00 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT (1) DESCRIPTION Debounce Time for Headset Short-Circuit Detection MCLK/DIV (Page 3 / (1) register 16) = 1-MHz Internal Oscillator Source Source 000: Debounce time = 0 μs 0 μs 001: Debounce time = 8 μs 7.8 μs 010: Debounce time = 16 μs 15.6 μs 011: Debounce time = 32 μs 31.2 μs 100: Debounce time = 64 μs 62.4 μs 101: Debounce time = 128 μs 124.9 μs 110: Debounce time = 256 μs 250 μs 111: Debounce time = 512 μs 500 μs Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale according to the actual oscillator frequency. 00: Default mode for the DAC 01: DAC performance increased by increasing the current 10: Reserved 11: DAC performance increased further by increasing the current again 0: HPL output driver is programmed as headphone driver. 1: HPL output driver is programmed as lineout driver. 0: HPR output driver is programmed as headphone driver. 1: HPR output driver is programmed as lineout driver. Reserved. Write only zero to this bit. The clock used for the debounce has a clock period = debounce duration/8. Page 1 / Register 45 (0x2D): Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 D3 R/W R/W 000 0 D2 D1–D0 R/W R/W 0 00 READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D0 R/W 00 0000 BIT D7–D0 DESCRIPTION Reserved. Do not write to this register. Page 1 / Register 46 (0x2E): MICBIAS BIT DESCRIPTION 0: Device software power down is not enabled. 1: Device software power down is enabled. Reserved. Write only zeros to these bits. 0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted. 1: Programmed MICBIAS is powered up even if headset is not inserted. Reserved. Write only zero to this bit. 00: MICBIAS output is powered down. 01: MICBIAS output is powered to 2 V. 10: MICBIAS output is powered to 2.5 V. 11: MICBIAS output is powered to AVDD. Page 1 / Register 47 (0x2F) Through Page 1 / Register 49 (0x31): Reserved BIT D7–D0 DESCRIPTION Reserved. Do not write to these bits. Page 1 / Register 50 (0x32): Input CM Settings BIT DESCRIPTION 0: AIN1 input is floating if it is not used for analog bypass. 1: AIN1 input is connected to CM internally if it is not used for analog bypass. 0: AIN2 input is floating if it is not used for analog bypass. 1: AIN2 input is connected to CM internally if it is not used for analog bypass. Reserved. Write only zeros to these bits. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 79 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved BIT D7–D0 6.4 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only the reset value to these bits. Control Registers, Page 3: MCLK Divider for Programmable Delay Timer Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 3 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected The only register used in page 3 is register 16. The remaining page-3 registers are reserved and should not be written to. Page 3 / Register 16 (0x10): Timer Clock MCLK Divider D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0001 BIT (1) DESCRIPTION 0: Internal oscillator is used for programmable delay timer. 1: External MCLK (1) is used for programmable delay timer. MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer 000 0000: MCLK divider = 128 000 0001: MCLK divider = 1 000 0010: MCLK divider = 2 ... 111 1110: MCLK divider = 126 111 1111: MCLK divider = 127 External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This feature is provided in case a more accurate delay is desired, because the internal oscillator frequency varies from device to device. 6.5 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63) Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 8 / Register 0 (0x00): Page Control Register BIT D7–D0 80 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Page 8 / Register 1 (0x01): DAC Coefficient RAM Control D7–D3 D2 READ/ WRITE R/W R/W RESET VALUE 0000 0 0 D1 R 0 D0 R/W 0 BIT DESCRIPTION Reserved. Write only the reset value. DAC Adaptive Filtering Control 0: Adaptive filtering disabled in DAC processing block 1: Adaptive filtering enabled in DAC processing block DAC Adaptive Filter Buffer Control Flag 0: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer A, and the external control interface accesses DAC coefficient buffer B. 1: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer B, and the external control interface accesses DAC coefficient buffer A. DAC Adaptive Filter Buffer Switch Control 0: DAC coefficient buffers are not switched at the next frame boundary. 1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled. This bit self-clears on switching. The remaining page-8 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3101. Reserved registers should not be written to. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-2 is a list of the page-8 registers, excepting the previously described register 0 and register 1. Table 6-2. Page 8 DAC Buffer A Registers REGISTER NUMBER RESET VALUE 2 (0x02) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad A 3 (0x03) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad A 4 (0x04) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad A 5 (0x05) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad A 6 (0x06) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad A 7 (0x07) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad A 8 (0x08) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad A 9 (0x09) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad A 10 (0x0A) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad A REGISTER NAME 11 (0x0B) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad A 12 (0x0C) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad B 13 (0x0D) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad B 14 (0x0E) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad B 15 (0x0F) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad B 16 (0x10) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad B 17 (0x11) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad B 18 (0x12) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad B 19 (0x13) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad B 20 (0x14) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad B 21 (0x15) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad B 22 (0x16) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad C 23 (0x17) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad C 24 (0x18) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad C REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 81 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-2. Page 8 DAC Buffer A Registers (continued) 82 REGISTER NUMBER RESET VALUE REGISTER NAME 25 (0x19) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad C 26 (0x1A) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad C 27 (0x1B) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad C 28 (0x1C) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad C 29 (0x1D) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad C 30 (0x1E) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad C 31 (0x1F) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad C 32 (0x20) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad D 33 (0x21) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad D 34 (0x22) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad D 35 (0x23) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad D 36 (0x24) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad D 37 (0x25) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad D 38 (0x26) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad D 39 (0x27) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad D 40 (0x28) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad D 41 (0x29) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad D 42 (0x2A) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad E 43 (0x2B) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad E 44 (0x2C) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad E 45 (0x2D) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad E 46 (0x2E) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad E 47 (0x2F) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad E 48 (0x30) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad E 49 (0x31) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad E 50 (0x32) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad E 51 (0x33) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad E 52 (0x34) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad F 53 (0x35) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad F 54 (0x36) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad F 55 (0x37) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad F 56 (0x38) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad F 57 (0x39) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad F 58 (0x3A) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad F 59 (0x3B) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad F 60 (0x3C) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad F 61 (0x3D) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad F 62 (0x3E) 0000 0000 Reserved 63 (0x3F) 0000 0000 Reserved 64 (0x40) 0000 0000 8 MSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25 65 (0x41) 0000 0000 8 LSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25 66 (0x42) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad A 67 (0x43) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad A 68 (0x44) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad A 69 (0x45) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad A 70 (0x46) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad A 71 (0x47) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad A REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-2. Page 8 DAC Buffer A Registers (continued) REGISTER NUMBER RESET VALUE 72 (0x48) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad A 73 (0x49) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad A 74 (0x4A) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad A REGISTER NAME 75 (0x4B) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad A 76 (0x4C) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad B 77 (0x4D) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad B 78 (0x4E) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad B 79 (0x4F) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad B 80 (0x50) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad B 81 (0x51) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad B 82 (0x52) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad B 83 (0x53) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad B 84 (0x54) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad B 85 (0x55) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad B 86 (0x56) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad C 87 (0x57) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad C 88 (0x58) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad C 89 (0x59) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad C 90 (0x5A) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad C 91 (0x5B) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad C 92 (0x5C) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad C 93 (0x5D) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad C 94 (0x5E) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad C 95 (0x5F) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad C 96 (0x60) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad D 97 (0x61) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad D 98 (0x62) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad D 99 (0x63) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad D 100 (0x64) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad D 101 (0x65) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad D 102 (0x66) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad D 103 (0x67) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad D 104 (0x68) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad D 105 (0x69) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad D 106 (0x6A) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad E 107 (0x6B) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad E 108 (0x6C) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad E 109 (0x6D) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad E 110 (0x6E) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad E 111 (0x6F) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad E 112 (0x70) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad E 113 (0x71) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad E 114 (0x72) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad E 115 (0x73) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad E 116 (0x74) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad F 117 (0x75) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad F 118 (0x76) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad F REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 83 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-2. Page 8 DAC Buffer A Registers (continued) 84 REGISTER NUMBER RESET VALUE 119 (0x77) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad F 120 (0x78) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad F 121 (0x79) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad F 122 (0x7A) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad F 123 (0x7B) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad F 124 (0x7C) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad F 125 (0x7D) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad F 126–127 0000 0000 Reserved REGISTER NAME REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com 6.6 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127) Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 9 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected The remaining page-9 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3101. Reserved registers should not be written to. The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-3 is a list of the page-9 registers, excepting the previously described register 0. Table 6-3. Page 9 DAC Buffer A Registers REGISTER NUMBER RESET VALUE 1 (0x01) XXXX XXXX 2 (0x02) 0111 1111 Coefficient N0(15:8) for left DAC-programmable first-order IIR 3 (0x03) 1111 1111 Coefficient N0(7:0) for left DAC-programmable first-order IIR 4 (0x04) 0000 0000 Coefficient N1(15:8) for left DAC-programmable first-order IIR 5 (0x05) 0000 0000 Coefficient N1(7:0) for left DAC-programmable first-order IIR 6 (0x06) 0000 0000 Coefficient D1(15:8) for left DAC-programmable first-order IIR 7 (0x07) 0000 0000 Coefficient D1(7:0) for left DAC-programmable first-order IIR 8 (0x08) 0111 1111 Coefficient N0(15:8) for right DAC-programmable first-order IIR 9 (0x09) 1111 1111 Coefficient N0(7:0) for right DAC-programmable first-order IIR 10 (0x0A) 0000 0000 Coefficient N1(15:8) for right DAC-programmable first-order IIR 11 (0x0B) 0000 0000 Coefficient N1(7:0) for right DAC-programmable first-order IIR 12 (0x0C) 0000 0000 Coefficient D1(15:8) for right DAC-programmable first-order IIR 13 (0x0D) 0000 0000 Coefficient D1(7:0) for right DAC-programmable first-order IIR 14 (0x0E) 0111 1111 Coefficient N0(15:8) for DRC first-order high-pass filter 15 (0x0F) 1111 0111 Coefficient N0(7:0) for DRC first-order high-pass filter 16 (0x10) 1000 0000 Coefficient N1(15:8) for DRC first-order high-pass filter 17 (0x11) 0000 1001 Coefficient N1(7:0) for DRC first-order high-pass filter 18 (0x12) 0111 1111 Coefficient D1(15:8) for DRC first-order high-pass filter 19 (0x13) 1110 1111 Coefficient D1(7:0) for DRC first-order high-pass filter 20 (0x14) 0000 0000 Coefficient N0(15:8) for DRC first-order low-pass filter 21 (0x15) 0001 0001 Coefficient N0(7:0) for DRC first-order low-pass filter 22 (0x16) 0000 0000 Coefficient N1(15:8) for DRC first-order low-pass filter 23 (0x17) 0001 0001 Coefficient N1(7:0) for DRC first-order low-pass filter 24 (0x18) 0111 1111 Coefficient D1(15:8) for DRC first-order low-pass filter 25 (0x19) 1101 1110 Coefficient D1(7:0) for DRC first-order low-pass filter 26–127 0000 0000 Reserved REGISTER NAME Reserved. Do not write to this register. REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 85 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 6.7 www.ti.com Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63) Table 6-4. Page 12 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected The remaining page-12 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3101. Reserved registers should not be written to. The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-5 is a list of the page-12 registers, excepting the previously described register 0. Table 6-5. Page-12 DAC Buffer B Registers 86 REGISTER NUMBER RESET VALUE 1 (0x01) 0000 0000 Reserved. Do not write to this register. 2 (0x02) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad A 3 (0x03) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad A 4 (0x04) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad A 5 (0x05) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad A 6 (0x06) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad A 7 (0x07) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad A 8 (0x08) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad A REGISTER NAME 9 (0x09) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad A 10 (0x0A) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad A 11 (0x0B) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad A 12 (0x0C) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad B 13 (0x0D) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad B 14 (0x0E) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad B 15 (0x0F) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad B 16 (0x10) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad B 17 (0x11) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad B 18 (0x12) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad B 19 (0x13) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad B 20 (0x14) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad B 21 (0x15) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad B 22 (0x16) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad C 23 (0x17) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad C 24 (0x18) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad C 25 (0x19) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad C 26 (0x1A) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad C 27 (0x1B) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad C REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-5. Page-12 DAC Buffer B Registers (continued) REGISTER NUMBER RESET VALUE 28 (0x1C) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad C 29 (0x1D) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad C 30 (0x1E) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad C 31 (0x1F) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad C 32 (0x20) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad D 33 (0x21) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad D 34 (0x22) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad D 35 (0x23) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad D 36 (0x24) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad D 37 (0x25) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad D 38 (0x26) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad D 39 (0x27) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad D 40 (0x28) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad D REGISTER NAME 41 (0x29) 0000 0000 Coefficient D2(17:0) for left DAC-programmable biquad D 42 (0x2A) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad E 43 (0x2B) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad E 44 (0x2C) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad E 45 (0x2D) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad E 46 (0x2E) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad E 47 (0x2F) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad E 48 (0x30) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad E 49 (0x31) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad E 50 (0x32) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad E 51 (0x33) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad E 52 (0x34) 0111 1111 Coefficient N0(15:8) for left DAC-programmable biquad F 53 (0x35) 1111 1111 Coefficient N0(7:0) for left DAC-programmable biquad F 54 (0x36) 0000 0000 Coefficient N1(15:8) for left DAC-programmable biquad F 55 (0x37) 0000 0000 Coefficient N1(7:0) for left DAC-programmable biquad F 56 (0x38) 0000 0000 Coefficient N2(15:8) for left DAC-programmable biquad F 57 (0x39) 0000 0000 Coefficient N2(7:0) for left DAC-programmable biquad F 58 (0x3A) 0000 0000 Coefficient D1(15:8) for left DAC-programmable biquad F 59 (0x3B) 0000 0000 Coefficient D1(7:0) for left DAC-programmable biquad F 60 (0x3C) 0000 0000 Coefficient D2(15:8) for left DAC-programmable biquad F 61 (0x3D) 0000 0000 Coefficient D2(7:0) for left DAC-programmable biquad F 62 (0x3E) 0000 0000 Reserved 63 (0x3F) 0000 0000 Reserved 64 (0x40) 0000 0000 8 MSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25 65 (0x41) 0000 0000 8 LSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25 66 (0x42) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad A 67 (0x43) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad A 68 (0x44) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad A 69 (0x45) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad A 70 (0x46) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad A 71 (0x47) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad A 72 (0x48) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad A 73 (0x49) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad A 74 (0x4A) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad A REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 87 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-5. Page-12 DAC Buffer B Registers (continued) 88 REGISTER NUMBER RESET VALUE REGISTER NAME 75 (0x4B) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad A 76 (0x4C) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad B 77 (0x4D) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad B 78 (0x4E) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad B 79 (0x4F) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad B 80 (0x50) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad B 81 (0x51) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad B 82 (0x52) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad B 83 (0x53) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad B 84 (0x54) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad B 85 (0x55) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad B 86 (0x56) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad C 87 (0x57) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad C 88 (0x58) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad C 89 (0x59) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad C 90 (0x5A) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad C 91 (0x5B) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad C 92 (0x5C) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad C 93 (0x5D) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad C 94 (0x5E) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad C 95 (0x5F) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad C 96 (0x60) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad D 97 (0x61) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad D 98 (0x62) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad D 99 (0x63) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad D 100 (0x64) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad D 101 (0x65) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad D 102 (0x66) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad D 103 (0x67) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad D 104 (0x68) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad D 105 (0x69) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad D 106 (0x6A) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad E 107 (0x6B) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad E 108 (0x6C) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad E 109 (0x6D) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad E 110 (0x6E) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad E 111 (0x6F) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad E 112 (0x70) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad E 113 (0x71) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad E 114 (0x72) 0000 0000 Coefficient ND2(15:8) for right DAC-programmable biquad E 115 (0x73) 0000 0000 Coefficient ND2(7:0) for right DAC-programmable biquad E 116 (0x74) 0111 1111 Coefficient N0(15:8) for right DAC-programmable biquad F 117 (0x75) 1111 1111 Coefficient N0(7:0) for right DAC-programmable biquad F 118 (0x76) 0000 0000 Coefficient N1(15:8) for right DAC-programmable biquad F 119 (0x77) 0000 0000 Coefficient N1(7:0) for right DAC-programmable biquad F 120 (0x78) 0000 0000 Coefficient N2(15:8) for right DAC-programmable biquad F 121 (0x79) 0000 0000 Coefficient N2(7:0) for right DAC-programmable biquad F REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-5. Page-12 DAC Buffer B Registers (continued) REGISTER NUMBER RESET VALUE 122 (0x7A) 0000 0000 Coefficient D1(15:8) for right DAC-programmable biquad F 123 (0x7B) 0000 0000 Coefficient D1(7:0) for right DAC-programmable biquad F 124 (0x7C) 0000 0000 Coefficient D2(15:8) for right DAC-programmable biquad F 125 (0x7D) 0000 0000 Coefficient D2(7:0) for right DAC-programmable biquad F 126–127 0000 0000 Reserved 6.8 REGISTER NAME Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127) Table 6-6. Page 13 / Register 0 (0x00): Page Control Register READ/ WRITE R/W BIT D7–D0 RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected Page 255 selected The remaining page-13 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320DAC3101. Reserved registers should not be written to. The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When programming any coefficient value for a filter, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers should be written in this sequence. Table 6-7 is a list of the page-13 registers, excepting the previously described register 0. Table 6-7. Page 13 DAC Buffer B Registers REGISTER NUMBER RESET VALUE 1 0000 0000 Reserved. Do not write to this register. 2 (0x02) 0111 1111 Coefficient N0(15:8) for left DAC-programmable first-order IIR 3 (0x03) 1111 1111 Coefficient N0(7:0) for left DAC-programmable first-order IIR 4 (0x04) 0000 0000 Coefficient N1(15:8) for left DAC-programmable first-order IIR 5 (0x05) 0000 0000 Coefficient N1(7:0) for left DAC-programmable first-order IIR 6 (0x06) 0000 0000 Coefficient D1(15:8) for left DAC-programmable first-order IIR 7 (0x07) 0000 0000 Coefficient D1(7:0) for left DAC-programmable first-order IIR 8 (0x08) 0111 1111 Coefficient N0(15:8) for right DAC-programmable first-order IIR 9 (0x09) 1111 1111 Coefficient N0(7:0) for right DAC-programmable first-order IIR 10 (0x0A) 0000 0000 Coefficient N1(15:8) for right DAC-programmable first-order IIR 11 (0x0B) 0000 0000 Coefficient N1(7:0) for right DAC-programmable first-order IIR 12 (0x0C) 0000 0000 Coefficient D1(15:8) for right DAC-programmable first-order IIR 13 (0x0D) 0000 0000 Coefficient D1(7:0) for right DAC-programmable first-order IIR 14 (0x0E) 0111 1111 Coefficient N0(15:8) for DRC first-order high-pass filter 15 (0x0F) 1111 0111 Coefficient N0(7:0) for DRC first-order high-pass filter 16 (0x10) 1000 0000 Coefficient N1(15:8) for DRC first-order high-pass filter 17 (0x11) 0000 1001 Coefficient N1(7:0) for DRC first-order high-pass filter 18 (0x12) 0111 1111 Coefficient D1(15:8) for DRC first-order high-pass filter 19 (0x13) 1110 1111 Coefficient D1(7:0) for DRC first-order high-pass filter REGISTER NAME REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 89 TLV320DAC3100 SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-7. Page 13 DAC Buffer B Registers (continued) 90 REGISTER NUMBER RESET VALUE 20 (0x14) 0000 0000 Coefficient N0(15:8) for DRC first-order low-pass filter 21 (0x15) 0001 0001 Coefficient N0(7:0) for DRC first-order low-pass filter 22 (0x16) 0000 0000 Coefficient N1(15:8) for DRC first-order low-pass filter 23 (0x17) 0001 0001 Coefficient N1(7:0) for DRC first-order low-pass filter 24 (0x18) 0111 1111 Coefficient D1(15:8) for DRC first-order low-pass filter 25 (0x19) 1101 1110 Coefficient D1(7:0) for DRC first-order low-pass filter 26–127 0000 0000 Reserved REGISTER NAME REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 TLV320DAC3100 www.ti.com SLAS671A – FEBRUARY 2010 – REVISED MAY 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (February, 2010) to Revision A • • • • • • • • • • • • • Page Changed register 36 to register 35 in section 5.4.2. ....................................................................... Deleted Analog Volume Control for Headphone and Speaker Outputs (for D7=0) table and added table note to D7=1 table. ................................................................................................................ Added D6–D0 to the Register Value column heading and changed Analog Attenuation to Analog Gain. ..... Changed page 0 to page 1 in section 5.5.12.1. ............................................................................. Added 80 MHz ≤ (PLL_CLKIN × J.D × R/P)≤ 110 MHz and 4 ≤ R × J ≤ 259 under equation 7. ..................... Added 80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz and R = 1 under equation 8. .................................. Added Timer section and image after PLL section. ....................................................................... Changed part number from TLV320DAC3101 to TLV320DAC3100. .................................................... Added table note to Page 0 / Register 64 (0x40): DAC VOLUME CONTROL. ......................................... Changed D0=1 to Reserved in Page 1 / Register 33. ...................................................................... Removed extraneous cross-references for deleted table. ................................................................ Added table note to Page 1 / Register 40 (0x28): HPL Driver. ........................................................... Added table note to Page 1 / Register 41 (0x29): HPR Driver. ........................................................... REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLV320DAC3100 21 41 41 42 51 51 52 61 70 76 77 78 78 91 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLV320DAC3100IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV320DAC3100IRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320DAC3100IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC3100IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC3100IRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320DAC3100IRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320DAC3100IRHBR QFN RHB 32 3000 367.0 367.0 35.0 TLV320DAC3100IRHBR QFN RHB 32 3000 367.0 367.0 35.0 TLV320DAC3100IRHBT QFN RHB 32 250 210.0 185.0 35.0 TLV320DAC3100IRHBT QFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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