CIRRUS CS48DV2B-DQZ

CS48DV2B Data Sheet
FEATURES
‰ World’s most cost-effective 32-bit DSP featuring Dolby®
Volume and Audistry® by Dolby
—
—
Supports native processing at input Fs up to 48kHz
Single download image enables support for 32 KHz,
44.1 kHz, and 48 kHz audio input
The new CS48DV2B supports a host of signal processing
applications concurrently, including the mass production-ready
Dolby Volume solution. See Section 3. for details about
firmware concurrency on the CS48DV2B. The target
applications for the CS48DV2B DSP are:
‰ CS48DV2B supports up to 2.0 channels of audio input
and up to 2.1 channels of output
Volume including Tone Control, Multiband Parametric EQ,
Bass Management, Delays.
‰ Configurable Serial Audio Inputs/Outputs
—
Configurable for all input/output digital audio types
(I2S/LJ/RJ)
— 32-bit data path delivers uncompromised dynamic
range
— 192 kHz capable integrated S/PDIF transmitter
— DAO can operate in master or slave mode (SCLK &
LRCLK)
‰ Integrated Clock Manager/PLL
—
—
—
—
PMD/iPod® Docking Stations
Automotive Head Units
Automotive Outboard Amplifiers
— Blu-ray Disc® & DVD Receivers / HTiBs
— PC Speakers
All of these applications and many more that use volume
control and are subject to playback from sources that do not
have consistent volume levels will benefit from the CS48DV2B
Dolby Volume solution.
Capable of operating from a wide variety of external
crystals or external oscillators
‰ Slave Host Boot Capability via Serial Interface
—
Digital Televisions
Soundbars / DTVs with Integrated Soundbars
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‰ Enables concurrent processing features beyond Dolby
—
—
SPI™ interface capable of running up to 25 MHz
during run time
Ordering Information:
See page 21 for ordering information.
‰ 1.8V Core and 3.3V I/O that is tolerant to 5V input
‰ Low-power Mode enabled
Energy Star® Design Compliance Capability via lowpower mode, 268 µW in Standby mode
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S/PDIF
Serial
Control 1
GPIO
Debug
Watchdog
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2.0 Ch.
Audio In
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—
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32-bit
DSP
P
X
TMR1
TMR2
Y
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Up to 2.1 Ch
Audio Out
http://www.cirrus.com
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Copyright 2009 Cirrus Logic
CONFIDENTIAL
FEB ’09
DS875F2
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
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Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to
change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the
use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties.
This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights,
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies
to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend
to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN
PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS
DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S
CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'
FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer is a trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
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Dolby, Audistry, and the sound shell logo are registered trademarks of Dolby Laboratories. Supply of an implementation of Dolby Technology does not convey a license
nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or
ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
SPI is a trademark of Motorola, Inc.
I2C is a registered trademark of Philips Semiconductor.
iPod is a registered trademark of Apple Computer, Inc.
Blu-ray Disc is a registered trademark of SONY KABUSHIKI KAISHA CORPORATION.
Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.
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Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
Table of Contents
1. Documentation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Code Overlays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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4.1 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 DSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 On-chip DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Digital Audio Input Port (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Digital Audio Output Port (DAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Serial Control Port (I2C® or SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 PLL-based Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 DSP I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Termination Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Application Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Digital DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Power Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.5 Thermal Data (48-Pin LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.6 Switching Characteristics— RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Switching Characteristics — XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.8 Switching Characteristics — Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.13 Switching Characteristics — Digital Audio Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.14 Switching Characteristics — DSD Slave Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.15 Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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8.1 CS48DV2B, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 48-pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
List of Figures
List of Tables
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Figure 1. RESET Timing ......................................................................................................................................... 12
Figure 2. XTI Timing ............................................................................................................................................... 12
Figure 3. Serial Control Port - SPI Slave Mode Timing........................................................................................... 14
Figure 4. Serial Control Port - SPI Master Mode Timing......................................................................................... 15
Figure 5. Serial Control Port - I2C Slave Mode Timing ........................................................................................... 16
Figure 6. Serial Control Port - I2C Master Mode Timing ......................................................................................... 17
Figure 7. Digital Audio Input (DAI) Port Timing Diagram ........................................................................................ 18
Figure 8. Direct Stream Digital - Serial Audio Input Timing..................................................................................... 18
Figure 9. Digital Audio Output Port Timing, Master Mode....................................................................................... 20
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ............................................ 20
Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram ............................................................................................. 23
Figure 12. 48-Pin LQFP Package Drawing ............................................................................................................. 24
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Table 1. CS48DV2B DSP Related Documentation................................................................................................5
Table 2. Device and Firmware Selection Guide.....................................................................................................7
Table 3. Ordering Information ..............................................................................................................................21
Table 4. Environmental, Manufacturing, & Handling Information.........................................................................22
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Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
1. Documentation Strategy
The CS48DV2B Data Sheet describes CS48DV2B multichannel audio processors. This document
should be used in conjunction with the following documents when evaluating or designing a system
around the CS48DV2B processors.
Table 1. CS48DV2B DSP Related Documentation
Document Name
Description
CS48DV2B Data Sheet
This document
Includes detailed system design information including
Typical Connection Diagrams, Boot-Procedures, Pin
Descriptions, etc.
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CS485xx Family Hardware User’s Manual
AN298 - CS485xx Family Firmware User’s Manual
DSP Composer User’s Manual
AN298VPMA,Audistry® by Dolby®”
AN298PPMN, Dolby® Volume Firmware User’s
Manual for the CS48DV2x Family
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
Includes detailed configuration and usage
information for the GUI development tool.
Describes API used to control the Audistry firmware
module.
Describes API used to control the Dolby Volume
firmware module.
The scope of the CS48DV2B Data Sheet is primarily the hardware specifications of the CS48DV2B
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS48DV2B Data Sheet is the system PCB designer, MCU
programmer, and the quality control engineer.
2. Overview
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The CS48DV2B DSP is designed to provide high-performance post-processing and mixing of digital
audio. The dual clock domain provided on the PCM inputs allows for the mixing of audio streams with
different sampling frequencies. The low-power standby preserves battery life for applications which
are always on, but not necessarily processing audio, such as automotive audio systems.
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The CS48DV2B supports dual input clock domains and dual audio processing paths. The
CS48DV2B is available in a 48-pin QFP package. Please refer to Table 2 on page 7 for the input,
output, firmware features of each device.
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2.1 Licensing
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Licenses are required for all of the 3rd party audio processing algorithms listed in Section 3. Please
contact your local Cirrus Logic Sales representative for more information.
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
3. Code Overlays
The suite of software available for the CS48DV2B DSP consists of an operating system (OS) and a
library of overlays. The overlays have been divided into three main groups called Matrix-processors,
Virtualizer-processors, and Post-processors. All software components are defined below:
1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, error concealment,
etc.
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2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more
output channels than input channels (2Ön channels). Examples are Dolby® Pro Logic® IIx and
DTS Neo:6™. Generally speaking, these modules increase the number of valid channels in the
audio I/O buffer.
3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than
input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the
physical audio channels that were eliminated. Examples are Dolby Headphone® and Dolby®
Virtual Speaker®. Generally speaking, these modules reduce the number of valid channels in the
audio I/O buffer.
4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the
matrix- or virtualizer-processors. Examples are the Dolby Volume and Audistry by Dolby
firmware, bass management, audio manager, tone control, EQ, delay, and customer-specific
effects
The bulk of each overlay is stored in ROM within the CS48DV2B, but a small image is required to
configure the overlays and boot the DSP. This small image can either be stored in an external serial
FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C® serial port.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For
example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not
need to be reloaded — only the new matrix-processor. This fact is also true for the other overlays.
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Table 2 lists the firmware available based on device selection. Please refer to AN298, CS485xx
Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules
available.
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Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
Table 2. Device and Firmware Selection Guide
Devices
Availability
CS48DV2B-CQZ
In Production Now
• Digital TV
Portable Audio
Docking Station
• Portable DVD
Players
• Multimedia PC
Speakers
• Soundbars
• Automotive
Entertainment
Systems
Specific Features
• 2.1 channels of audio
input and 2.1
channels of PCM
audio output.
• 512 FFT Window, 20Bands/Channel
• Dolby Volume Native
Processing of the
following Fs:
— 32 kHz
— 44.1 kHz
— 48 kHz
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CS48DV2B-DQZ
Suggested Applications
4. Hardware Functional Description
4.1 DSP Core
The CS48DV2B DSPs are single-core DSP with separate X and Y data and P code memory spaces.
The DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of
performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight
72-bit accumulators, four X- and four Y-data registers, and 12 index registers.
The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between
peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output
(DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads
data move instructions from the DSP core, leaving more MIPS available for signal processing
instructions.
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CS48DV2B functionality is controlled by application codes that are stored in on-board ROM or
downloaded to the CS48DV2B from a host controller or external serial FLASH/EEPROM.
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Users can develop their applications using DSP Composer to create the processing chain and then
compile the image into a series of commands that are sent to the CS48DV2B through the SCP. The
processing application can either load modules (matrix-processors, virtualizers, post-processors)
from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.
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The CS48DV2B is suitable for a variety of audio post-processing applications such as automotive
head-ends, automotive amplifiers, and boom boxes.
4.1.1 DSP Memory
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The DSP core has its own on-chip data and program RAM and ROM and does not require external
memory for post-processing applications.
The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P
equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.
4.1.2 DMA Controller
The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource
has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
modes are supported, with flexible start address and increment controls. The service intervals for
each DMA channel, as well as up to 6 interrupt events, are programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
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The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.
The port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD
is supported and internally converted to PCM before processing. The DAI also supports a time
division multiplexed (TDM) one-line data mode that packs multiple channels of PCM audio input on a
single data line. The total number of channels that are possible depends on the ratio of SCLK to
LRCLK.
The port has two independent slave-only clock domains. Each data input can be independently
assigned to a clock domain. The sample rate of the input clock domains can be determined
automatically by the DSP, off-loading the task of monitoring the S/PDIF receiver from the host. A
time-stamping feature allows the input data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as
192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a
clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can
be re-configured as a S/PDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with
embedded clock on a single line).
The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple
channels of PCM audio on a single data line.
4.2.3 Serial Control Port (I2C® or SPI™)
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The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C®
modes. Master/Slave operation is chosen by mode select pins when the CS48DV2B comes out of
Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed
must always be ≤ (Fdclk/2)). The CS48DV2B serial control port also includes a pin for flow control of
the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the
host (SCP_IRQ).
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4.2.4 GPIO
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Many of the CS48DV2B peripheral pins are multiplexed with GPIO. Each GPIO can be configured as
an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising
edge, falling edge, active-low, or active-high.
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4.2.5 PLL-based Clock Generator
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The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used
to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock
domain can be output on the DAO port for driving audio converters. The CS48DV2B defaults to
running from the external reference frequency and is switched to use the PLL output after overlays
have been loaded and configured, either through master boot from an external FLASH or through
host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output
frequency ratio is selectable between 1:1 (default) or 2:1.
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Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
4.2.6 Hardware Watchdog Timer
The CS48DV2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS48DV2B will reset itself in the event of a temporary system failure. In
stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
(that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and
the DSP should be rebooted and re-configured.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
EN
D TI
EL A
L
PH D
I RA
FT
Many of the CS48DV2B pins are multi-functional. For details on pin functionality please refer to the
CS485xx Hardware User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS48DV2B must be pulled high for proper operation. Please refer to the
CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
resistor is required for proper operation.
Mode select pins in the CS48DV2B are used to select the boot mode upon the rising edge from
reset. A detailed explanation of termination requirements for each communication mode select pin
can be found in the CS485xx Hardware User’s Manual.
4.3.3 Pads
The CS48DV2B I/Os operate from the 3.3 V supply and are 5 V tolerant.
4.4 Application Code Security
C
O
N
FI
D
The external program code may be encrypted by the programmer to protect any intellectual property
it may contain. A secret, customer-specific key is used to encrypt the program code that is to be
stored external to the device. Please contact your local Cirrus representative for details.
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
9
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5. Characteristics and Specifications
Note:
All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,
CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)
Parameter
Min
Max
Unit
VDD
VDDA
VDDIO
-0.3
-0.3
-0.3
-
2.0
3.6
3.6
0.3
V
V
V
V
Iin
-
+/-10
mA
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
EN
D TI
EL A
L
PH D
I RA
FT
DC power supplies:
Symbol
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
Storage temperature
Vfilt
-0.3
3.6
V
Vinio
-0.3
5.0
V
Tstg
-65
150
°C
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V)
Parameter
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
Ambient operating temperature
Symbol
Min
Typ
Max
Unit
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
TA
-
CS48DV2B-CQZ
CS48DV2B-DQZ
0
-40
°C
+70
+85
D
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
FI
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
N
Parameter
High-level input voltage
O
Low-level input voltage, except XTI
Low-level input voltage, XTI
Symbol
Min
Typ
Max
Unit
VIH
2.0
-
-
V
VIL
-
-
0.8
V
VILXTI
-
-
0.6
V
Vhys
High-level output voltage (IO = -2mA), except XTI
VOH
VDDIO * 0.9
Low-level output voltage (IO = 2mA), except XTI
VOL
Input leakage XTI
ILXTI
Input leakage current (all digital pins with internal
pull-up resistors enabled)
ILEAK
C
Input Hysteresis
10
0.4
Copyright 2009 Cirrus Logic
CONFIDENTIAL
V
-
-
V
-
-
VDDIO * 0.1
V
-
-
5
μA
-
-
70
μA
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.4 Power Supply Characteristics
(Measurements performed under operating conditions)
Parameter
Min
Typ
Max
Unit
-
203
8
27
480
-
mA
mA
mA
mW
-
100
1
50
348
-
μA
μA
μA
μW
Operational Power Supply Current:
VDD: Core and I/O operating1
VDDA: PLL operating
VDDIO: With most ports operating
Total Operational Power Dissipation:
EN
D TI
EL A
L
PH D
I RA
FT
Standby Power Supply Current:
VDD: Core and I/O not clocked
VDDA: PLL halted
VDDIO: All connected I/O pins 3-stated by other ICs in system
Total Standby Power Dissipation:
1. Dependent on application firmware and DSP clock speed.
5.5 Thermal Data (48-Pin LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Tj
-
-
125
°C
Thermal Resistance (Junction to Ambient)
Two-layer Board1
Four-layer Board2
θja
-
63.5
54
-
°C / Watt
Thermal Resistance (Junction to Top of Package)
Two-layer Board3
Four-layer Board4
ψ jt
-
0.70
0.64
-
°C / Watt
Junction Temperature
1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &
bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top &
bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers.
3. To calculate the die temperature for a given power dissipation
D
Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
FI
4. To calculate the case temperature for a given power dissipation
C
O
N
Tc = Tj - [ (Power Dissipation in Watts) * ψ jt ]
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
11
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.6 Switching Characteristics— RESET
Parameter
Symbol
Min
Max
Unit
Trstl
1
-
ms
All bidirectional pins high-Z after RESET low
Trst2z
-
100
ns
Configuration pins setup before RESET high
Trstsu
50
-
ns
Configuration pins hold after RESET high
Trsthld
20
-
ns
EN
D TI
EL A
L
PH D
I RA
FT
RESET minimum pulse width low
RESET
HS[3:0]
All Bidirectional
Pins
Trstsu Trsthld
Trst2z
Trstl
Figure 1. RESET Timing
5.7 Switching Characteristics — XTI
Parameter
External Crystal operating
frequency1
XTI period
XTI high time
XTI low time
D
External Crystal Load Capacitance (parallel
resonant)2
External Crystal Equivalent Series Resistance
Symbol
Min
Max
Unit
Fxtal
Tclki
11.2896
27
MHz
33.3
100
ns
Tclkih
13.3
-
ns
Tclkil
13.3
-
ns
CL
10
18
pF
50
Ω
ESR
FI
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z
C
O
N
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should
be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor
selection.
XTI
t clkih
t clkil
Tclki
Figure 2. XTI Timing
12
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.8 Switching Characteristics — Internal Clock
Parameter
Internal DCLK
frequency1
Symbol
Min
Max
Fdclk
Fxtal
Fxtal
150
150
6.7
6.7
1/Fxtal
1/Fxtal
CS48DV2B-CQZ
CS48DV2B-DQZ
Internal DCLK period1
DCLKP
CS48DV2B-CQZ
CS48DV2B-DQZ
Unit
MHz
ns
C
O
N
FI
D
EN
D TI
EL A
L
PH D
I RA
FT
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until
the next power-on reset.
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
13
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Parameter
Symbol
Min
Max
Units
SCP_CLK frequency
fspisck
-
25
MHz
SCP_CS falling to SCP_CLK rising
tspicss
24
-
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MOSI input
tspidsu
5
-
ns
Hold time SCP_MOSI input
tspidh
5
-
ns
SCP_CLK low to SCP_MISO output valid
tspidov
-
11
ns
SCP_CLK falling to SCP_IRQ rising
tspiirqh
-
20
ns
SCP_CS rising to SCP_IRQ falling
tspiirql
0
tspicsh
24
SCP_CS rising to SCP_MISO output high-Z
tspicsdz
-
20
ns
SCP_CLK rising to SCP_BSY falling
tspicbsyl
-
3*DCLKP+20
ns
SCP_CLK low to SCP_CS rising
Typical
EN
D TI
EL A
L
PH D
I RA
FT
1
-
ns
ns
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
tspicss
SCP_CS
tspickl
0
SCP_CLK
fspisck
A5
D
tspidsu
6
7
0
A0
R/W
MSB
5
6
7
tspicsh
LSB
tspidov
tspicsdz
MSB
N
FI
tspidh
SCP_MISO
2
tspickh
A6
SCP_MOSI
1
LSB
O
tspiirqh
tspiirql
SCP_IRQ
C
tspibsyl
SCP_BSY
Figure 3. Serial Control Port - SPI Slave Mode Timing
14
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
Symbol
1
Min
fspisck
-
tspicss
-
SCP_CLK low time
tspickl
SCP_CLK high time
Typical
Max
Units
2
Fxtal/2
MHz
-
ns
20
-
ns
tspickh
20
-
ns
Setup time SCP_MISO input
tspidsu
9
-
ns
Hold time SCP_MISO input
tspidh
5
-
ns
SCP_CLK frequency
11*DCLKP +
(SCP_CLK PERIOD)/2
EN
D TI
EL A
L
PH D
I RA
FT
SCP_CS falling to SCP_CLK rising
3
SCP_CLK low to SCP_MOSI output valid
tspidov
-
8
ns
SCP_CLK low to SCP_CS falling
tspicsl
7
-
ns
tspicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
3*DCLKP
-
ns
20
ns
SCP_CLK low to SCP_CS rising
Bus free time between active SCP_CS
tspicsx
SCP_CLK falling to SCP_MOSI output high-Z
tspidz
-
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter
tspicsx
tspicss
EE_CS#
tspickl
tspicsl
0
SCP_MISO
FI
fspisck
D
SCP_CLK
1
A6
A5
2
6
7
0
A0
R/W
MSB
5
7
6
tspicsh
tspickh
LSB
N
tspidsu
tspidov
tspidz
MSB
LSB
C
O
SCP_MOSI
tspidh
DS875F2
Figure 4. Serial Control Port - SPI Master Mode Timing
Copyright 2009 Cirrus Logic
CONFIDENTIAL
15
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Parameter
Symbol
Min
Max
Units
SCP_CLK frequency
fiicck
-
400
kHz
SCP_CLK low time
tiicckl
1.25
-
µs
SCP_CLK high time
tiicckh
1.25
-
µs
tiicckcmd
1.25
START condition to SCP_CLK falling
tiicstscl
1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
Bus free time between STOP and START conditions
tiicbft
3
-
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-
18
ns
SCP_CLK falling to SCP_IRQ rising
tiicirqh
-
3*DCLKP + 40
ns
NAK condition to SCP_IRQ low
tiicirql
1
SCP_CLK rising to SCB_BSY low
µs
EN
D TI
EL A
L
PH D
I RA
FT
SCP_CLK rising to SCP_SDA rising or falling for
START or STOP condition
Typical
tiicbsyl
-
ns
3*DCLKP + 20
ns
3*DCLKP + 20
ns
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer.
tiicckcmd
tiicckl
0
1
SCP_CLK
tiicckh
A6
FI
SCP_SDA
tiicf
7
8
tiicckcmd
0
tiicdov
A0
R/W
1
6
7
8
tiicstp
fiicck
ACK
MSB
LSB
tiicbft
ACK
tiicirqh
tiicirql
tiich
O
N
tiicsu
SCP_IRQ
6
D
tiicstscl
tiicr
tiiccbsyl
C
SCP_BSY
Figure 5. Serial Control Port - I2C Slave Mode Timing
16
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode
Parameter
Symbol
Min
Max
Units
fiicck
-
400
kHz
SCP_CLK low time
tiicckl
1.25
-
µs
SCP_CLK high time
tiicckh
1.25
-
µs
tiicckcmd
1.25
START condition to SCP_CLK falling
tiicstscl
1.25
-
µs
SCP_CLK falling to STOP condition
SCP_CLK
frequency1
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
µs
2.5
-
µs
tiicbft
3
-
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
tiicdov
-
18
ns
EN
D TI
EL A
L
PH D
I RA
FT
tiicstp
Bus free time between STOP and START conditions
SCP_CLK low to SCP_SDA out valid
ns
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
tiicckcmd
tiicckl
0
1
SCP_CLK
tiicstscl
6
tiicckh
A6
SCP_SDA
tiicr
8
0
tiicdov
A0
tiich
7
tiicckcmd
R/W
1
6
7
8
tiicstp
fiicck
ACK
MSB
LSB
tiicbf
ACK
D
tiicsu
tiicf
C
O
N
FI
Figure 6. Serial Control Port - I2C Master Mode Timing
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
17
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.13 Switching Characteristics — Digital Audio Slave Input Port
Parameter
Symbol
Min
Max
Unit
Tdaiclkp
40
-
ns
-
45
55
%
Setup time DAI_DATAn
tdaidsu
10
-
ns
Hold time DAI_DATAn
tdaidh
5
-
ns
DAI_SCLK period
DAI_SCLK duty cycle
EN
D TI
EL A
L
PH D
I RA
FT
DAI_SCLK
tdaidsu
tdaidh
DAI_DATAn
Figure 7. Digital Audio Input (DAI) Port Timing Diagram
5.14 Switching Characteristics — DSD Slave Input Port
Min
78
78
1.024
20
20
Typ
-
Max
3.2
-
Unit
ns
ns
MHz
ns
ns
C
O
N
FI
D
Parameter
Symbol
DSD_SCLK Pulse Width Low
tsclkl
DSD_SCLK Pulse Width High
tsclkh
DSD_SCLK Frequency
(64x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time
tsdlrs
DSD_SCLK rising to DSD_A or DSD_B hold time
tsdh
Figure 8. Direct Stream Digital - Serial Audio Input Timing
18
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.15 Switching Characteristics — Digital Audio Output Port
Parameter
DAO_MCLK period
Symbol
Min
Max
Unit
Tdaomclk
40
-
ns
-
45
55
%
DAO_MCLK duty cycle
1
DAO_SCLK period for Master or Slave mode
Tdaosclk
40
-
ns
-
40
60
%
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
tdaomsck
-
19
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaomstlr
-
respectively3
tdaomlrts
-
8
ns
tdaomdv
-
10
ns
tdaosdv
-
15
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaosstlr
-
30
ns
3
tdaoslrts
-
15
ns
DAO_SCLK duty cycle for Master or Slave mode1
EN
D TI
EL A
L
PH D
I RA
FT
Master Mode (Output A1
Mode)1,2
DAO_SCLK delay from DAO_LRCLK transition,
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
8
ns
Slave Mode (Output A0 Mode)4
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
DAO_SCLK delay from DAO_LRCLK transition, respectively
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
data is valid.
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk
DAO_MCLK
tdaomclk
DAO_MCLK
N
tdaomdv
tdaomsck
DAO_SCLK
FI
DAO_SCLK
D
tdaomsck
O
DAOn_DATAn
tdaomlrts
tdaomstlr
DAO_LRCLK
C
DAO_LRCLK
DAOn_DATAn
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
19
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
Figure 9. Digital Audio Output Port Timing, Master Mode
tdaosstlr
tdaosclk
DAO_LRCLK
DAO_LRCLK
DAO_SCLK
tdaosclk
tdaoslrts
EN
D TI
EL A
L
PH D
I RA
FT
DAOn_DATAn
DAO_SCLK
tdaosdv
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
C
O
N
FI
D
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
20
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
6. Ordering Information
The CS48DV2B part number is described as follows:
CS48DVNI-XYZR
where
N - Product Number Variant
I - ROM ID Number
X - Product Grade
Z - Lead (Pb) Free
EN
D TI
EL A
L
PH D
I RA
FT
Y - Package Type
R - Tape and Reel Packaging
Table 3. Ordering Information
Part No.
CS48DV2B-CQZ
CS48DV2B-DQZ
Grade
Temp. Range
Package
Commercial
0 to +70 °C
48-pin LQFP
Automotive
-40 to +85 °C
48-pin LQFP
C
O
N
FI
D
NOTE: Please contact the factory for availability of the -D (automotive grade) package.
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
21
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
7. Environmental, Manufacturing, & Handling Information
Table 4. Environmental, Manufacturing, & Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
260 °C
3
7 Days
CS48DV2B-CQZ
CS48DV2B-CQZR
CS48DV2B-DQZ
CS48DV2B-DQZR
C
O
N
FI
D
EN
D TI
EL A
L
PH D
I RA
FT
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
22
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
8. Device Pinout Diagrams
GPIO4, DAO1_ DATA2, HS2
GPIO18, DAO_MCLK
26
25
GNDIO3
30
GPIO3, DAO1_ DATA1, HS1
GPIO6, DAO2 _DATA0, HS3
31
27
GPIO7, DAO2_D ATA1, HS4
32
VDD2
GND4
33
28
GPIO9, SCP_MOSI
34
CS48DV2B
42
10
11
12
GPIO16, DAI1_DATA0, TM0, DSD0
GPIO0, DAI1_DATA1, TM1, DSD1
VDDIO1
DBDA
RESET#
FI
TEST
N
GND3
DAO_LRCLK
20
DAO1_DATA0, HS0
GNDIO2
18
GPIO15, DAI2_SCLK
17
GPIO14, DAI2_LRCLK
16
VDD1
15
GPIO17, DAI2_DATA0, DSD4
14
GPIO2, DAI1_DATA3, TM3, DSD3
13
GPIO1, DAI1_DATA2, TM2, DSD2
C
O
9
48
GND2
VDDA (3.3V)
8
47
DAI1_SCLK, DSD-CLK
PLL_REF_RES
7
46
GNDIO1
GNDA
6
45
DAI1_LRCLK, DAI1_DATA4, DSD5
XTO
5
44
1
XTI
DAO_SCLK
21
19
48-Pin LQFP
43
VDDIO2
EN
D TI
EL A
L
PH D
I RA
FT
41
D
XTAL_OUT
40
3
VDD3
22
2
GPIO13, SCP_BSY , EE_CS
GPIO5, DAO1_DATA3, X MTA
GPIO10, SCP__MISO / SDA
35
23
39
GNDIO4
29
GPIO11, SCP_CLK
38
DBCK
GPOI12, SCP_IRQ
24
4
GPIO8, SCP_CS
37
GND1
VDDIO3
36
8.1 CS48DV2B, 48-pin LQFP Pinout Diagram
Figure 11. CS48DV2B 48-Pin LQFP Pinout Diagram
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
8.2 48-pin LQFP Package Drawing
D
Number of Leads
48
MIN
NOM
MAX
1.60
0.05
0.15
1.35
1.40
1.45
0.17
0.22
0.27
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0
7
0.45
0.60
0.75
1.00 REF
C
O
N
FI
A
A1
A2
b
D
D1
e
E
E1
theta
L
L1
EN
D TI
EL A
L
PH D
I RA
FT
48 LD LQFP (7 x 7 x 1.4 mm body)
NOTES:
1) Reference document: JEDEC MS-026
2) All dimensions are in millimeters and controlling dimension is in millimeters.
3) D1 and E1 do not include mold flash which is 0.25 mm max. per side.A1
4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
Figure 12. 48-Pin LQFP Package Drawing
24
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
9. Revision History
Date
Changes
F1
December 3, 2008
Initial Release of CS48DV2B Data Sheet
F2
February 16, 2009
Updated Section 5.5, adding Junction Temperature specification.
C
O
N
FI
D
EN
D TI
EL A
L
PH D
I RA
FT
Revision
DS875F2
Copyright 2009 Cirrus Logic
CONFIDENTIAL
25
C
O
N
FI
D
EN
D TI
EL A
L
PH D
I RA
FT
CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
26
Copyright 2009 Cirrus Logic
CONFIDENTIAL
DS875F2