CIRRUS VRE4125K

VRE4112
VRE4100
VRE4125
VRE4141
P r o d u c t I n n o v a t i o nF r o m
Product Innovation From
Precision Voltage Reference
Features
♦ +1.250, +2.500, +4.096 V Output
♦ Initial Error: ± 0.05% Max.
♦ Temperature Drift: 1.0 ppm/ºC Max.
♦ Low Noise: 2.2 μVP-P (0.1 Hz-10 Hz, 1.024 V)
♦ Low Thermal Hysteresis: 20 ppm
♦ ±8 mA Output Source
♦ Power Down Mode
♦ Industry Standard SOIC 8-pin Package
♦ Commercial and Industrial Temp Ranges
♦ Second source for ADR29X, REF19X ,LT1460,
LT1461, LT1798, MAX616X, REF102
Applications
This series is recommended for use as a reference for
14, 16, or 18-bit data converters which require a precision reference. The series offers superior performance
over standard on-chip references commonly found
with data converters.
DESCRIPTION
The VRE4112/VRE4125/VRE4141 are low cost, high
precision bandgap references that operate from +5 V.
These devices feature low noise, digital error correction, and an SOIC-8 package. The ultra stable output
is 0.05% accurate with a temperature coefficient as
low as 1.0 ppm/ºC. The improvement in overall accuracy is made possible by using EEPROM registers and
CMOS DAC’s for temperature and initial error correction. The DAC trimming is done after assembly which
eliminates assembly related shifts.
Selection Guide
Model
Output
(V)
Temp. Coeff.
(ppm/ºC)
Temp. Range
(ºC)
VRE4112C
VRE4112K
+1.250
+1.250
2.0
3.0
0ºC to +70ºC
-40ºC to +85ºC
VRE4125B
VRE4125K
+2.500
+2.500
1.0
3.0
0ºC to +70ºC
-40ºC to +85ºC
VRE4141B
VRE4141K
+4.096
+4.096
1.0
3.0
0ºC to +70ºC
-40ºC to +85ºC
VRE4100DS
http://www.cirrus.com
Copyright
© Cirrus
Logic, Inc. 2009
(All Rights Reserved)
8-pin SOIC
Package Style FX
APR 2009 APEX − VRE4100DSREVA
VRE4100
P r o d u c t I n n o v a t i o nF r o m
1. Characteristics and Specifications
ABSOLUTE MAXIMUM RATINGS
Output Short Circuit Duration............................... Indefinite
ESD Susceptibility Human Body Model....................... 2kV
ESD Susceptibility Machine Model............................. 200V
Lead Temperature (soldering, 10 sec).....................+260ºC
Power Supply to any input pin.......-0.3V to +5.6V
Operating Temp. (B,C)....................... 0ºC to 70ºC
Operating Temp. (K).....................-40ºC to +85ºC
Storage Temperature Range......-65ºC to +150ºC
ELECTRICAL Specifications
VPS = +3 V for VRE4112, VPS = +5 V for VRE4125 and VRE4141. T = +25ºC, ILOAD = 1mA, COUT = 1µF Unless Otherwise Noted.
Parameter
Symbol
Input Voltage
Conditions
Min
Typ
Max
Units
+5.5
V
B Grade
±0.025
±0.050
C/K Grade
±0.040
±0.080
VIN
Output Voltage Error
(Note 1)
VOUT
Output Voltage
Temperature Coefficient
(Note 2)
TCVOUT
Dropout Voltage (Note 3)
+1.8
B Grade
+0.5
+1.0
C Grade
+1.0
+2.0
K Grade
+1.5
+3.0
235
%
ppm/ºC
VIN - VOUT
IL = 8mA
160
Turn-On Settling Time
TON
To 0.01% of final value
2
µs
Output Noise Voltage
(Note 4)
En
0.1Hz < f < 10Hz
2.2
µVp-p
Note 5
20
ppm
Temperature Hysteresis
Long Term Stability
Supply Current
∆VOUT/T
1000 Hours
50
IIN
VLOAD = 0mA
230
320
µA
1mA ≤ ILOAD ≤ 8mA
1
20
ppm/mA
20
200
ppm/V
Load Regulation (Note 6) ∆VOUT/ ∆IOUT
Line Regulation
(Note 6)
mV
∆VOUT/ ∆VIN
Logic High Input Voltage
VH
Logic High Input Current
IH
Logic Low Input Voltage
VL
Logic Low Input Current
IL
VREF + 200mV ≤ VIN ≤ 5.5V
ppm
0.8
V
2
nA
0.4
1
V
nA
NOTES:
1. High temperature and mechanical stress can effect the initial accuracy of this reference series.See
discussion on output accuracy.
2. The temperature coefficient is determined by the box method. See discussion on temperature performance. All units are 100% tested over temperature.
3. The minimum input to output differential voltage at which the output voltage drops by 0.5% from
nominal.
4. Based on 1.024 V output. Noise is linearly proportional to VREF.
5. Defined as change in 25ºC output voltage after cycling device over operating temperature range.
6. Line and load regulation are measured with pulses and do not include output voltage changes due to
self heating.
VRE4100DS
VRE4100
P r o d u c t I n n o v a t i o nF r o m
2. TYPICAL PERFORMANCE CURVES
Load Regulation vs Temperature
Output Voltage vs Load Current
Load Transient Response
Line Regulation vs Temperature
Power Up/Down Ground Current
Line Transient Response
Enable Response
VRE4100DS
Output Impedance
Power Supply Rejection Ratio
VRE4100
P r o d u c t I n n o v a t i o nF r o m
Total Current (Is(ON)) vs Supply Voltage
Total Current (Is(OFF)) vs Supply Voltage
Ground Current vs Load Current
Output Voltage Change vs Sink Current I(SINK)
Dropout Voltage vs Load Current
IQ vs Temperature
Dropout Voltage vs Load Current (VOUT) = 2.0V
Spectral Noise Density (0.1Hz to 10Hz)
Spectral Noise Density (10Hz to 100kHz)
VRE4100DS
VRE4100
P r o d u c t I n n o v a t i o nF r o m
3. TEMPERATURE PERFORMANCE
This series is designed for applications where the initial error at room temperature and drift over temperature are
important to the user. For many instrument manufacturers, a voltage reference with a temperature coefficient of
1ppm/ºC makes it possible to eliminate a system temperature calibration, a slow and costly process.
Of the three TC specification methods (slope, butterfly, and box), the box method is most commonly used. A box
is formed by the min/max limits for the nominal output voltage over the operating temperature range. The equation
follows:
VMAX – VMIN
TC =
x 106
VNOMINAL x (TMAX – TMIN)
This method corresponds more accurately to the method of test and provides a closer estimate of actual error than
the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape
or slope of the device under test.
4. BASIC CIRCUIT CONNECTION
The proper connection for the VRE4112/VRE4125/VRE4141 series voltage references is shown below.
To achieve the specified performance, pay careful attention to the layout. Commons should be connected to a single
point to minimize interconnect resistances. This will reduce voltage errors, noise pickup, and noise coupled from
the power supply.
PIN DESCRIPTION
4
GND
These must be connected to ground
2
VIN
Positive power supply input
3
Enable
Pulled to VIN for nominal operation
1,5,7,8
NC
This pin must be left open
6
VOUT
Reference output
EXTERNAL CONNECTIONS
+ VIN
2
Enable
3
+ VOUT
VRE4112 6
VRE4125
VRE4141
1,5,7,8
COUT 1µF
NC
4
VRE4100DS
VRE4100
P r o d u c t I n n o v a t i o nF r o m
For example a designer who needs a 14-bit accurate data acquisition system over the industrial temperature range
(-40ºC to +85ºC), will need a voltage reference with a temperature coefficient (TC) of 1.0ppm/ºC if the reference is
allowed to contribute an error equivalent to 1LSB. The required reference TC vs. ∆T change from 25ºC for resolution
ranging from 8 bits to 20 bits is shown below.
10000
Reference TC (ppm/ºC)
1000
100
8 BIT
10 BIT
10
12 BIT
1
14 BIT
16 BIT
0.1
18 BIT
0.01
20 BIT
1
10
100
Reference TC vs. ∆T change from 25°C for 1 LSB change
4. OPERATIONAL NOTES
Input Capacitor
An input capacitor is recommended for the VRE4112/VRE4125/VRE4141. A supply bypass capacitor on the input
will assure that the reference is working from a low impedance source which will improve stability. It can improve
the transient response when the load current is suddenly increased.
Output Capacitor
This series requires a 1 μF output capacitor for loop stabilization (compensation) as well as transient response.
When the load current changes, the output capacitor must source or sink current during the time it takes the control
loop of the device to respond.
The output capacitor must meet the requirements of minimum capacitance and equivalent series resistance (ESR)
range. See Capacitor Selection below.
Capacitor Selection
A minimum value of 0.2 μF over the operating temperature range is recommended. For a 0.22 μF capacitor the ESR
range for 0°C to +70°C is 0.9 to 6.0; 1.0 μF is 0.8 to 6.0; and 10 μF is 0.4 to 7.0.
Surface mount tantalum capacitors offer small size for the value and ESR in the range required for this series. The
optimum performance for the output capacitor is achieved with a 1.0 μF value.
Aluminum electrolytic capacitors have a relatively large size for the value. They meet the ESR requirements at 1.0
μF as long as the temperature is above 0°C. Below 0°C, the ESR increases and it may exceed the limits indicated
in the figures.
Multilayer ceramic capacitors have a small size for the value, are available in surface mount, and have excellent
RF characteristics. They may not meet the minimum ESR requirements and have a large change in value with
temperature.
VRE4100DS
VRE4100
P r o d u c t I n n o v a t i o nF r o m
Reverse Current Path
The P-channel pass transistor used in this series has an inherent diode connected between the Vin and VOUT pins.
Forcing the output to voltages higher than the input or pulling Vin below the voltage stored in the output capacitor
by more than the Vbe will forward bias this diode and current will flow from the Vout pin to Vin. This will not damage
the device as long as the current does not exceed 50 mA.
ON/OFF Operation
This series features a sleep mode that is activated by pulling the enable pin low. To turn the reference on, the enable pin is pulled high. If this feature is not used, the enable pin should be tied to Vin to keep the reference on at all
times. The enable pin must not be left unconnected (floating).
When powered off, these devices will quickly reduce both Vout and IQ to zero. During power down, the charge
across the output capacitor is discharged to ground through the internal circuitry. On power up, the Vout is restored
in less than 200 μs.
The signal source used to drive the enable pin can come from either a totem-pole output or an open collector output
with a pull-up resistor to the input voltage. The signal source must be able to swing above and below the voltage
thresholds to guarantee an ON or OFF state. It must not exceed the absolute maximum rating for the enable pin.
Output Accuracy
The output accuracy after assembly at room temperature is made up of three components: initial accuracy of the device, thermal hysteresis, and mechanical stress. The initial accuracy is measured at the factory and may not reflect
the actual output voltage when the devices are mounted to a PCB. The effects of mechanical stress and thermal
hysteresis can shift the output voltage.
Thermal Hysteresis
Thermal hysteresis is a change in output voltage as a result of a temperature change. When references experience
a temperature change and return to the initial temperature, they do not always have the same initial voltage. Thermal hysteresis is difficult to correct and is a major error source in systems that experience temperature changes
greater than 25°C. Reference vendors are starting to include this important specification in their datasheets
Mechanical Hysteresis
Recommendations to minimize mechanical stress:
1) Mount the VRE4112/VRE4125/VRE4141 near the edges or corners of the PCB. The center of the board generally
has the highest mechanical and thermal stress.
2) Mechanically isolate the device by cutting a U shaped slot around the package. This provides some mechanical
and thermal isolation from the rest of the circuit.
PIN CONFIGURATION
NC
1
+VIN
2
Enable
3
GND
4
VRE4100DS
8
NC
VRE4100
7
NC
TOP
VIEW
6
VREF
5
NC
VRE4100
P r o d u c t I n n o v a t i o nF r o m
Contacting Cirrus Logic Support
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact [email protected]
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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VRE4100DS