Si8401DB Vishay Siliconix P-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) −20 rDS(on) (W) ID (A) 0.065 @ VGS = −4.5 V −4.9 0.095 @ VGS = −2.5 V −4.1 D TrenchFETr Power MOSFET D New MICRO FOOTr Chipscale Packaging Reduces Footprint Area Profile (0.62 mm) and On-Resistance Per Footprint Area D Pin Compatible to Industry Standard Si3443DV APPLICATIONS D PA, Battery and Load Switch D Battery Charger Switch D PA Switch MICRO FOOT Bump Side View 3 S Backside View 2 D S 4 8401 xxx D G Device Marking: 8401 xxx = Date/Lot Traceability Code G D 1 P-Channel MOSFET Ordering Information: Si8401DB-T1 Si8401DB-T1—E3 (Lead Free) ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol 5 secs Steady State Drain-Source Voltage VDS −20 Gate-Source Voltage VGS "12 Continuous Drain Current (TJ = 150_C)a TA = 25_C TA = 70_C Pulsed Drain Current ID IS TA = 25_C Maximum Power Dissipationa TA = 70_C Operating Junction and Storage Temperature Range Package Reflow Conditionsb PD V −3.6 −4.9 −3.9 −2.8 IDM continuous Source Current (Diode Conduction)a −10 −2.5 −2.5 2.77 1.47 1.77 0.94 TJ, Tstg Unit −55 to 150 VPR 215/245c IR/Convection 220/250c A W _C _C THERMAL RESISTANCE RATINGS Parameter M i Maximum JJunction-to-Ambient ti t A bi ta Maximum Junction-to-Foot (drain) Symbol t v 5 sec Steady State Steady State RthJA RthJF Typical Maximum 35 45 72 85 16 20 Unit _C/W C/W Notes a. Surface Mounted on 1” x 1” FR4 Board. b. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering. c. Package reflow conditions for lead-free. Document Number: 71674 S-40384—Rev. F, 01-Mar-04 www.vishay.com 1 Si8401DB Vishay Siliconix SPECIFICATIONS (TJ = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol Test Condition Min Typ VGS(th) VDS = VGS, ID = −250 mA −0.45 −0.9 Max Unit Static Gate Threshold Voltage Gate-Body Leakage IGSS Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain Source On-State Drain-Source On State Resistancea VDS = 0 V, VGS = "12 V Diode Forward Voltagea "100 VDS = −20 V, VGS = 0 V −1 VDS = −20 V, VGS = 0 V, TJ = 70_C −5 VDS v −5 V, VGS = −4.5 V rDS(on) DS( ) Forward Transconductancea V nA mA −5 A VGS = −4.5 V, ID = −1 A 0.057 0.065 VGS = −2.5 V, ID = −1 A 0.080 0.095 gfs VDS = −10 V, ID = −1 A 6 VSD IS = −1 A, VGS = 0 V −0.73 −1.1 11 17 VDS = −10 V, VGS = −4.5 V, ID = −1 A 2.1 W S V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd 2.9 Turn-On Delay Time td(on) 17 Rise Time tr Turn-Off Delay Time VDD = −10 V, RL = 10 W ID ^ −1 A, VGEN = −4.5 V, RG = 6 W td(off) Fall Time tf Source-Drain Reverse Recovery Time trr nC 25 28 45 88 135 60 90 ns IF = − A, di/dt = 100 A/ms Notes a. Pulse test; pulse width v 300 ms, duty cycle v 2%. b. Guaranteed by design, not subject to production testing. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Output Characteristics 10 Transfer Characteristics 10 VGS = 5 thru 2.5 V 8 2V I D − Drain Current (A) I D − Drain Current (A) 8 6 4 2 1.5 V 6 4 TC = 125_C 2 25_C −55_C 0 0 2 4 6 8 VDS − Drain-to-Source Voltage (V) www.vishay.com 2 10 0 0.0 0.5 1.0 1.5 2.0 2.5 VGS − Gate-to-Source Voltage (V) Document Number: 71674 S-40384—Rev. F, 01-Mar-04 Si8401DB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) On-Resistance vs. Drain Current Capacitance 1500 1200 0.12 C − Capacitance (pF) r DS(on) − On-Resistance ( W ) 0.15 VGS = 2.5 V 0.09 VGS = 4.5 V 0.06 Ciss 900 600 Coss 0.03 300 0.00 0 Crss 0 1 2 3 4 5 6 7 0 4 Gate Charge rDS(on) − On-Resiistance (Normalized) V GS − Gate-to-Source Voltage (V) 20 VGS = 4.5 V ID = 1 A 1.4 6 4 2 1.2 1.0 0.8 0 0 4 8 12 16 0.6 −50 20 −25 Qg − Total Gate Charge (nC) Source-Drain Diode Forward Voltage 25 50 75 100 125 150 On-Resistance vs. Gate-to-Source Voltage 0.30 r DS(on) − On-Resistance ( W ) TJ = 150_C 1 TJ = 25_C 0.1 0.0 0 TJ − Junction Temperature (_C) 10 I S − Source Current (A) 16 On-Resistance vs. Junction Temperature 1.6 VDS = 10 V ID = 1 A 8 12 VDS − Drain-to-Source Voltage (V) ID − Drain Current (A) 10 8 0.24 ID = 1 A 0.18 0.12 0.06 0.00 0.2 0.4 0.6 0.8 1.0 VSD − Source-to-Drain Voltage (V) Document Number: 71674 S-40384—Rev. F, 01-Mar-04 1.2 0 1 2 3 4 5 6 VGS − Gate-to-Source Voltage (V) www.vishay.com 3 Si8401DB Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Threshold Voltage Single Pulse Power, Juncion-To-Ambient 0.4 80 ID = 250 mA 0.3 0.2 Power (W) V GS(th) Variance (V) 60 0.1 40 0.0 20 −0.1 −0.2 −50 −25 0 25 50 75 100 125 150 0 0.001 0.01 TJ − Temperature (_C) 0.1 1 10 Time (sec) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 72_C/W 3. TJM − TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10−4 10−3 10−2 10−1 1 Square Wave Pulse Duration (sec) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Foot Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10−4 www.vishay.com 4 10−3 10−2 10−1 Square Wave Pulse Duration (sec) 1 10 Document Number: 71674 S-40384—Rev. F, 01-Mar-04 Si8401DB Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 4-BUMP (2 X 2, 0.8-mm PITCH) 4 O 0.30 X 0.31 Note 3 Solder Mask O X 0.40 e A A2 Silicon A1 Bump Note 2 b Diamerter e S Recommended Land E e 8401 XXX e S D Mark on Backside of Die NOTES (Unless Otherwise Specified): 1. Laser mark on the silicon die back, coated with a thin metal. 2. Bumps are Eutectic solder 63/57 Sn/Pb. (Sn 3.8 Ag, 0.7 Cu for Pb-free bumps) 3. Non-solder mask defined copper landing pad. 4. The flat side of wafers is oriented at the bottom. MILLIMETERS* INCHES Dim Min Max Min Max A 0.600 0.650 0.0236 0.0256 A1 0.260 0.290 0.0102 0.0114 A2 0.340 0.360 0.0134 0.0142 b 0.370 0.410 0.0146 0.0161 D 1.520 1.600 0.0598 0.0630 E 1.520 1.600 0.0598 0.0630 e 0.750 0.850 0.0295 0.0335 S 0.370 0.380 0.0146 0.0150 * Use millimeters as the primary measurement. Document Number: 71674 S-40384—Rev. F, 01-Mar-04 www.vishay.com 5