ELPIDA HB52R329E22-A6F

HB52R329E22-F
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256 MB Registered SDRAM DIMM
32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module
(36 pcs of 16 M × 4 Components)
PC100 SDRAM
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Description
E0112H10 (1st edition)
(Previous ADE-203-1046A (Z))
Feb. 28, 2001
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The HB 52R 329E22 belongs to 8-byte DI MM (D ual In- line Memory Module) fa mily, and has bee n deve loped
as an optimiz ed main memory solution for 8-byte proc essor applica tions. The HB 52R 329E22 is a 16M × 72
× 2-ba nk S ynchronous Dyna mic R AM Module, mounted 36 piec es of 64-Mbit S DRA M (H M5264405F TB )
sea led in TC P pac kage and 1 piec e of P LL cloc k drive r (2510) , 3 piec es re giste r drive r (162835) , 1 piec e of
inver te r and 1 piec e of ser ia l EEP RO M (2- kbit EEP RO M) for P rese nce De te ct (P D). An outline of the
HB 52R 329E22 is 168-pin socke t type pac kage (dua l lea d out). The ref ore, the HB 52R 329E22 make s high
density mounting possible without surf ace mount tec hnology. The HB 52R 329E22 provide s common data
inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.
Features
• Fully compatible with : JEDEC standard outline registered 8-byte DIMM
: Intel PCB Reference design (Rev. 1.2)
• 168-pin socket type package (dual lead out)
 Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
 Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
This Product became EOL in October, 2005.
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Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be
electrical defects.
HB52R329E22-F
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 Sequential (BL = 1/2/4/8/full page)
 Interleave (BL = 1/2/4/8)
Programmable CE latency : 3/4 (HB52R329E22-A6F)
: 4 (HB52R329E22-B6F)
Byte control by DQMB
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
 Auto refresh
 Self refresh
Full page burst length capability
 Sequential burst
 Burst stop capability
•
•
•
•
•
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Ordering Information
Frequency
CE latency
Package
Contact pad
HB52R329E22-A6F
HB52R329E22-B6F
100 MHz
100 MHz
3/4
4
168-pin dual lead out socket type
Gold
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Type No.
Data Sheet No. E0112H10
2
HB52R329E22-F
Pin Arrangement
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1 pin 10 pin 11 pin
40 pin 41 pin
85 pin 94 pin 95 pin 124 pin 125 pin
84 pin
168 pin
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Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
S3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VCC
48
NC
90
VCC
132
NC
7
DQ4
49
VCC
91
DQ36
133
VCC
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VCC
101
DQ45
143
VCC
18
VCC
60
DQ20
102
VCC
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VCC
68
VSS
110
VCC
152
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Pin No.
VSS
Data Sheet No. E0112H10
3
HB52R329E22-F
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
27
W
69
DQ24
111
CE
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0
72
DQ27
114
S1
156
DQ59
31
NC
73
VCC
115
RE
157
VCC
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
37
A8
38
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Pin No.
VSS
120
A7
162
VSS
79
CK2
121
A9
163
CK3
A10 (AP)
80
NC
122
A13 (BA0)
164
NC
39
A12 (BA1)
81
WP
123
A11
165
SA0
40
VCC
82
SDA
124
VCC
166
SA1
41
VCC
83
42
CK0
84
Pr
78
SCL
125
CK1
167
SA2
VCC
126
NC
168
VCC
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Data Sheet No. E0112H10
4
HB52R329E22-F
Pin Description
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Pin name
Function
A0 to A11
Address input
 Row address
A0 to A11
 Column address
A0 to A9
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
S0 to S3
Chip select input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Write enable input
DQMB0 to DQMB7
Byte data mask
Clock input
CKE0
Clock enable input
WP
Write protect for serial PD
1
REGE*
Register enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
NC
Note:
Serial address input
Primary positive power supply
Ground
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VSS
Pr
CK0 to CK3
VCC
BA0/BA1
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A13/A12
No connection
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
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Data Sheet No. E0112H10
5
HB52R329E22-F
Serial PD Matrix*1
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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
0
0C
12
4
Number of column addresses
bits
0
0
0
0
1
0
1
0
0A
10
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
0
1
0
0
1
0
0
0
48
72 bit
7
Module data width (continued)
0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels
0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
6 ns
11
Module configuration type
12
Refresh rate/type
13
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Byte No. Function described
Pr
1
1
0
0
0
0
0
60
*3
0
0
0
0
0
0
1
0
02
ECC
1
0
0
0
0
0
0
0
80
Normal
(15.625 µs)
Self refresh
SDRAM width
0
0
0
0
0
1
0
0
04
16M × 4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04
×4
15
SDRAM device attributes:
0
minimum clock delay for back-toback random column addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8,
full page
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
(-A6F)
0
0
0
0
0
1
1
0
06
2, 3
0
0
0
0
0
1
0
0
04
3
0
0
0
0
0
0
0
1
01
0
(-B6F)
19
SDRAM device attributes:
S latency
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0
Data Sheet No. E0112H10
6
HB52R329E22-F
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM device attributes
0
0
0
1
0
1
1
0
16
Registered
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
0
0
0
0
0
0
0
0
00
0
1
1
0
0
0
0
0
60
EO
Byte No. Function described
(-B6F) Undefined
24
L
SDRAM access from Clock
(2nd highest CE latency)
(-A6F) 6 ns
(-B6F) Undefined
0
0
0
0
0
0
0
0
00
CL = 2
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on module 0
0
1
0
0
0
0
0
20
2 bank
128M byte
32
Address and command signal
input setup time
0
0
1
0
0
0
0
0
20
2 ns*3
33
Address and command signal
input hold time
0
0
0
1
0
0
0
0
10
1 ns*3
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns*3
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns*3
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6F)
0
0
1
1
0
1
1
1
37
55
0
0
1
1
0
1
0
1
35
53
Manufacturer’s JEDEC ID code
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
00
(-B6F)
64
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25
Data Sheet No. E0112H10
7
HB52R329E22-F
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
72
Manufacturing location
×
×
×
×
×
×
×
×
××
* 4 (ASCII8bit code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
1
0
0
1
0
52
R
78
Manufacturer’s part number
0
0
1
1
0
0
1
1
33
3
79
Manufacturer’s part
0
0
1
1
0
0
1
0
32
2
80
Manufacturer’s part number
0
0
1
1
1
0
0
1
39
9
81
Manufacturer’s part number
0
1
0
0
0
1
0
1
45
E
82
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
83
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
84
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
85
Manufacturer’s part number
(-A6F)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
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Byte No. Function described
Pr
(-B6F)
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
87
Manufacturer’s part number
0
1
0
0
0
1
1
0
46
F
88
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*5
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD) * 5
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86
95 to 98 Assembly serial number
*7
99 t o 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*6
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification CE# latency
support
(-A6F)
1
0
0
0
0
1
1
1
87
CL = 2, 3
1
0
0
0
0
1
0
1
85
CL = 3
(-B6F)
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Data Sheet No. E0112H10
8
HB52R329E22-F
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Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These
SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte10, 32 through 35 are component spec.
4. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
5. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
6. All bits of 99 through 125 are not defined (“1” or “0”).
7. Bytes 95 through 98 are assembly serial number.
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Data Sheet No. E0112H10
9
HB52R329E22-F
Block Diagram
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RS0
RS1
RDQMB0
RDQMB4
DQMB CS
4
10 Ω
DQ0 to DQ3
I/O0
to I/O3
D0
DQMB CS
4
10 Ω
DQ4 to DQ7
I/O0
to I/O3
D1
DQMB CS
I/O0
to I/O3
I/O0
to I/O3
D2
DQMB CS
4
DQ12 to DQ15
10 Ω
I/O0
to I/O3
D3
DQMB CS
CB0 to CB3
4
10 Ω
I/O0
to I/O3
D4
10 Ω
4
10 Ω
4
10 Ω
I/O0
to I/O3
4
10 Ω
DQ16 to DQ19
I/O0
to I/O3
D5
DQMB CS
4
10 Ω
I/O0
to I/O3
D6
I/O0
to I/O3
D28
DQMB CS
I/O0
to I/O3
DQ40 to DQ43
DQMB CS
DQ44 to DQ47
DQMB CS
I/O0
to I/O3
I/O0
to I/O3
CB4 to CB7
D29
DQMB CS
D12
I/O0
to I/O3
DQMB
D22
I/O0
to I/O3
I/O0
to I/O3
D11
DQMB CS
D21
I/O0
to I/O3
DQMB CS
DQMB CS
D20
D30
DQMB
D13
D31
I/O0
to I/O3 CS
I/O0
to I/O3
DQMB CS
DQMB CS
CS
DQMB CS
I/O0
to I/O3
D23
4
10 Ω
4
10 Ω
DQ48 to DQ51
DQMB CS
I/O0
to I/O3
D24
DQ52 to DQ55
I/O0
to I/O3
D14
I/O0
to I/O3
DQMB CS
DQMB CS
I/O0
to I/O3
D32
D15
I/O0
to I/O3
D33
RDQMB7
DQMB CS
4
10 Ω
DQ24 to DQ27
I/O0
to I/O3
D7
DQMB CS
4
10 Ω
DQ28 to DQ31
I/O0
to I/O3
D8
DQMB CS
I/O0
to I/O3
D25
I/O0
to I/O3
10 Ω
4
10 Ω
DQ56 to DQ59
DQMB CS
D26
R
E
G
I
S
T
E
R
10k
I/O0
to I/O3
D16
DQ60 to DQ63
SCL
SDA
U0
A0
A1
I/O0
to I/O3
SDA
WP
A2
D17
I/O0
to I/O3
10 Ω
I/O0
to I/O3
D35
PLL
12 pF
CK : SDRAMs
(D0 to D35)
Register
10 Ω
VSS
12 pF
VCC (D0 to D35, U0)
0.22 µF × 19 pcs
VSS (D0 to D35, U0)
* D0 to D35: HM5264405
PLL: 2510
Register: 162835
U0: 2k bit EEPROM
47 kΩ
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SA0 SA1 SA2 VSS
Notes:
1. The SDA pull-up resistor is required due to the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
Data Sheet No. E0112H10
D34
DQMB CS
DQMB CS
RS0, RS1, RS2, RS3
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CK1
RA0 to RA11 -> A0 to A11: SDRAMs D0 to D35
to CK3
RRAS -> RAS: SDRAMs D0 to D35
RCAS -> CAS: SDRAMs D0 to D35
VCC
RCKE0 -> CKE: SDRAMs D0 to D35
0.0022 µF × 25 pcs
RW -> WE: SDRAMs D0 to D35
VSS
Serial PD
SCL
DQMB CS
DQMB CS
4
CK0
S0, S1, S2, S3
DQMB0 to DQMB7
BA0 to BA1
A0 to A11
RE
CE
CKE0
W
10
DQMB CS
D10
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od
RDQMB3
VCC
REGE
PLL CK
D27
RDQMB6
DQMB CS
DQ20 to DQ23
4
DQ36 to DQ39
Pr
RS2
RS3
RDQMB2
10 Ω
I/O0
to I/O3
DQMB CS
D19
L
DQ8 to DQ11
4
I/O0
to I/O3
D9
RDQMB5
DQMB CS
10 Ω
10 Ω
DQMB CS
RDQMB1
4
4
DQ32 to DQ35
I/O0
to I/O3
DQMB CS
DQMB CS
D18
HB52R329E22-F
Absolute Maximum Ratings
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Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
18.0
W
Operating temperature
Topr
0 to +55
°C
Storage temperature
Tstg
–50 to +100
°C
Note:
L
1. Respect to VSS
DC Operating Conditions (Ta = 0 to +55°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1, 2
Input low voltage
Ambient illuminance
0
0
V
3
VIH
2.0
VCC
V
1, 4
VIL
0
0.8
V
1, 5
—
—
100
lx
All voltage referred to VSS
The supply voltage with all VCC and VCCQ pins must be on the same level.
The supply voltage with all VSS and VSS Q pins must be on the same level.
VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
VIL (min) = VCC – 2.0 V for pulse width ≤ 3 ns at VSS .
t
uc
od
Notes: 1.
2.
3.
4.
5.
Pr
Input high voltage
VSS
Data Sheet No. E0112H10
11
HB52R329E22-F
VIL/VIH Clamp (Component characteristics)
EO
This SDRAM component has VIL and VIH clamp for CK, CKE, S, DQMB and DQ pins.
Minimum VIL Clamp Current
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
L
VIL (V)
–1.2
–1
–0.9
–8
–4
–2
–0.8
–0.6
–0.6
0
Pr
–0.4
0
–0.2
0
0
0
0
I (mA)
–10
–15
–20
–25
–30
–35
–2
–1.5
–1
–0.5
0
uc
od
–5
VIL (V)
t
Data Sheet No. E0112H10
12
HB52R329E22-F
Minimum VIH Clamp Current (referred to VCC)
EO
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
L
VIH (V)
VCC + 0.4
VCC + 0.2
VCC + 0
I (mA)
8
6
4
2
0
VCC + 0.5
uc
od
0
VCC + 0
0
Pr
10
0
VCC + 1
VCC + 1.5
VCC + 2
VIH (V)
t
Data Sheet No. E0112H10
13
HB52R329E22-F
IOL/IOH Characteristics (Component characteristics)
EO
Output Low Current (I OL)
I OL
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
L
1
58
151
70
188
72
194
75
203
1.8
77
209
1.95
77
212
3
80
220
3.45
81
223
1.4
1.5
1.65
IOL (mA)
200
150
uc
od
Pr
250
min
max
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Vout (V)
t
Data Sheet No. E0112H10
14
HB52R329E22-F
Output High Current (I OH ) (Ta = 0 to 55˚C, VCC = 3.0 V to 3.45 V, VSS = 0 V)
EO
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
–73
–248
–78
–270
–81
–285
1
–89
–345
0
–93
–503
L
I OH
1.65
1.5
1.4
–200
0.5
1
1.5
2
2.5
3
3.5
uc
od
IOH (mA)
–100
0
Pr
0
min
–300
–400
–500
–600
max
Vout (V)
t
Data Sheet No. E0112H10
15
HB52R329E22-F
DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
EO
HB52R329E22
-A6F/B6F
Symbol
Min
Max
Unit
Test conditions
Notes
Operating current
(CE latency = 3)
—
2315
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CE latency = 4)
I CC1
—
2315
mA
Standby current in power down I CC2P
—
803
mA
CKE = VIL, t CK = 12 ns
6
Standby current in power down I CC2PS
(input signal stable)
—
767
mA
CKE = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
1271
mA
CKE, S = VIH,
t CK = 12 ns
4
Active standby current in power I CC3P
down
—
839
mA
CKE = VIL, t CK = 12 ns
1, 2, 6
Active standby current in non
power down
—
1415
mA
CKE, S = VIH,
t CK = 12 ns
1, 2, 4
t CK = min, BL = 4
1, 2, 5
L
Parameter
(CE latency = 4)
I CC4
I CC4
Pr
Burst operating current
(CE latency = 3)
I CC3N
—
2315
mA
—
2315
mA
—
3125
mA
t RC = min
3
—
731
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
–10
10
µA
0 ≤ Vin ≤ VCC
I CC5
Self refresh current
I CC6
Input leakage current
I LI
Output leakage current
I LO
–10
10
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
V
I OL = 4 mA
uc
od
Refresh current
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
t
Data Sheet No. E0112H10
16
HB52R329E22-F
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
EO
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CI1
25
pF
1, 2, 4
Input capacitance (RE, CE, W)
CI2
25
pF
1, 2, 4
Input capacitance (CKE)
CI3
45
pF
1, 2, 4
Input capacitance (S)
CI4
20
pF
1, 2, 4
Input capacitance (CK)
CI5
45
pF
1, 2, 4
Input capacitance (DQMB)
CI6
20
pF
1, 2, 4
Input/Output capacitance (DQ)
CI/O1
25
pF
1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Data-out.
This parameter is sampled and not 100% tested.
L
Notes: 1.
2.
3.
4.
t
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od
Pr
Data Sheet No. E0112H10
17
HB52R329E22-F
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
EO
HB52R329E22
-A6F/B6F
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
System clock cycle time
(CE latency = 3)
t CK
Tclk
10
—
ns
(CE latency = 4)
t CK
Tclk
10
—
ns
CK high pulse width
t CKH
Tch
4
—
ns
1
CK low pulse width
t CKL
Tcl
4
—
ns
1
t AC
Tac
—
7.5
ns
t AC
Tac
—
7.5
ns
t OH
Toh
2.1
—
ns
1, 2
(CE latency = 4)
Data-out hold time
1
L
Access time from CK
(CE latency = 3)
Notes
1, 2
t LZ
1.1
—
ns
1, 2, 3
CK to Data-out high impedance
t HZ
—
7.5
ns
1, 4
Data-in setup time
Pr
CK to Data-out low impedance
Tsi
2.9
—
ns
1
t DH
Thi
3.4
—
ns
1
t AS
Tsi
2.6
—
ns
1
t AH
Thi
3.0
—
ns
1
t CES
Tsi
2.6
—
ns
1, 5
t CESP
Tpde
2.6
—
ns
1
CKE hold time
t CEH
Thi
3.0
—
ns
1
Command setup time
t CS
Tsi
2.6
—
ns
1
Command hold time
t CH
Thi
3.0
—
ns
1
Ref/Active to Ref/Active command period t RC
Trc
70
—
ns
1
Active to precharge command period
t RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t RCD
Trcd
20
—
ns
1
Precharge to active command period
t RP
Trp
20
—
ns
1
Write recovery or data-in to precharge
lead time
t DPL
Tdpl
10
—
ns
1
Active (a) to Active (b) command period
t RRD
Trrd
20
—
ns
1
Transition time (rise to fall)
tT
1
5
ns
Refresh period
t REF
—
64
ms
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit
t
uc
od
t DS
Data Sheet No. E0112H10
18
HB52R329E22-F
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES defines CKE setup time to CK rising edge except power down exit command.
EO
Notes: 1.
2.
3.
4.
5.
Test Conditions
L
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
• Ambient illuminance: Under 100 lx
2.4 V
input
0.4 V
DQ
2.0 V
0.8 V
CL
Pr
t
T
tT
t
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od
Data Sheet No. E0112H10
19
HB52R329E22-F
Relationship Between Frequency and Minimum Latency
EO
HB52R329E22
Parameter
-A6F/B6F
Frequency (MHz)
100
PC100
Symbol Symbol 10
Notes
Active command to column command (same bank)
I RCD
2
1
Active command to active command (same bank)
I RC
7
= [IRAS + I RP]
1
Active command to precharge command (same bank)
I RAS
5
1
Precharge command to active command (same bank)
I RP
2
1
1
1
2
1
2
2
3
= [IDPL + I RP]
7
= [IRC]
3
L
tCK (ns)
Write recovery or data-in to precharge command (same I DPL
bank)
Active command to active command (different bank)
I RRD
Self refresh exit time
I SREX
I APW
Self refresh exit to command input
Precharge command to high impedance
(CE latency = 3)
(CE latency = 4)
Last data out to precharge (early precharge)
(CE latency = 3)
(CE latency = 4)
Column command to column command
DQMB to data in
DQMB to data out
CKE to CK disable
Register set to active command
S to command disable
Power down exit to command input
Tdal
I SEC
I HZP
Troh
3
I HZP
Troh
4
uc
od
Last data out to active command (auto precharge)
(same bank)
Write command to data in latency
Tsrx
Pr
Last data in to active command
(Auto precharge, same bank)
Tdpl
I APR
0
I EP
–2
I EP
–3
I CCD
Tccd
1
I WCD
Tdwd
1
I DID
Tdqm
1
I DOD
Tdqz
3
I CLE
Tcke
2
I RSA
Tmrd
1
I CDD
0
I PEC
1
t
Data Sheet No. E0112H10
20
HB52R329E22-F
HB52R329E22
-A6F/B6F
Frequency (MHz)
100
EO
Parameter
tCK (ns)
PC100
Symbol Symbol 10
Burst stop to output valid data hold
(CE latency = 3)
I BSR
2
I BSR
3
I BSH
3
I BSH
4
I BSW
1
(CE latency = 4)
Burst stop to output high impedance
(CE latency = 3)
(CE latency = 4)
L
Burst stop to write data ignore
Notes
Notes: 1. I RCD to I RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
t
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od
Pr
Data Sheet No. E0112H10
21
HB52R329E22-F
Pin Functions
EO
CK0 to CK3 (in pu t p in ): C K is the master cloc k input to this pin. The other input signals ar e re fe rre d at C K
rising edge.
S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE , CE an d W (in pu t p in s): Although these pin name s ar e the same as those of conve ntiona l DR AMs, they
func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the
combination of their voltage levels. For details, refer to the command operation section.
L
A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive
command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or
wr ite command cyc le C K rising edge . And this column addr ess bec omes burst ac ce ss start addr ess. A10
defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But
whe n A10 = Low at the pre cha rge command cyc le, only the bank that is sele cted by A12/A13 (B A) is
precharged.
Pr
A12/A13 (input pin): A12/A13 are bank select signal (BA). The memory array is divided into bank 0, bank 1,
bank 2 and bank 3. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is
selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising
edge is valid. If C KE is Low, the next C K rising edge is invalid. This pin is used for powe r-dow n and cloc k
suspend modes.
uc
od
DQMB 0 to DQMB 7 (in pu t p in s) : R ea d oper ation: If DQMB is High, the output buff er bec omes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z.
Wr ite oper ation: If DQMB is High, the pre vious data is held (the new data is not wr itten) . If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
t
Data Sheet No. E0112H10
22
HB52R329E22-F
Command Operation
EO
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE
Symbol
n-1 n
S
RE
CE
W
A0
A12/A13 A10 to A11
Ignore command
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
BST
H
×
L
H
H
L
×
×
×
Column address and read command
READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
×
L
H
L
H
V
H
V
Column address and write command
WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
×
L
H
L
L
V
H
V
Pr
Burst stop in full page
L
Command
Row address strobe and bank active
Precharge select bank
Precharge all bank
Refresh
Mode register set
ACTV
H
×
L
L
H
H
V
V
V
PRE
H
×
L
L
H
L
V
L
×
PALL
H
×
L
L
H
L
×
H
×
REF/SELF H
V
L
L
L
H
×
×
×
MRS
×
L
L
L
L
V
V
V
H
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
uc
od
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command input
at the clock. However, the internal status is held.
No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page) and
is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the
start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition, the
start address of burst read is determined by the column address and the bank select address (BA). After the read
operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
t
Data Sheet No. E0112H10
23
HB52R329E22-F
EO
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the
burst wr ite mode is sele cted, the column addr ess and the bank sele ct addr ess (B A) bec ome the burst wr ite start
addr ess. Whe n the single wr ite mode is sele cte d, data is only wr itten to the loca tion spec ified by the column
address and the bank select address (BA).
Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this
command is illegal.
L
Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by B ank
sele ct addr ess (B A) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2
is activated. When A12 and A13 are High, bank 3 is activated.
Pr ech arge sele cte d b ank [PR E] : This command starts pre cha rge oper ation for the bank sele cted by B ank
sele ct addr ess (B A) . If A12 and A13 ar e Low, bank 0 is sele cted. If A12 is High and A13 is Low, bank 1 is
selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Pr
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the
one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mod e re gister set [M RS ]: The S DRA M module has a mode re giste r that def ines how it oper ates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
re giste r conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode
register set command to set up the mode register.
t
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od
Data Sheet No. E0112H10
24
HB52R329E22-F
DQMB Truth Table
EO
CKE
Command
Symbol
n-1
n
DQMB
Write enable/output enable
ENB
H
×
L
Write inhibit/output disable
MASK
H
×
H
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: I DID is needed.
Read: I DOD is needed.
L
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other
hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
Pr
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held
(the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or burst wr ite by setting DQMB .
For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
CKE
n
S
RE
CE
W
Address
Clock suspend mode entry
H
L
×
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Command
Active
Self refresh
Power down
Self refresh exit (SELFX)
Power down exit
Note: H: VIH. L: VIL. ×: VIH or VIL.
uc
od
n-1
Current state
t
Clock susp en d mod e en tr y: The S DRA M module ente rs cloc k suspend mode fr om ac tive mode by setting
C KE to Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k
suspend mode changes depending on the current status (1 clock before) as shown below.
Data Sheet No. E0112H10
25
HB52R329E22-F
EO
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the
bank active status.
RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to
be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted.
However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock susp en d mod e exit : The S DRA M module exits fr om cloc k suspend mode by setting C KE to High
during the clock suspend state.
L
IDLE: In this state, all banks are not selected, and completed precharge operation.
Pr
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module starts
auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M module. F or
eve ry auto- ref resh cyc le, the interna l addr ess counte r is update d. Ac cordingly, 4096 time s ar e re quired to
refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state.
In addition, since the pre cha rge for all banks is automatica lly per forme d afte r auto- ref resh, no pre cha rge
command is required after auto-refresh.
S elf-r ef re sh en tr y [S E LF] : Whe n this command is input during the ID LE state, the S DRA M module starts
self- re fre sh oper ation. Af te r the exe cution of this command, self- re fre sh continues while C KE is Low. S inc e
self-refresh is performed internally and automatically, external refresh operations are unnecessary.
uc
od
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module enters
powe r down mode. In powe r down mode, powe r consumption is suppre sse d by cutting off the initia l input
circuit.
S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M module ca n exit
from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state.
Powe r d own exit : Whe n this command is exe cute d at the powe r down mode, the S DRA M module ca n exit
from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
t
Data Sheet No. E0112H10
26
HB52R329E22-F
Function Truth Table
EO
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM module. The following table assumes that CKE is high.
Current state
S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
Idle
L
H
H
BA, RA
ACTV
ILLEGAL*4
L
L
H
L
BA, A10
PRE, PALL
NOP*6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
Begin read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
t
uc
od
Pr
Row active
L
Data Sheet No. E0112H10
27
HB52R329E22-F
Current state
RE
CE
W
Address
Command
Operation
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10 READ/READ A
Continue burst read to CE
latency and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and
Precharge
Read with autoprecharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10 READ/READ A
Term burst and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
Pr
BST
ILLEGAL
t
uc
od
Write
L
EO
Read
S
Data Sheet No. E0112H10
28
HB52R329E22-F
S
RE
CE
W
Address
Command
Operation
Write with autoprecharge
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
Refresh
(auto-refresh)
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
ILLEGAL*5
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*5
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
uc
od
Pr
L
EO
Current state
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If t RRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
t
Data Sheet No. E0112H10
29
HB52R329E22-F
From PRECHARGE state, command operation
EO
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE state
after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
L
To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
Pr
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
uc
od
T o [PR E] , [PA LL ]: The se commands set the S DRA M module to pre cha rge mode. (H oweve r, an interva l of
tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE latency,
the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
t
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
Data Sheet No. E0112H10
30
HB52R329E22-F
From READ with AUTO-PRECHARGE state, command operation
EO
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the
SDRAM module then enters precharge mode.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
L
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
Pr
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
uc
od
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM
module enters precharge mode.
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
T o [D ES L] , [N OP] , [B S T] : Af te r an auto- ref resh cyc le (a fter tRC), the S DRA M module automatica lly ente rs
the IDLE state.
t
Data Sheet No. E0112H10
31
HB52R329E22-F
Simplified State Diagram
EO
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
L
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
Pr
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
CKE
READ
WRITE
WITH
AP
READ
WRITE
READ
WITH AP
WRITEA
CKE
POWER
ON
CKE
READ
SUSPEND
READ
WITH AP
CKE_
READA
CKE
PRECHARGE
POWER
APPLIED
CKE_
READ
PRECHARGE
CKE_
WRITEA
SUSPEND
WRITE
WITH AP
Read
uc
od
WRITE
WITH AP
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
t
Data Sheet No. E0112H10
32
HB52R329E22-F
Mode Register Configuration
EO
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode
register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9 A8: (OPCODE ): The S DRA M module has two types of wr ite modes. One is the
burst write mode, and the other is the single write mode. These bits specify write mode.
B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column
address specified in the write cycle.
L
B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
Pr
A2, A1, A0: (BL): These pins specify the burst length.
A13
A12
A11
A10
A9
A8
OPCODE
A7
A6
0
0
0
0
0
1
R
0
1
0
3*
0
1
1
4
1
X
X
R
A8
0
0
0
0
0
0
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
1
Note: Only -6A.
Write mode
BT
0 Sequential
1
Burst read and single write
R
A2
A1
A0
BL
A3 Burst Type
Burst read and burst write
R
A3
uc
od
0
R
A9
A4
LMODE
A6 A5 A4 CAS Latency
A13 A12 A11 A10
A5
Interleave
A2 A1 A0
Burst Length
BT=0
BT=1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
t
Data Sheet No. E0112H10
33
HB52R329E22-F
Burst Sequence
EO
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A1
0
0
0
0
0
1
L
A2
A0 Sequential
Interleave
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
Pr
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
t
uc
od
Data Sheet No. E0112H10
34
HB52R329E22-F
Operation of the Registered SDRAM module
EO
Read/Write Operations
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the
status of the B ank sele ct addr ess (B A) pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11
pins at the bank active command cycle. An interval of tRCD is required between the bank active command input
and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the
(CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
L
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column
address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts
after the number of clocks specified by the CE Latency. The CE Latency can be set to 3 or 4.
Whe n the burst length is 1, 2, 4 or 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the
successive burst-length data has been output.
Pr
The CE latency and burst length must be specified at the mode register.
CE Latency
CK
Command
Address
Dout
ACTV
Row
CL = 3
CL = 4
READ
Column
uc
od
t RCD
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CE latency
Burst Length = 4
t
Data Sheet No. E0112H10
35
HB52R329E22-F
Burst Length
EO
CK
t RCD
Command
ACTV
READ
Address
Row
Column
BL = 1
out 0
out 0 out 1
BL = 2
Dout
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
L
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
BL = full page
out 0-1
out 0
out 1
BL : Burst Length
CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8)
of the mode register.
Pr
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the next clock as a write command set. (The latency of data input is 1 clock.) The burst length can be set to
1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess
(and the bank select address (BA) at the write command set cycle.
CK
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page
uc
od
t RCD
Command
in 8
in 0-1
in 0
in 1
CE Latency = 3, 4
t
Data Sheet No. E0112H10
36
HB52R329E22-F
EO
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite
oper ation, data is only wr itten to the column addr ess and the bank selec t addr ess (B A) spec ified by the wr ite
command set cycle without regard to the burst length setting. (The latency of data input is 1 clock).
CK
Command
Address
t RCD
WRIT
ACTV
Row
Column
L
Din
Auto Precharge
in 0
Pr
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a
re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d
for the same bank after the execution of this command must be the bank active (ACTV) command. In addition,
an interval defined by lAPR is required before execution of the next command.
CE latency
Precharge start cycle
4
2 cycle before the final data is output
3
1 cycle before the final data is output
CK
CL=3 Command
ACTV
READ A
lRAS
Dout
uc
od
Burst Read (Burst Length = 4)
ACTV
out0
out1
out2
out3
lAPR = 0
CL=4 Command
ACTV
READ A
lRAS
Dout
ACTV
out0
out1
out2
out3
lAPR = 0
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
t
Data Sheet No. E0112H10
37
HB52R329E22-F
EO
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a
burst write or single write operation, a precharge command need not be executed after each write operation. The
command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV )
command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next
command.
Burst Write (Burst Length = 4)
CK
L
Command
ACTV
ACTV
WRIT A
IRAS
Din
in0
in1
in2
in3
lAPW
Pr
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
Command
ACTV
ACTV
WRIT A
IRAS
Din
uc
od
CK
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
t
Data Sheet No. E0112H10
38
HB52R329E22-F
Full-page Burst Stop
EO
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a
full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The
timing from command input to the last data changes depending on the CE latency setting. In addition, the BST
command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CE latency
BST to valid data
BST to high impedance
3
2
3
4
3
4
L
CE Latency = 3, Burst Length = full page
CK
Pr
BST
Command
Dout
out
out
out
out
out
out
out
l BSH = 3 clocks
l BSR = 2 clocks
CK
BST
Command
Dout
uc
od
CE Latency = 4, Burst Length = full page
out
out
out
out
out
out
l BSR = 3 clocks
out
out
l BSH = 4 clocks
t
Data Sheet No. E0112H10
39
HB52R329E22-F
EO
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input
during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt
cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command.
Burst Length = full page
CK
BST
Command
L
Din
in
in
PRE/PALL
in
t DPL
I BSW = 1 cycle
t
uc
od
Pr
Data Sheet No. E0112H10
40
HB52R329E22-F
Command Intervals
EO
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address of
the same bank as the preceding read command execution, the second read can be performed after an interval of
no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the
second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
Command
Address
ACTV
Row
L
CK
READ
READ
Column A Column B
BA
Dout
Bank0
Active
Pr
out A0 out B0 out B1 out B2 out B3
Column =A Column =B
Read
Read
Column =A Column =B
Dout
Dout
CE Latency = 4
Burst Length = 4
Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad
commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command
and a bank-active command.
uc
od
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad
that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout
Dout
CE Latency = 4
Burst Length = 4
t
Data Sheet No. E0112H10
41
HB52R329E22-F
Write command to Write command interval:
EO
1. Same bank, same ROW address: When another write command is executed at the same ROW address of
the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less
than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Row
BA
Din
WRIT
WRIT
L
Address
ACTV
Column A Column B
in A0
in B1
in B2
in B3
Column =A Column =B
Write
Write
Pr
Bank0
Active
in B0
Burst Write Mode
Burst Length = 4
Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a
bank-active command.
uc
od
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite
command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
Bank3 Bank0 Bank3
Active Write Write
in B0
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
t
Data Sheet No. E0112H10
42
HB52R329E22-F
Read command to Write command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the
same bank as the preceding read command, the write command can be performed after an interval of no less than
1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
CK
Command
CL=4
Din
L
CL=3
DQMB
READ WRIT
in B0
in B1
in B2
in B3
Burst Length = 4
Burst write
High-Z
Dout
Pr
READ to WRITE Command Interval (2)
CK
Command
WRIT
uc
od
DQMB
READ
2 clock
CL=3
Dout
CL=4
Din
High-Z
High-Z
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so that
the output buffer becomes High-Z before data input.
t
Data Sheet No. E0112H10
43
HB52R329E22-F
Write command to Read command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the
same bank as the preceding write command, the read command can be performed after an interval of no less than
1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cyc le bef ore the re ad
command is executed.
WRITE to READ Command Interval (1)
CK
DQMB
Din
WRIT
READ
L
Command
in A0
Dout
out B1
out B0
out B2
Pr
Column = A
Write
Column = B
Read
out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
CE Latency
Column = B
Dout
WRITE to READ Command Interval (2)
CK
WRIT
READ
DQMB
Din
in A0
in A1
Dout
uc
od
Command
out B0
Column = A
Write
out B1
CE Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot
be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive
command.
t
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data
will continue to be written until one clock before the read command is executed (as in the case of the same bank
and the same address).
Data Sheet No. E0112H10
44
HB52R329E22-F
Read with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by
the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond
command.
Read with Auto Precharge to Read Command Interval (Different bank)
CK
Command
Dout
READ
L
BA
READ A
bank0
Read A
out A0
out A1
out B0
bank3
Read
out B1
CE Latency = 4
Burst Length = 4
Note: Internal auto-precharge starts at the timing indicated by "
".
Pr
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one
bank starts at the next clock of the second command .
uc
od
Write with Auto Precharge to Write Command Interval (Different bank)
CK
Command
WRIT A
WRIT
BA
Din
in A0
bank0
Write A
in A1
bank3
Write
in B0
Note: Internal auto-precharge starts at the timing indicated by "
in B1
in B2
in B3
Burst Length = 4
".
2. Same bank: The consecutive write command (the same bank) is illegal.
t
Data Sheet No. E0112H10
45
HB52R329E22-F
Read with auto precharge to Write command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input. The
internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CK
Command
READ A
WRIT
DQMB
L
BA
CL = 3
CL = 4
Din
Dout
in B0
in B1
in B2
in B3
High-Z
Pr
bank0
Read A
Burst Length = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet No. E0112H10
46
HB52R329E22-F
Write with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Howe ver , in ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad
command is executed. The internal auto-precharge of one bank starts at the next clock of the second command.
Write with Auto Precharge to Read Command Interval (Different bank)
CK
Command
WRIT A
READ
BA
Din
Dout
L
DQMB
in A0
bank3
Read
out B1
Pr
bank0
Write A
out B0
Note: Internal auto-precharge starts at the timing indicated by "
out B2
out B3
CE Latency = 4
Burst Length = 4
".
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet No. E0112H10
47
HB52R329E22-F
Read command to Precharge command interval (same bank):
EO
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after
the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the
precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be
assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 3, Burst Length = 4
L
CK
READ
Command
Dout
PRE/PALL
out A0
out A1
CK
Command
READ
out A3
Pr
CL=3
CE Latency = 4, Burst Length = 4
out A2
l EP = -2 cycle
PRE/PALL
uc
od
Dout
out A0
CL=4
out A1
out A2
out A3
l EP = -3 cycle
t
Data Sheet No. E0112H10
48
HB52R329E22-F
READ to PRECHARGE Command Interval (same bank): To stop output data
EO
CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 3
L
CE Latency = 4, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
PRE/PALL
Pr
Dout
READ
out A0
High-Z
lHZP = 4
t
uc
od
Data Sheet No. E0112H10
49
HB52R329E22-F
EO
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d
for the same bank as the write command that preceded it, the minimum interval between the two commands is 1
cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQMB
for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank):
Burst Length = 4 (To stop write operation)
CK
DQMB
Din
WRIT
PRE/PALL
L
Command
tDPL
Pr
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
Burst Length = 4 (To write all data)
CK
Command
PRE/PALL
WRIT
DQMB
Din
uc
od
tDPL
in A0
in A1
in A2
in A3
tDPL
t
Data Sheet No. E0112H10
50
HB52R329E22-F
Bank active command interval:
EO
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank Active to Bank Active for Same Bank
CK
Command
ACTV
ACTV
Address
ROW
ROW
L
BA
t RC
Bank 0
Active
Bank 0
Active
Pr
2. In the case of different bank-active commands: The interval between the two bank-active commands must
be no less than tRRD.
Bank Active to Bank Active for Different Bank
CK
Address
ACTV
ACTV
ROW:0
ROW:1
BA
t RRD
Bank 0
Active
uc
od
Command
Bank 3
Active
t
Data Sheet No. E0112H10
51
HB52R329E22-F
EO
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and
executing a bank-active command must be no less than lRSA .
CK
Command
Address
MRS
ACTV
CODE
BS & ROW
L
I RSA
Mode
Register Set
Bank
Active
DQMB Control
Pr
The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.
Re adin g: Whe n data is re ad, the output buff er ca n be contr olle d by DQMB . B y setting DQMB to Low, the
output buff er bec omes Low- Z, ena bling data output. B y setting DQMB to High, the output buff er bec omes
High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency
of DQMB during reading is 3 clocks.
t
uc
od
Writ in g: Input data ca n be maske d by DQMB . B y setting DQMB to Low, data ca n be wr itten. In addition,
when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of
DQMB during writing is 1 clock.
Data Sheet No. E0112H10
52
HB52R329E22-F
Reading
EO
CK
DQMB
Dout
High-Z
out 0
out 1
out 3
lDOD = 3 Latency
L
Writing
CK
;
;;
Pr
DQMB
Din
in 0
in 1
in 3
l DID = 1 Latency
t
uc
od
Data Sheet No. E0112H10
53
HB52R329E22-F
Refresh
EO
Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW
addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64
ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter
auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required.
L
S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held
Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter mina te d by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all
refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after exiting
from self-refresh mode.
Pr
Others
Powe r- down mod e: The S DRA M module ente rs powe r-dow n mode whe n C KE goes Low in the ID LE state.
In powe r down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down
mode continues while C KE is held Low. In addition, by setting C KE to High, the S DRA M module exits fr om
the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not
performed.
uc
od
Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M
module ente rs cloc k suspend mode. Dur ing cloc k suspend mode, exte rnal input signals ar e ignore d and the
interna l state is maintained. Whe n C KE is drive n High, the S DRA M module ter mina te s cloc k suspend mode,
and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high before
power up, the large current flows from these pins to VCC through the diodes.
t
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF).
S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping
DQM, DQMU /D QML to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ
bus contention on memory system formed with a number of device.
Data Sheet No. E0112H10
54
HB52R329E22-F
EO
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF).
S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping
DQMB to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus conte ntion
on memory system formed with a number of device.
S tabilizat ion time : The P LL re quires a stabiliz ation time to ac hieve phase lock of the fe edba ck signal to the
re fe renc e signal. This stabiliz ation time is re quired following powe r-up. S o this S DRA M module nee ds
dammy cycle for 50 µs after power-up.
Initialization sequence
Power up sequence
CKE, DQMB
200 µs
L
VCC
100 µs
0V
Low
Low
S, DQ
Low
Pr
CK
Power stabilize
t
uc
od
Data Sheet No. E0112H10
55
HB52R329E22-F
Timing Waveforms
EO
;;;;;;;
;;;;;;; ;
Read Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
RP
;
;
;;;
;
;;;
;
;
; ;;
t
t RCD
t CS t CH
L
S
t CS t CH
RE
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
BA
t AS t AH
A10
t AS t AH
Pr
W
t AS t AH
t AS t AH
t AS t AH
t AS t AH
Address
t CH
DQMB
Din
uc
od
t CS
t AC
Dout
t AC
Bank 0
Active
t CS t CH
t CS t CH
Bank 0
Read
t LZ
t OH
t AC
t OH
t AC
t OH
Bank 0
Precharge
t HZ
t OH
CE latency = 3
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet No. E0112H10
56
;
;
;
;;;;;;
HB52R329E22-F
Write Cycle
EO
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t RCD
t CS t CH
t RP
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
;;;
;
;
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
RE
L
t CS t CH
CE
t CS t CH
W
t AS t AH
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t CS t CH
t AS t AH
BA
Pr
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
DQMB
t AS t AH
t CH
t DH t DS t DH t DS
t DH
uc
od
t DS t DH tDS
Din
t AS t AH
t AS t AH
t DPL
Dout
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
CE latency = 3
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet No. E0112H10
57
;
;;;;;;;;
;;;
HB52R329E22-F
EO
;
;
;
;;;;;;;;;;;;;;;;
;; ; ;;;;;;;;;
;;;;;;
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CK
VIH
CKE
S
RE
CE
W
BA
DQMB
Dout
Din
code R: b
l RSA
l RP
Precharge
If needed
1
2
3
4
5
CKE
VIH
High-Z
6
7
8
9
10
RE
CE
W
BA
R:a
C:a
R:b
C:b
Din
CKE
a
a+1 a+2 a+3
12
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
VIH
14
15
16
b’+3
l RCD = 3
CE latency = 4
Burst length = 4
IH = V IL or V
17
18
19
20
21
Read cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
b
C:b"
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Write cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
S
CE
W
BA
R:a
C:a
R:b
C:b
C:b'
DQMB
C:b"
High-Z
Dout
a
Bank 0
Active
Bank 0
Write
a+1 a+2 a+3
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
Data Sheet No. E0112H10
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
t
Din
58
13
b’+2
High-Z
RE
Address
11
C:b'
DQMB
Dout
b’+1
uc
od
S
Address
b’
Output mask
Bank 3
Read
Pr
0
CK
b+3
b
l RCD
Mode
Bank 3
register Active
Set
Read Cycle/Write Cycle
C: b’
C: b
;
valid
L
Address
;
;;;;;;
;
;
HB52R329E22-F
Read/Single Write Cycle
;
; ;;
;
;
;
;
EO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a' C:a
DQMB
a
Bank 0
Active
CKE
L
Din
Dout
VIH
S
Bank 0
Read
a
a+1 a+2 a+3
Bank 3
Active
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
RE
W
BA
Address
R:a
C:a
DQMB
Pr
CE
R:b
C:a
C:b C:c
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
a+1
b
c
a+3
Bank 0
Write
Bank 3
Active
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
uc
od
Read/Single write
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
t
Data Sheet No. E0112H10
59
HB52R329E22-F
Read/Burst Write Cycle
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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0
CK
CKE
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a'
DQMB
a
Bank 0
Active
CKE
L
Din
Dout
VIH
S
Bank 0
Read
Bank 3
Active
a
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 0
Precharge
Bank 0
Write
Bank 3
Precharge
RE
W
BA
Address
R:a
C:a
DQMB
Pr
CE
R:b
C:a
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
a+1
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 3
Active
Bank 0
Precharge
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Read/Burst write
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
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Data Sheet No. E0112H10
60
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HB52R329E22-F
Full Page Read/Write Cycle
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CK
CKE
VIH
S
RE
CE
W
BA
Address
R:a
DQMB
Dout
Din
VIH
S
RE
CE
W
BA
Address
R:b
Bank 0
Read
a
a+1
a+2
High-Z
Bank 3
Active
Burst stop
Bank 3
Precharge
L
CKE
Bank 0
Active
C:a
Read cycle
RE-CE delay = 3
CE latency = 4
Burst length = full page
= VIH or VIL
R:a
C:a
R:b
Pr
DQMB
Write cycle
RE-CE delay = 3
CE latency = 4
Burst length = full page
= VIH or VIL
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1
Bank 3
Active
a+2
a+3
a+4
a+5
Burst stop
Bank 3
Precharge
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Data Sheet No. E0112H10
61
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HB52R329E22-F
Auto Refresh Cycle
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
a
a+1
CK
CKE
VIH
S
RE
CE
W
BA
Address
Din
Dout
L
DQMB
Auto Refresh
tRC
Active
Bank 0
Auto Refresh
Read
Bank 0
Pr
Self Refresh Cycle
CK
Refresh cycle and
Read cycle
RE-CE delay = 2
CE latency = 4
Burst length = 4
= VIH or VIL
l SREX
CKE Low
CKE
RE
CE
W
BA
A10=1
DQMB
Din
uc
od
S
Address
High-Z
t RC
t RP
Precharge
If needed
C:a
R:a
A10=1
High-Z
Dout
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
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Data Sheet No. E0112H10
62
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HB52R329E22-F
Clock Suspend Mode
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t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
CK
CKE
RE
CE
W
BA
R:a
C:a
R:b
C:b
DQMB
L
Dout
Din
Bank0 Active clock
Active suspend start
CKE
S
RE
Active clock Bank0
suspend end Read
Bank3
Active
a
a+1 a+2
a+3
High-Z
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
Address
Pr
W
C:a R:b
R:a
DQMB
C:b
High-Z
Dout
a
Din
Bank0
Active
Active clock
suspend start
19
20
Active clock Bank0 Bank3
supend end Write Active
b
b+1 b+2 b+3
Earliest Bank3
Precharge
Write cycle
RE-CE delay = 2
CE latency = 3
Burst length = 4
= VIH or VIL
CE
BA
18
Read cycle
RE-CE delay = 2
CE latency = 3
Burst length = 4
= VIH or VIL
S
Address
17
a+1 a+2
Write suspend
start
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
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Data Sheet No. E0112H10
63
HB52R329E22-F
Power Down Mode
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CK
CKE Low
CKE
S
RE
CE
L
W
BA
Address
R: a
A10=1
DQMB
Pr
Din
High-Z
Dout
tRP
Precharge command
If needed
Power down entry
Power down
mode exit
Active Bank 0
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Initialization Sequence
Power down cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
0
1
2
3
4
5
6
CK
CKE
VIH
S
RE
CE
W
DQMB
8
9
VIH
48
49
50
51
53
52
54
55
Valid
High-Z
DQ
t RP
t RC
Auto Refresh
t RSA
tRC
Auto Refresh
Data Sheet No. E0112H10
Mode register
Set
Bank active
If needed
t
All banks
Precharge
64
10
code
valid
Address
7
HB52R329E22-F
Physical Outline
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Unit: mm
inch
Front side
4.80
0.189
127.35
5.014
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Component area
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(Front)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1
84
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
L
C
11.43
8.89
0.350
0.450
B
4.00 min
0.157 min
3.00
0.118
3.00
0.118
133.37
5.251
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A
36.83
1.450
1.27 ± 0.10
0.050 ± 0.004
54.61
2.150
Detail C
3.125 ± 0.125
0.123 ± 0.005
0.25 max
0.010 max
3.175
0.125
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
4.175
0.164
3.125 ± 0.125
0.123 ± 0.005
85
2.54 min
0.100 min
168
1.00 ± 0.05
0.039 ± 0.002
Detail B
1.27
0.050
uc
od
Detail A
4.00
0.157
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Component area
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(Back)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38.10
1.500
Pr
2 – φ 3.00
2 – φ 0.118
17.78
0.700
Back side
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
Note: Tolerance on all dimensions ± 0.15/0.006 unless otherwise specified.
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Data Sheet No. E0112H10
65
HB52R329E22-F
Cautions
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1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third
party’s patent, copyright, trademark, or other intellectual property rights for information contained in this
document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights,
including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when
used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other
consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
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Data Sheet No. E0112H10
66