XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR OCTOBER 2007 REV. 1.0.1 GENERAL DESCRIPTION attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/ mapper device. When the SDEXT is de-asserted by the optical module or when internal DLOS is asserted, the receive serial data output will be forced to a logic zero state for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the SDEXT becomes active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream. Figure 1 shows the block diagram of the XRT91L34. The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The device internally monitors Loss of Lock (LOL) conditions and automatically mutes recovered data upon Loss of Signal (LOS) conditions. CLOCK AND DATA RECOVERY OVERVIEW The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the LVDS or Differential LVPECL receiver and generates a clock that is the same frequency as the incoming data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. All four channels share a single 77.76MHz or 19.44MHz reference clock. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL FIGURE 1. BLOCK DIAGRAM OF XRT91L34 TEST RESET DLOSDIS /SDI OUTCFG XRT91L34 HOST /HW 0 CDRREFSEL DLOSDIS SDI REFCLKP Global Control Block 1 Serial Proccesor INT 19.44 / 77.76 MHz REFCLKN TTLREFCLK Interface CS SCLK SDO RXDI0P RXDI0N LVDS/LVPECL LEVEL SELECT RCLKDIS0 LVDS/LVPECL Output Drivers LVDS/LVPECL Input Drivers RXDATAIN 100 RX LOOP FILTER CDR STS-12/3/1 or STM-4/1/0 Clock and Data Recovery RECVDDATAOUT RXDO0P 0 RXDO0N 1 RECVDCLKOUT RXCLKO0P 0 RXCLKO0N 1 HOST MODE ONLY CDRDIS0 DATA0RATE1 Channel Control Block LOL0 DLOSDIS DLOS DATA0RATE0 SDEXT0 POL0 Channel 0 Channel 1 Channel 2 Channel 3 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 APPLICATIONS • SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and Switch/Routers • DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment FEATURES • Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications • Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, or 51.84 Mbps. • Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions • Optional flexibility to configure for LVDS or Differential LVPECL High Speed I/O Interface • Internal 100Ω termination for the high speed LVDS/Differential LVPECL inputs included • Utilizes reference clock frequency of either 19.44 MHz or 77.76 MHz • Host mode serial microprocessor interface simplifies monitor and control, including LOS monitoring • Diagnostics features include LOS monitoring in Host Mode and automatic recovered data mute upon LOS • Loss of Lock Detect output for each channel • Permits mixed data rate configuration of the four channels • Independent power down control of unused channels for lower power operation • Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications. • Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and JESD 8-B LVTTL and LVCMOS standard. • Operates with dual power supply of 1.8V core and 3.3V IO supply • 90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation • Package: 14 x 14 x 1.4 mm 128-pin LQFP • RoHS Compliant Lead-Free package availability • ESD greater than 2kV on all pins 2 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 n/c SDEXT0 POL0 SDEXT1 POL1 AVDD1.8 HOST/HW GND TTLREFCLK CDRREFSEL REFCLKN REFCLKP DATA0RATE0 DATA0RATE1 DATA1RATE0 DATA1RATE1 DVDD1.8 GND GND CAP0P CAP0N CDRDIS0 CDRDIS1 AVDD1.8 AVDD1.8 CAP1P CAP1N GND GND LOL1 LOL0 n/c FIGURE 2. 128 LQFP PIN OUT OF THE XRT91L34 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 XRT91L34 VDD_IO VDD_IO RXDO0P RXDO0N GND_IO GND_IO RXCLKO0P RXCLKO0N VDD_IO VDD_IO RXDO1P RXDO1N GND_IO GND_IO RXCLKO1P RXCLKO1N RXCLKO2N RXCLKO2P GND_IO GND_IO RXDO2N RXDO2P VDD_IO VDD_IO RXCLKO3N RXCLKO3P GND_IO GND_IO RXDO3N RXDO3P VDD_IO VDD_IO SDEXT3 POL3 SDEXT2 POL2 SCLK CS DLOSDIS/SDI SDO INT AVDD1.8 GND OUTCFG TEST RESET DATA3RATE0 DATA3RATE1 DATA2RATE0 DATA2RATE1 DVDD1.8 GND CAP3P CAP3N CDRDIS3 CDRDIS2 AVDD1.8 AVDD1.8 CAP2P CAP2N GND GND LOL2 LOL3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 n/c n/c RXDI0P RXDI0N VDD_IO VDD_IO GND_IO GND_IO n/c n/c RXDI1P RXDI1N VDD_IO VDD_IO GND_IO GND_IO GND_IO GND_IO VDD_IO VDD_IO RXDI2N RXDI2P n/c n/c GND_IO GND_IO VDD_IO VDD_IO RXDI3N RXDI3P n/c n/c ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT91L34IV 128 Pin Lead LQFP -40°C to +85°C XRT91L34IV-F 128 Pin Lead-Free LQFP -40°C to +85°C 3 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE OF CONTENTS GENERAL DESCRIPTION .................................................................................................1 FIGURE 1. BLOCK DIAGRAM OF XRT91L34 ...................................................................................................................................... 1 APPLICATIONS ...........................................................................................................................................2 FEATURES ......................................................................................................................................................2 FIGURE 2. 128 LQFP PIN OUT OF THE XRT91L34 (TOP VIEW)........................................................................................................ 3 ORDERING INFORMATION.....................................................................................................................3 TABLE OF CONTENTS .......................................................................................................... IV PIN DESCRIPTIONS ..........................................................................................................6 HARDWARE CONTROL ....................................................................................................................................6 RECEIVER SECTION ........................................................................................................................................9 POWER AND GROUND ..................................................................................................................................10 SERIAL MICROPROCESSOR INTERFACE ......................................................................................................11 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12 1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12 1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12 TABLE 1: CHANNEL DATA RATE SELECTION .................................................................................................................................... 12 1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13 TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS)............................ 13 FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS ............................................................................................................................ 13 2.0 RECEIVE SECTION .............................................................................................................................14 2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14 FIGURE 4. RECEIVE SERIAL INPUT INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM....................................... 14 FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION ..................................... 15 2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15 TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 16 2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16 2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16 FIGURE 6. EXTERNAL LOOP FILTERS .............................................................................................................................................. 16 2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17 FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT ........................................................................................................................ 17 TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING ........................................................................................................... 17 2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18 FIGURE 8. MULTICHANNEL RECOVERED OUTPUT INTERFACE BLOCK ................................................................................................ 18 2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19 FIGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING ................................................................................................................... 19 TABLE 5: RECOVERED DATA OUTPUT TIMING (STS-12/STM-4 OPERATION).................................................................................... 19 TABLE 6: RECOVERED DATA OUTPUT TIMING (STS-3/STM-1 OPERATION)...................................................................................... 19 TABLE 7: RECOVERED DATA OUTPUT TIMING (STS-1/STM-0 OPERATION)...................................................................................... 19 3.0 JITTER PERFORMANCE ....................................................................................................................20 3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20 3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20 FIGURE 10. GR-253/G.783 JITTER TOLERANCE MASK ................................................................................................................... 20 FIGURE 11. XRT91L34 MEASURED JITTER TOLERANCE AT 51.84 MBPS STS-1/STM-0 .................................................................. 20 FIGURE 12. XRT91L34 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1 ................................................................ 21 FIGURE 13. XRT91L34 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4 .............................................................. 21 3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22 FIGURE 14. XRT91L34 MEASURED JITTER TRANSFER AT 51.84 MBPS STS-1/STM-0 .................................................................... 22 FIGURE 15. XRT91L34 MEASURED JITTER TRANSFER AT 155.52 MBPS STS-3/STM-1 .................................................................. 22 FIGURE 16. XRT91L34 MEASURED JITTER TRANSFER AT 622.08 MBPS STS-12/STM-4 ................................................................ 23 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24 FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 24 4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24 FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 24 4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25 4.2.1 4.2.2 4.2.3 4.2.4 R/W (SCLK1) ............................................................................................................................................................... A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. X (DUMMY BIT SCLK8) .............................................................................................................................................. D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25 25 25 25 4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25 IV XRT91L34 REV. 1.0.1 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 5.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 26 TABLE 8: MICROPROCESSOR INTERFACE REGISTER MAP ................................................................................................................ 26 TABLE 9: MICROPROCESSOR INTERFACE REGISTER 0X00 BIT DESCRIPTION .................................................................................... 27 TABLE 10: MICROPROCESSOR INTERFACE REGISTER 0X01 BIT DESCRIPTION .................................................................................. 28 TABLE 11: MICROPROCESSOR INTERFACE REGISTER 0X02 BIT DESCRIPTION .................................................................................. 28 TABLE 12: MICROPROCESSOR INTERFACE REGISTER 0X03 BIT DESCRIPTION .................................................................................. 29 TABLE 13: MICROPROCESSOR INTERFACE REGISTER 0X04 BIT DESCRIPTION .................................................................................. 29 TABLE 14: MICROPROCESSOR INTERFACE REGISTER 0X05 BIT DESCRIPTION .................................................................................. 29 TABLE 15: MICROPROCESSOR INTERFACE REGISTER 0X08, 0X10, 0X18, 0X20 BIT DESCRIPTION .................................................... 30 TABLE 16: MICROPROCESSOR INTERFACE REGISTER 0X09, 0X11, 0X19, 0X21 BIT DESCRIPTION .................................................... 31 TABLE 17: MICROPROCESSOR INTERFACE REGISTER 0X0A, 0X12, 0X1A, 0X22 BIT DESCRIPTION ................................................... 32 6.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 33 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 33 TABLE 18: ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ........................................................................................... 33 TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS ............................................................................................ 33 TABLE 20: LVDS/DIFFERENTIAL LVPECL INPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................ 34 FIGURE 19. LVDS/DIFFERENTIAL LVPECL VOLTAGE PARAMETER CONVENTION ............................................................................. 35 TABLE 21: LVDS OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................................................. 36 TABLE 22: DIFFERENTIAL LVPECL OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS....................................................... 36 TABLE 23: LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ....................................................................................... 36 TABLE 24: ORDERING INFORMATION ............................................................................................................................................... 37 PACKAGE DIMENSIONS ................................................................................................ 37 TABLE 25: REVISION HISTORY ........................................................................................................................................................ 38 V XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 PIN DESCRIPTIONS HARDWARE CONTROL NAME LEVEL TYPE PIN DESCRIPTION RESET LVTTL, LVCMOS I 46 Master Reset Input Active "Low." When this pin is pulled "Low", the internal state machines and registers are set to their default state. "Low" = Master Hardware Reset "High" = Normal Operation This pin is provided with an internal pull-up. TEST LVTTL, LVCMOS I 45 Test Input Active "High." When this pin is pulled "High", the 91L34 internal state machines will enter into a factory test mode. "Low" = Normal Operation "High" = Factory Test Diagnostic Mode NOTE: This pin should be pulled Low for normal operation. This pin is provided with an internal pull-down. DATA0RATE[1:0] LVTTL, LVCMOS I 115, 116 Data Rate Selection Selects SONET/SDH reception speed rate for each of the four channels independently according to the logic below. DATA1RATE[1:0] LVTTL, LVCMOS I 113, 114 DATA2RATE[1:0] LVTTL, LVCMOS I 50, 49 0 0 STS-1/STM-0 51.84 Mbps DATA3RATE[1:0] LVTTL, LVCMOS I 48, 47 0 1 STS-3/STM-1 155.52 Mbps 1 0 STS-12/STM-4 622.08 Mbps 1 1 STS-12/STM-4 622.08 Mbps DATANRATE[1:0] DATA RATE NOTE: These pins have no function in Host Mode. These pins are provided with internal pull-down. 6 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 NAME LEVEL TYPE PIN DESCRIPTION CDRREFSEL LVTTL, LVCMOS I 119 Clock and Data Recovery Unit Reference Frequency Select Selects the Clock and Data Recovery Unit reference frequency on REFCLKP/N pins or TTLREFCLK pin based on the table below. "Low" = 77.76 MHz reference clock "High" = 19.44 MHz reference clock CDRREFSEL REFCLKP/N OR TTLREFCLK FREQUENCY 0 77.76 MHz 1 19.44 MHz CHANNEL 0 - 3 AVAILABLE DATA RATES STS-12/STM-4 622.08 Mbps STS-3/STM-1 155.52 Mbps STS-1/STM-0 51.84 Mbps NOTE: REFCLKP/N or TTLREFCLK input should be generated from a crystal oscillator which has a frequency accuracy better than 100ppm in order for the received data rate frequency to have the necessary accuracy required for SONET systems. NOTE: This pin has no function in Host Mode. This pin is provided with an internal pull-down. OUTCFG LVTTL, LVCMOS I 44 Output Configuration Globally selects recovered clock and data outputs to be LVDS or Differential LVPECL on all four channels based on table below. "Low" = LVDS Standard Output "High" = Differential LVPECL Standard Output OUTCFG Input Configuration Output Configuration 0 LVDS/ Differential LVPECL LVDS 1 LVDS/ Differential LVPECL Differential LVPECL This pin is provided with an internal pull-down. CDRDIS0 CDRDIS1 CDRDIS2 CDRDIS3 LVTTL, LVCMOS I 107 106 56 55 Clock and Data Recovery Unit Disable Active "High." Disables internal Clock and Data Recovery unit for respective channel. This enables lower power operation when channel is unused. "Low" = Internal CDR unit is Enabled "High" = Internal CDR unit is Disabled NOTE: These pins have no function in Host Mode. These pins are provided with internal pull-down. 7 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 NAME LEVEL TYPE PIN DESCRIPTION DLOSDIS /SDI LVTTL, LVCMOS I 39 DLOS (Digital Loss of Signal) Disable Hardware Mode Disables internal DLOS monitoring and automatic muting of RXDO[3:0]P/N recovered data output pins upon DLOS detection. DLOS is declared when the incoming data stream has no transition for more than 2.5µs. DLOS is cleared when transitions are detected within a 128µs interval sliding window. "Low" = Monitor & Mute recovered data upon DLOS declaration "High" = Disable internal DLOS monitoring This pin is provided with an internal pull-down. Host Mode This pin is functions as the microprocessor Serial Data Input. POL0 POL1 POL2 POL3 LVTTL, LVCMOS I 126 124 36 34 Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "Low" = SDEXT is active "Low." "High" = SDEXT is active "High." NOTE: These pins have no function in Host Mode. These pins are provided with internal pull-down. SDEXT0 SDEXT1 SDEXT2 SDEXT3 LVTTL, LVCMOS, I 127 125 35 33 Signal Detect Input from Optical Module When inactive, it will immediately declare a Loss of Signal (LOS) condition and assert LOS register bit and mute the activity of the RXDO[3:0]P/N serial data output on the respective channel. "Active" = Normal Operation "Inactive" = LOS Condition (SDEXT detects signal absence) These pins are provided with internal pull-down. REFCLKP REFCLKN LVDS, Diff LVPECL I 117 118 Reference Clock Input (77.76 MHz or 19.44 MHz) This differential reference clock input will accept either a 77.76 MHz or a 19.44 MHz LVDS/Differential LVPECL clock source. Pin CDRREFSEL determines the value used as the reference. See Pin CDRREFSEL for more details. REFCLKP/N inputs are internally biased to 1.2V via 15kΩ resistance. These pins are equipped with a 100Ω line-to-line internal termination. NOTE: In the event that TTLREFCLK LVTTL/LVCMOS input is used instead of these differential inputs for clock reference, the REFCLKP should be left unconnected and REFCLKN should be tied to GND. TTLREFCLK LVTTL, LVCMOS I 120 TTL Reference Clock Input (77.76 MHz or 19.44 MHz) This optional single-ended clock input reference can be used instead of the differential REFCLKP/N input. It will accept either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin CDRREFSEL determines the value used as the reference. See Pin CDRREFSEL for more details. NOTE: In the event that REFCLKP/N differential inputs are used instead of this LVTTL/LVCMOS input for clock reference, the TTLREFCLK should be tied to ground. This pin is provided with an internal pull-down. 8 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 RECEIVER SECTION NAME LEVEL TYPE PIN DESCRIPTION RXDI0P RXDI0N RXDI1P RXDI1N RXDI2P RXDI2N RXDI3P RXDI3N LVDS, Diff LVPECL I 3 4 11 12 22 21 30 29 Receive Serial Data Input The differential receive serial data stream of 622.08 Mbps STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 is applied to these differential input pins. These pins accept LVDS or Differential LVPECL input standard. These pins are internally biased to 1.2V via 15kΩ resistance and are equipped with a 100Ω line-to-line internal termination. RXDO0P RXDO0N RXDO1P RXDO1N RXDO2P RXDO2N RXDO3P RXDO3N LVDS, Diff LVPECL O 94 93 86 85 75 76 67 68 Recovered Serial Data Output 622.08 Mbps STS-12/STM-4 / 155.52 Mbps STS-3/STM-1 / 51.84 Mbps STS-1/STM-0 differential recovered serial data output that is updated simultaneously on the falling edge of the corresponding channel RXCLKO output. User selectable LVDS standard or Differential LVPECL standard output based on OUTCFG pin state. RXCLKO0P RXCLKO0N RXCLKO1P RXCLKO1N RXCLKO2P RXCLKO2N RXCLKO3P RXCLKO3N LVDS, Diff LVPECL O 90 89 82 81 79 80 71 72 Recovered Clock Output (622.08 MHz/ 155.52 MHz/ 51.84 MHz) 622.08 MHz STS-12/STM-4 / 155.52 MHz STS-3/STM-1 / 51.84 MHz STS-1/STM-0 differential clock output for the corresponding recovered data output RXDO[0:3]P/N. The recovered serial data output port will be updated on the falling edge of this clock. User selectable LVDS standard or Differential LVPECL standard output based on OUTCFG pin state. LOL0 LOL1 LOL2 LOL3 LVCMOS O 98 99 63 64 CDR LOL Detect Output This pin is used to monitor the lock condition of the PLL in the clock and data recovery unit of each channel. "Low" = CDR Locked "High" = CDR Out of Lock CAP0P CAP0N Analog - 109 108 CAP1P CAP1N Analog - 103 102 CAP2P CAP2N Analog - 59 60 CDR Non-polarized External Loop Filter Capacitors Mode of Operation: 1. STS12/STM4: CAP[0:3]P/N = 0.47µF ± 10% tolerance 2. STS3/STM1: CAP[0:3]P/N = 0.47µF ± 10% tolerance 3. STS1/STM0: CAP[0:3]P/N = 1.0µF ± 10% tolerance Use type X7R or X5R for improved stability over temperature. (Isolate from noise and place close to pin) CAP3P CAP3N Analog - 53 54 9 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 POWER AND GROUND NAME TYPE PIN DESCRIPTION AVDD1.8 PWR 42, 57, 58, 104, 105, 123 1.8V Analog Core Power Supply AVDD1.8 should be isolated from DVDD1.8 and 3.3V VDD_IO power supplies. For best results, use a ferrite bead along with an internal power plane separation. The AVDD1.8 power supply pins should have bypass capacitors to the nearest ground. DVDD1.8 PWR 51, 112 1.8V Digital Core Power Supply DVDD1.8 should be isolated from AVDD1.8 and 3.3V VDD_IO power supplies. For best results, use an internal power plane separation. The DVDD1.8 power supply pins should have bypass capacitors to the nearest ground. VDD_IO PWR 5, 6, 13, 14, 19, 20, 27, 28, 65, 66, 73, 74, 87, 88, 95, 96 3.3V Input/Output Bus Power Supply These pins require a 3.3V potential voltage for properly biasing the Differential LVDS/Differential LVPECL and LVCMOS/LVTTL input and output pins. VDD_IO should be isolated from the AVDD1.8 and DVDD1.8 Core power supplies. For best results, use a ferrite bead along with an internal power plane separation. The VDD_IO power supply pins should have bypass capacitors to the nearest ground. GND_IO GND 7, 8, 15, 16, 17, 18, 25, 26, 69, 70, 77, 78, 83, 84, 91, 92 Ground for 3.3V VDD Input/Output Power Supplies It is recommended that all ground pins of this device be tied together. GND GND 43, 52, 61, 62, 100, 101, 110, 111, 121 Power Supply and Thermal Ground It is recommended that all ground pins of this device be tied together. NC 1, 2, 9, 10, 23, 24, 31, 32, 97, 128 No Connect 10 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 SERIAL MICROPROCESSOR INTERFACE NAME LEVEL TYPE PIN DESCRIPTION HOST/HW LVTTL, LVCMOS I 122 Host or Hardware Mode Select Input The XRT91L34 offers two modes of operation for interfacing to the device. The Host mode uses a serial microprocessor interface for programming individual registers. The Hardware mode is controlled by the state of the hardware pins set by the user. When left unconnected, by default, the device is configured in the Hardware mode. "Low" = Hardware Mode "High" = Host Mode This pin is provided with an internal pull-down. CS LVTTL, LVCMOS I 38 Chip Select Input (Host Mode) Active "Low" signal. This signal enables the serial microprocessor interface by pulling chip select "Low". The serial microprocessor is disabled when the chip select signal returns "High". NOTES: 1. The serial microprocessor interface does not support burst mode. Chip Select must be de-asserted after each operation cycle. 2. Chip Select is only active in Host Mode. This pin is provided with an internal pull-up. SCLK LVTTL, LVCMOS I 37 Serial Clock Input (Host Mode Only) Once CS is pulled "Low", the serial microprocessor interface requires 16 clock cycles for a complete Read or Write operation. Serial Clock Input is only active in Host Mode. This pin is provided with an internal pull-down. DLOSDIS /SDI LVTTL, LVCMOS I 39 Serial Data Input (Host Mode Only) When CS is pulled "Low", the serial data input is sampled on the rising edge of SCLK. Serial Data Input is only active in Host Mode. This pin is provided with an internal pull-down. Hardware Mode This pin is functions as the DLOSDIS control pin. SDO LVCMOS O 40 Serial Data Output (Host Mode Only) If a Read function is initiated, the serial data output is updated on the falling edge of SCLK8 through SCLK15, with the LSB (D0) updated first. This enables the data to be sampled on the rising edge of SCLK9 through SCLK16. Serial Data Output is only active in Host Mode. INT LVCMOS O 41 Interrupt Output (Host Mode Only) Active "Low" signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". Interrupt Output is only active in Host Mode. NOTE: This open-drain output pin requires an external pull-up resistor. 11 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 1.0 FUNCTIONAL DESCRIPTION The XRT91L34 Quad Channel CDR is designed to operate with a multichannel SONET Framer/ASIC device and provide a high-speed serial clock and data recovery interface to optical networks. The CDR receives differential NRZ serial bit stream running at STS-12/STM-4 or STS-3/STM-1 or STS-1/STM-0, and outputs recovered serial clock and data via differential LVDS/LVPECL drivers. It implements four independently configurable receive clock and data recovery (CDR) units and a LOL and LOS detection circuit (Host Mode Only) for each channel. The CDR is used to provide the front end component of SONET equipment. 1.1 Hardware Mode vs. Host Mode Functional control of the receiver can be configured by using either Host mode or Hardware mode. Hardware mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected. The receiver functionality is then controlled by the hardware pins described in the Hardware Pin Descriptions. Host mode is selected by pulling HOST/HW "High". In Host mode the functionality is controlled by programming internal R/W registers using the Serial Microprocessor interface. Host mode offers functions not available in Hardware mode, such as Loss of Signal Monitoring, Interrupt Generation and Disabling of the recovered clock output. 1.2 STS-12/STM-4 and STS-3/STM-1 and STS-1/STM-0 Mode of Operation The data rate of each receiver channel can be configured by using the appropriate signal level on the DATAnRATE1:0] pins (where n = channel 0, 1, 2, or 3) as shown in Table 1. TABLE 1: CHANNEL DATA RATE SELECTION DATA RATE SELECTED FOR DATANRATE[1:0] CHANNEL N 0 0 STS-1/STM-0 51.84 Mbps 0 1 STS-3/STM-1 155.52 Mbps 1 0 STS-12/STM-4 622.08 Mbps 1 1 STS-12/STM-4 622.08 Mbps NOTE: n denotes channel number. 12 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 1.3 Reference Clock Input The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP/N or a Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N or TTLREFCLK should be generated from a source which has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to have the necessary accuracy required for SONET systems. The reference clock can be provided with one of two frequencies chosen by CDRREFSEL. The reference frequency options for the XRT91L34 are listed in Table 2. Figure 3 illustrate the reference clock design options. TABLE 2: CDR REFERENCE FREQUENCY OPTIONS (LVDS/ DIFF LVPECL OR SINGLE-ENDED LVTTL/LVCMOS) REFCLKP/N OR TTLREFCLK CDRREFSEL FREQUENCY 0 77.76 MHz 1 19.44 MHz CHANNEL 0 - 3 AVAILABLE DATA RATES STS-1/STM-0 51.84 Mbps STS-3/STM-1 155.52 Mbps STS-12/STM-4 622.08 Mbps FIGURE 3. REFERENCE CLOCK DESIGN OPTIONS Single-Ended LVTTL/LVCMOS Reference Clock Option Differential LVPECL or LVDS Reference Clock Option REFCLKP and REFCLKN pins internally biased and terminated with 100 Ohm line-to-line Differential Clock Source 77.76/19.44 MHz REFCLKP REFCLKN Leave REFCLKP unconnected and tie REFCLKN pin to GND 100 VBB 1.2 REFCLKP REFCLKN 100 VBB 1.2 130 Ohm Resistors for LVPECL Remove for LVDS Internal REFCLK Internal REFCLK TTLREFCLK TTLREFCLK Tie unused TTLREFCLK input pin to GND Single Ended Clock Source 77.76/19.44 MHz XRT91L34 13 XRT91L34 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 2.0 RECEIVE SECTION The receive section of XRT91L34 includes four differential input buffers RXDI[3:0]P/N, followed by clock and data recovery units (CDR) and recovered serial data and clock differential output drivers. The receiver accepts the high speed Non-Return to Zero (NRZ) serial data at 622.08/155.52/51.84 Mbps through the input interfaces RXDI[3:0]P/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming data stream. The recovered serial data is presented to the RXDO[3:0]P/N differential output driver interface. The high-speed recovered clock RXCLKO[3:0]P/N, is used to synchronize the transfer of the RXDO[3:0]P/N data with the receive portion of a framer/mapper device. The recovered data RXDO[3:0]P/N and clock RXCLKO[3:0]P/N differential output driver interfaces are designed for ultimate flexibility by supporting either LVDS or Differential LVPECL protocol level. Upon initialization or loss of signal or loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock recovery phase-locked loop for proper operation. The included CDR blocks in the XRT91L34 can be individually disabled by asserting the CDRDIS[3:0] pins to permit the flexibility of powering down unused channels. 2.1 Receive Serial Input The receive serial inputs are applied to RXDI[3:0]P/N. The XRT91L34 includes internal termination, this has the advantage of reducing the number of external board components. The XRT91L34 terminates the receive inputs using 100Ω line-to-line method of termination. Differential LVPECL operation of receive inputs can be supported, provided each optical module Differential LVPECL output pin must have a 130Ω DC current path resistor to GND whether internally or externally. A simplified LVDS/Differential LVPECL DC coupling block diagram is shown in Figure 4. FIGURE 4. RECEIVE SERIAL INPUT INTERFACE USING LVDS/DIFF LVPECL DC COUPLING INTERNAL TERM Internal 100 Ohm line-to-line termination active on RXDI[3:0]P and RXDI[3:0]N pins LVDS or DIFF LVPECL Operation Internal 130 Ohm line to GND DC current path resistors required for Optical Module DIFF LVPECL Operation RXDI0P VBB1.2 100 RXDI0N Channel 0 Optical Module Optical Fiber RXDI1P XRT91L34 STS-12/3/1 or STM-4/1/0 Clock and Data Recovery VBB1.2 100 RXDI1N Channel 1 Optical Module Optical Fiber RXDI2P VBB1.2 100 RXDI2N Channel 2 Optical Module Optical Fiber RXDI3P VBB1.2 100 RXDI3N Channel 3 Optical Module Optical Fiber NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module. AC or DC coupling is largely specific to system design and optical module of choice. 14 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified Differential LVPECL AC coupling using external passive components block diagram is shown in Figure 5. FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION Internal 100 Ohm line-to-line termination active on RXDI[3:0]P and RXDI[3:0]N pins DIFF LVPECL A/C Coupling using External Passive Components Channel 0 RXDI0P VBB1.2 100 RXDI0N Channel 1 RXDI1P XRT91L34 STS-12/3/1 or STM-4/1/0 Clock and Data Recovery VBB1.2 100 RXDI1N Channel 2 Optical Fiber Optical Module RXDI2N Channel 3 RXDI3P VBB1.2 100 Optical Fiber Optical Module RXDI2P VBB1.2 100 Optical Fiber Optical Module Optical Fiber Optical Module RXDI3N 130 x 8 Install DC current path resistors as close to Optical Module LVPECL output driver pins NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module. 2.2 Receive Clock and Data Recovery The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential receiver and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the reference clock from REFCLKP/N or TTLREFCLK to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch to the local reference clock, declare a Loss of Lock and output a high level signal on the LOL output pin. Whenever a Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock (based on the local reference). When the SDEXT becomes active and internal DLOS is cleared and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source, the clock recovery PLL will switch back to the incoming receive serial data stream. Table 3 specifies the Clock and Data Recovery Unit performance characteristics. 15 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE NAME PARAMETER MIN MAX UNITS 40 60 % -100 +100 ppm REFDUTY Reference clock duty cycle REFTOL Reference clock frequency tolerance2 TOLJIT Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern 0.3 OCLKDUTY Clock output duty cycle 45 TYP 0.4 UI 55 % Jitter specification is defined using a 12kHz to 0.4/1.3/5MHz LP-HP single-pole filter. 1 These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms). 2 Required to meet SONET output frequency stability requirements. 2.2.1 Internal Clock and Data Recovery Disable Optionally, each of the four internal CDR unit can be disabled and powered down when the channel is not in use. Asserting the CDRDISn pin (where n = channel 0, 1, 2, or 3 ) "High" in Hardware Mode or setting CDRDISn bit (where n = channel 0, 1, 2, or 3 ) in Host Mode, disables the internal Clock and Data Recovery unit for that particular channel. 2.3 External Receive Loop Filter Capacitors For STS12/STM4 and STS3/STM1 operation, use 0.47µF (or greater) non-polarized external loop filter capacitors to achieve the required receiver jitter performance for each of the channels. For STS1/STM0 operation, use a minimum of 1.0µF non-polarized capacitors. If all 3 data rates STS12/STS3/STS1 are required in an application, then use 1uF loop filter capacitors. They must be well isolated to prohibit noise entering the CDR block and should be placed as close to the pins as possible. Figure 6 shows the pin connections and external loop filter components. These four non-polarized capacitors should be of +/- 10% tolerance. Use type X7R or X5R capacitors for improved stability over temperature. FIGURE 6. EXTERNAL LOOP FILTERS 0.47uF 0.47uF non-polarized non-polarized Channel 0 Loop Filter External Capacitor pin 108 pin 109 Channel 1 Loop Filter External Capacitor pin 103 pin 102 CAP0P CAP1P CAP0N Use 1.0uF non-polarized capacitors for STS1/STM0 Operation CAP1N .. .. 0.47uF non-polarized 0.47uF non-polarized Channel 2 Loop Filter External Capacitor pin 59 pin 60 Channel 3 Loop Filter External Capacitor pin 53 Pin 54 CAP2P CAP3P CAP2N 16 CAP3N XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 2.4 Internal Digital Loss of Signal and External Signal Detection XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection (SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the incoming data stream. If the incoming data stream has no transition for more than 2.5µs, Loss of Signal is declared. This LOS condition will be cleared when the circuit detects transitions in a 128µs interval sliding window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of Signal declaration and clearance criteria for specific applications. The external Signal Detect function is supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings. FIGURE 7. LOSS OF SIGNAL DECLARATION CIRCUIT DLOSDIS LOS Declaration and Recovered Data Mute (Internal) DLOS Detect POL (External) SDEXT TABLE 4: EXTERNAL LOS DECLARATION POLARITY SETTING SDEXT POL 0 0 0 1 1 1 0 1 INTERNAL SIGNAL DETECT LOS BIT STATE RXDO[3:0]P/N (HOST MODE ONLY) Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. Low Normal Operation Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. High LOS declared Muted Active Low. Optical signal presence indicated by SDEXT logic 0 input from optical module. High LOS declared Muted Active High. Optical signal presence indicated by SDEXT logic 1 input from optical module. Low Normal Operation 17 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 2.5 REV. 1.0.1 Multichannel Recovered Output Interface The recovered data RXDO[3:0]P/N differential output drivers along with the recovered clock RXCLKO[3:0]P/N differential output drivers can be configured for LVDS or Differential LVPECL standard operation. In addition, Host Mode operation permits each of the channelized recovered clock output to be independently disabled such as in repeater applications to save power. FIGURE 8. MULTICHANNEL RECOVERED OUTPUT INTERFACE BLOCK LVDS Operation OUTCFG = 0 RXDO0P RXDO0N Channel 0 100 SONET Framer/ ASIC RXDO1P XRT91L34 RXDO1N STS-12/3/1 or STM-4/1/0 Clock and Data Recovery Channel 1 100 RXDO2P RXDO2N Channel 2 100 Channel 3 100 Internal or External 100 Ohm line-to-line termination required on RXDO[3:0]P and RXDO[3:0]N pins on the SONET Framer/ASIC end RXDO3P RXDO3N RXCLKO[3:0]P and RXCLKO[3:0]N Clock Output pins terminated similarly OUTCFG = 1 VDDIO 120 x 8 Install terminators as close to SONET Framer/ ASIC pins LVPECL Operation RXDO0P Channel 0 RXDO0N SONET Framer/ ASIC RXDO1P XRT91L34 STS-12/3/1 or STM-4/1/0 Clock and Data Recovery Channel 1 RXDO1N RXDO2P Channel 2 RXDO2N RXDO3P Channel 3 RXDO3N RXCLKO[3:0]P and RXCLKO[3:0]N Clock Output pins terminated similarly 82 x 8 18 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 2.6 Differential Recovered Data Output Timing The differential recovered data and clock outputs operating at the STS-12/STM-4 or STS-3/STM-1 or STS-1/ STM-0 datarates will adhere to the data valid output timing shown in Figure 9 ,Table 5, Table 6, and Table 7. FIGURE 9. DIFFERENTIAL RECOVERED OUTPUT TIMING tRXCLKO RXCLKO[3:0]P/N RXDO[3:0]P/N D1 D2 D3 D4 D5 tRXDO_VALID TABLE 5: RECOVERED DATA OUTPUT TIMING (STS-12/STM-4 OPERATION) SYMBOL tRXCLKO tRXDO_VALID PARAMETER MIN Recovered high-speed output clock period Time the data is valid on RXDO[3:0]P/N before and after the rising edge of RXCLKO[3:0]P/N TYP MAX 1.608 UNITS ns 0.5 ns TABLE 6: RECOVERED DATA OUTPUT TIMING (STS-3/STM-1 OPERATION) SYMBOL tRXCLKO tRXDO_VALID PARAMETER MIN Recovered high-speed output clock period Time the data is valid on RXDO[3:0]P/N before and after the rising edge of RXCLKO[3:0]P/N TYP MAX 6.43 UNITS ns 2.8 ns TABLE 7: RECOVERED DATA OUTPUT TIMING (STS-1/STM-0 OPERATION) SYMBOL tRXCLKO tRXDO_VALID PARAMETER MIN Recovered high-speed output clock period Time the data is valid on RXDO[3:0]P/N before and after the rising edge of RXCLKO[3:0]P/N 19 TYP 19.29 8.3 MAX UNITS ns ns XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 3.0 JITTER PERFORMANCE 3.1 SONET Jitter Requirements SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of each of these types of jitter are given below. 3.1.1 Rx Jitter Tolerance: OC-1/STM-0, OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter applied according to the mask of Figure 10, with the corresponding parameters specified in the figure. FIGURE 10. GR-253/G.783 JITTER TOLERANCE MASK A3 slope= -20dB/decade Input Jitter Amplitude (UIpp) A2 slope= -20dB/decade A1 f0 f1 f2 f4 f3 Jitter Frequency (Hz) OC-N F0 (HZ) F1 (HZ) F2 (HZ) F3 (HZ) F4 (HZ) A1 (UIPP) A2 (UIPP) A3 (UIPP) OC1/STS11 STM-X LEVEL STM0 10 30 300 2K 20K 0.15 1.5 15 OC3/STS33 STM1 10 30 300 6.5K 65K 0.15 1.5 15 OC12/STS12 12 STM4 10 30 300 25K 250K 0.15 1.5 15 FIGURE 11. XRT91L34 MEASURED JITTER TOLERANCE AT 51.84 MBPS STS-1/STM-0 Jitte r T ole rance , G R -253, O C -1 (51 M bps) Mas k Jitter Toleranc e Amplitude (UI) 1 0 0 .0 0 1 0 .0 0 1 .0 0 0 .1 0 0 .0 1 1 E+0 1 E+1 1E+2 1 E+3 1 E+4 Fre que nc y (Hz) 20 1 E+5 1 E+6 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR FIGURE 12. XRT91L34 MEASURED JITTER TOLERANCE AT 155.52 MBPS STS-3/STM-1 Jitter Tolerance, GR-253, OC-3 (155 Mbps) Jitter Tolerance Mask 100.00 Amplitude (UI) 10.00 1.00 0.10 0.01 1E+0 1E+1 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 1E+7 FIGURE 13. XRT91L34 MEASURED JITTER TOLERANCE AT 622.08 MBPS STS-12/STM-4 Jitte r T ole rance , G R -253, O C -12 (622 M bps) Jitter Toler anc e Mas k 1 0 0 0 .0 0 1 0 0 .0 0 Amplitude (UI) REV. 1.0.1 1 0 .0 0 1 .0 0 0 .1 0 0 .0 1 1 E+ 0 1 E +1 1 E+2 1 E +3 1 E +4 Fre que nc y (Hz) 21 1 E+5 1 E+6 1 E +7 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 3.1.2 REV. 1.0.1 Rx Jitter Transfer Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. It displays the ability of the component unit to attenuate jitter at the specified injected jitter frequencies. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low bandwidth loop. The XRT91L34 meets the latest jitter transfer characteristics as shown in the Figure 14, Figure 15, and Figure 16. The XRT91L34 complies with STS-12/3/1 and STM-4/1/0 jitter transfer masks set forth by Bellcore GR-253 Core section 5.6.2.1 and ITUT G.783 section 15.1.3 as defined in G.825. FIGURE 14. XRT91L34 MEASURED JITTER TRANSFER AT 51.84 MBPS STS-1/STM-0 Jitter Transfer, GR253H, OC-1 (52Mbps) Mask 5 Jitter Transfer 0 Gain (dB) -5 -10 -15 -20 -25 -30 1E+1 1E+2 1E+3 1E+4 Frequuency (Hz) 1E+5 1E+6 FIGURE 15. XRT91L34 MEASURED JITTER TRANSFER AT 155.52 MBPS STS-3/STM-1 Jitter Transfer, GR253H, OC-3 (155 Mbps) Mask Jitter Transf er 5 0 Gain (dB) -5 -10 -15 -20 -25 -30 1E+1 1E+2 1E+3 1E+4 1E+5 Frequuency (Hz) 22 1E+6 1E+7 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR FIGURE 16. XRT91L34 MEASURED JITTER TRANSFER AT 622.08 MBPS STS-12/STM-4 Jitte r T ransfe r, G R253H , O C -12 (622 M bps) Mas k Jitter Trans f er 5 0 -5 Gain (dB) REV. 1.0.1 -10 -15 -20 -25 -30 1E+1 1E+2 1E+3 1E+4 1E+5 Frequuency (Hz) 23 1E+6 1E+7 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the device. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor the device via an interrupt pin, and reset the device to its default configuration by pulling reset "Low" for more than 10ns. A simplified block diagram of the Serial Microprocessor Interface is shown in Figure 17. FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE SDI SDO Data out Shift Register SCLK Address bus Data bus CS INT Register Bank Status bits and error Flags from CDRs Controls to CDRs RESET 4.1 SERIAL TIMING INFORMATION The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor Interface samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor Interface is shown in Figure 18. FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE CS 25nS 50nS SCLK 1 SDI R/W SDO 2 A0 3 A1 4 A2 5 A3 6 A4 7 9 8 A5 X High-Z 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 High-Z NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active "Low") must be de-asserted at the end of each write or read operation. 24 XRT91L34 REV. 1.0.1 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR 4.2 16-BIT SERIAL DATA INPUT DESCRITPTION The serial data input is sampled on the rising edge of SCLK. For read operations, the SDO signal is updated on the falling edge of SCLK. The serial data must be applied to the serial port LSB first. The 16 bits of serial data are described below. 4.2.1 R/W (SCLK1) The first serial bit applied to the device SDI pin determines whether a Read or Write operation is desired. If the R/W bit is set to “0”, the serial port is configured for a Write operation. If the R/W bit is set to “1”, the serial port is configured for a Read operation. 4.2.2 A[5:0] (SCLK2 - SCLK7) The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0 (LSB) must be sent to the SDI pin first followed by A1 and so forth until all 6 address bits have been sampled by SCLK. 4.2.3 X (Dummy Bit SCLK8) The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold either “0” or “1” during both Read and Write operations. 4.2.4 D[7:0] (SCLK9 - SCLK16) The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the address bits. D0 (LSB) must be sent to the SDI pin first followed by D1 and so forth until all 8 data bits have been sampled by SCLK. Once 16 SCLK cycles have been complete, the data is held until CS is pulled “High” whereby, the serial port latches the data into the selected internal register. 4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION When R/W is set to “1” (Read operation) the serial data output is updated on the falling edge of SCLK8 SCLK16, D0 (LSB) is provided at the SDO pin on the falling edge of SCLK8, followed by D1 and so forth until all 8 data bits have been updated after which the SDO output pin returns to a high impedance state until the next read operation. 25 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 5.0 REGISTER MAP AND BIT DESCRIPTIONS The XRT91L34 consists of 6 Common Registers including the Device ID and Revision ID registers and 12 channelized registers. Table 8 below presents the overall Register Map. TABLE 8: MICROPROCESSOR INTERFACE REGISTER MAP REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 Control Registers (0x00 - 0x22) 0 0x00 R/W Reserved Reserved Reserved DLOSDIS Reserved MINT_EN CDRREFSEL SWRST 1 0x01 RO Reserved Reserved Reserved Reserved INTS3 INTS2 INTS1 INTS0 2 0x02 RO Device ID MSB (See Bit Description) 3 0x03 RO Device ID LSB (See Bit Description) 4 0x04 RO Revision ID MSB (Register value is 0x00) 5 0x05 RO Revision ID LSB (See Bit Description) 6 0x06 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 7 0x07 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RCLKDIS0 CDRDIS0 POL0 Reserved Reserved LOL0_IE LOS0_IE Reserved Reserved LOL0_IS LOS0_IS Reserved RCLKDIS1 CDRDIS1 POL1 Reserved Reserved LOL1_IE LOS1_IE Reserved Reserved LOL1_IS LOS1_IS Reserved RCLKDIS2 CDRDIS2 POL2 Reserved Reserved LOL2_IE LOS2_IE Reserved Reserved LOL2_IS LOS2_IS Reserved RCLKDIS3 CDRDIS3 POL3 Reserved Reserved LOL3_IE LOS3_IE Reserved Reserved LOL3_IS LOS3_IS CHANNEL 0 8 0x08 R/W Reserved Reserved 9 0x09 R/W Reserved Reserved 10 0x0A RO RUR Reserved Reserved 0x0B - 0x0F RO Reserved Reserved DATA0RATE1 DATA0RATE0 LOL0 LOS0 Reserved CHANNEL 1 16 0x10 R/W Reserved Reserved 17 0x11 R/W Reserved Reserved 18 0x12 RO RUR Reserved Reserved 0x13 - 0x17 RO Reserved Reserved DATA1RATE1 DATA1RATE0 LOL1 LOS1 Reserved CHANNEL 2 24 0x18 R/W Reserved Reserved 25 0x19 R/W Reserved Reserved 26 0x1A RO RUR Reserved Reserved 0x1B - 0x1F RO Reserved Reserved DATA2RATE1 DATA2RATE0 LOL2 LOS2 Reserved CHANNEL 3 32 0x20 R/W Reserved Reserved 33 0x21 R/W Reserved Reserved 34 0x22 RO RUR Reserved Reserved Reserved Reserved DATA3RATE1 DATA3RATE0 LOL3 LOS3 26 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 COMMON CONTROL REGISTERS TABLE 9: MICROPROCESSOR INTERFACE REGISTER 0X00 BIT DESCRIPTION GLOBAL CONTROL REGISTER (0X00) Register Type Default Value (HW Reset) This Register Bit is Not Used RO 0 Reserved This Register Bit is Not Used RO 0 D5 Reserved This Register Bit is Not Used RO 0 D4 DLOSDIS DLOS (Digital Loss of Signal) Disable This global bit is used to disable the channelized internal DLOS monitoring and automatic muting of RXDO[3:0]P/N recovered data output pins upon DLOS detection. "0" = Monitor & Mute recovered data upon LOS declaration "1" = Disable internal DLOS monitoring R/W 0 D3 Reserved This Register Bit is Not Used RO 0 D2 MINT_EN Master Interrupt Enable "0" = Disables Interrupt generation "1" = Enables Interrupt generation R/W 0 R/W 0 R/W 0 BIT NAME D7 Reserved D6 D1 D0 FUNCTION CDRREFSEL Clock and Data Recovery Unit Reference Frequency Select This bit is used to select the clock input reference. "0" = 77.76 MHz reference frequency support "1" = 19.44 MHz reference frequency support SWRST Software Reset A "0" to "1" transition will asynchronously reset the device and all register bit settings to their default state. This bit will automatically reset itself to "0". User does not have to write "0" to this bit to resume normal operation. "0" = Normal Operation "1" = Resets all registers to default values 27 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 10: MICROPROCESSOR INTERFACE REGISTER 0X01 BIT DESCRIPTION CHANNEL INTERRUPT STATUS REGISTER (0X01) Register Type Default Value (HW Reset) This Register Bit is Not Used RO 0 Reserved This Register Bit is Not Used RO 0 D5 Reserved This Register Bit is Not Used RO 0 D4 Reserved This Register Bit is Not Used RO 0 D3 INTS3 Channel 3 Interrupt Status This bit indicates an interrupt occuring in Channel 3. "0" = No Interrupt Generated "1" = Channel Interrupt Occurring RO 0 D2 INTS2 Channel 2 Interrupt Status This bit indicates an interrupt occuring in Channel 2. "0" = No Interrupt Generated "1" = Channel Interrupt Occurring RO 0 D1 INTS1 Channel 1 Interrupt Status This bit indicates an interrupt occuring in Channel 1. "0" = No Interrupt Generated "1" = Channel Interrupt Occurring RO 0 D0 INTS0 Channel 0 Interrupt Status This bit indicates an interrupt occuring in Channel 0. "0" = No Interrupt Generated "1" = Channel Interrupt Occurring RO 0 BIT NAME D7 Reserved D6 FUNCTION TABLE 11: MICROPROCESSOR INTERFACE REGISTER 0X02 BIT DESCRIPTION DEVICE "ID" REGISTER (0X02) BIT D7 D6 D5 D4 D3 D2 D1 D0 NAME FUNCTION Device "ID" The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the revision "ID", the device "ID" is used to enable software to identify MSB the silicon adding flexibility for system control and debug. 28 Register Type Default Value (HW reset) RO 1 0 0 0 0 1 0 0 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 12: MICROPROCESSOR INTERFACE REGISTER 0X03 BIT DESCRIPTION DEVICE "ID" REGISTER (0X03) BIT D7 D6 D5 D4 D3 D2 D1 D0 NAME FUNCTION Device "ID" The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the revision "ID", the device "ID" is used to enable software to identify LSB the silicon adding flexibility for system control and debug. Register Type Default Value (HW reset) RO 0 0 0 0 0 1 0 1 TABLE 13: MICROPROCESSOR INTERFACE REGISTER 0X04 BIT DESCRIPTION REVISION "ID" REGISTER (0X04) BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" MSB The revision "ID" of the XRT91L34 CDR is used to enable software to identify which revision of silicon is currently being tested. This MSB revision "ID" register will always contain the value 0x00h. Register Type Default Value (HW reset) RO 0 0 0 0 0 0 0 0 TABLE 14: MICROPROCESSOR INTERFACE REGISTER 0X05 BIT DESCRIPTION REVISION "ID" REGISTER (0X05) BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" LSB The revision "ID" of the XRT91L34 CDR is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon (Revision A) will be 0x01h. 29 Register Type Default Value (HW reset) RO This byte shows the revision of the device. XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 CHANNELIZED REGISTERS TABLE 15: MICROPROCESSOR INTERFACE REGISTER 0X08, 0X10, 0X18, 0X20 BIT DESCRIPTION CHANNEL CONTROL REGISTER (CH0 = 0X08, CH1 = 0X10, CH2 = 0X18, CH3 = 0X20) Register Type Default Value (HW reset) This Register Bit is Not Used RO 0 Reserved This Register Bit is Not Used RO 0 D5 Reserved This Register Bit is Not Used RO 0 D4 Reserved This Register Bit is Not Used RO 0 D3 Reserved This Register Bit is Not Used RO 0 D2 RCLKDISn Recovered Serial Clock Output Disable This bit is used to control the activity of the 622.08/155.52/51.84 MHz differential serial clock output. Tristating RXCLKOnP/N output reduces power consumption. "0" = RXCLKOnP/N output Enabled "1" = RXCLKOnP/N output Tristated R/W 0 D1 CDRDISn Clock and Data Recovery Unit Disable Disables Internal Clock and Data Recovery Unit. "0" = Internal CDR Unit is Enabled "1" = Internal CDR Unit is Disabled R/W 0 D0 POLn Polarity for SDEXT Input Controls the Signal Detect polarity convention of SDEXT. "0" = SDEXT is active "Low" "1" = SDEXT is active "High" R/W 0 BIT NAME D7 Reserved D6 FUNCTION NOTE: n denotes channel number. 30 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 16: MICROPROCESSOR INTERFACE REGISTER 0X09, 0X11, 0X19, 0X21 BIT DESCRIPTION CONFIGURATION AND INTERRUPT ENABLE CHANNEL REGISTER (CH0 = 0X09, CH1 = 0X11, CH2 = 0X19, CH3 = 0X21) BIT NAME D7 Reserved D6 Reserved D5 DATAnRATE1 D4 DATAnRATE0 Register Type Default Value (HW reset) This Register Bit is Not Used RO 0 This Register Bit is Not Used RO 0 Data Rate Selection Bit-1 and Bit-0 These bits selects SONET/SDH reception speed rate for each of the four channels independently according to the logic below. R/W 0 R/W 0 FUNCTION DATANRATE[1:0] DATA RATE 0 0 STS-1/STM-0 51.84 Mbps 0 1 STS-3/STM-1 155.52 Mbps 1 0 STS-12/STM-4 622.08 Mbps 1 1 STS-12/STM-4 622.08 Mbps D3 Reserved This Register Bit is Not Used RO 0 D2 Reserved This Register Bit is Not Used RO 0 D1 LOLn_IE Loss of Lock Interrupt Enable "0" = Masks the LOL interrupt generation "1" = Enables Interrupt generation R/W 0 D0 LOSn_IE Loss of Signal Interrupt Enable "0" = Masks the LOS interrupt generation "1" = Enables Interrupt generation R/W 0 NOTE: n denotes channel number. 31 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 17: MICROPROCESSOR INTERFACE REGISTER 0X0A, 0X12, 0X1A, 0X22 BIT DESCRIPTION INTERRUPT STATUS CONTROL REGISTER (CH0 = 0X0A, CH1 = 0X12, CH2 = 0X1A, CH3 = 0X22) Register Type Default Value (HW reset) This Register Bit is Not Used RO 0 This Register Bit is Not Used RO 0 LOLn Loss of Lock Detection The Loss of Lock Detect is used to indicate whether the CDR PLL is locked. "0" = CDR Locked "1" = CDR Out of Lock RO 0 D4 LOSn Loss of Signal The LOS indicates the Loss of Signal activity. "0" = No Alarm "1" = A LOS condition is present RO 0 D3 Reserved This Register Bit is Not Used RO 0 D2 Reserved This Register Bit is Not Used RO 0 D1 LOLn_IS Loss of Lock Interrupt Status An external interrupt will not occur unless the LOLn_IE interrupt enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and 0x21 for channels 0, 1, 2, and 3 respectively. "0" = No Change "1" = Change in CDR Lock Status Occurred RUR 0 D0 LOSn_IS Loss of Signal Interrupt Status An external interrupt will not occur unless the LOSn_IE interrupt enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and 0x21 for channels 0, 1, 2, and 3 respectively. "0" = No Change "1" = Change in LOS Status Occurred RUR 0 BIT NAME D7 Reserved D6 Reserved D5 FUNCTION NOTE: n denotes channel number. 32 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 6.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Air Thermal Resistance of LQFP Package.....ΘjA = 25°C/W Operating Temperature Range.................-40°C t o 85°C Case Thermal Resistance of LQFP Package.ΘjC = 4°C/W Case Temperature under bias..................-55°C to 125°C ESD Protection (HBM)..........................................>2000V Storage Temperature ...............................-65°C to 150°C TABLE 18: ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS SYMBOL TYPE PARAMETER MIN. VDD1.8 1.8V Core Power Supplies VDDIO TYP. MAX. UNITS -0.5 3.6 V 3.3V Input/Output Power Supplies -0.5 5.5 V LVDS DC logic signal input voltage -0.5 VDDIO +0.5 V LVPECL DC logic signal input voltage -0.5 VDDIO +0.5 V LVTTL/ DC logic signal input voltage LVCMOS -0.5 VDDIO +0.5 V LVDS DC logic signal output voltage -0.5 VDDIO +0.5 V LVPECL DC logic signal output voltage -0.5 VDDIO +0.5 V LVCMOS DC logic signal output voltage -0.5 VDDIO +0.5 V LVDS Input current -200 200 mA LVPECL Input current -200 200 mA LVTTL/ Input current LVCMOS -200 200 mA NOTE: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods will severely affect device reliability. TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS VDD1.8 Core Power Supply Voltage 1.710 1.8 1.890 V VDDIO I/O Power Supply Voltage 3.135 3.3 3.465 V CONDITIONS IDD1.8-OC1 1.8V 51.84Mbps Total Power Supply Current mA LVDS Mode IDD1.8-OC3 1.8V 155.52Mbps Total Power Supply Current mA LVDS Mode IDD1.8-OC12 1.8V 622.08Mbps Total Power Supply Current mA LVDS Mode IDD3.3-OC1 3.3V 51.84Mbps Total Power Supply Current mA LVDS Mode IDD3.3-OC3 3.3V 155.52Mbps Total Power Supply Current mA LVDS Mode 33 117 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS CONDITIONS IDD3.3-OC12 3.3V 622.08Mbps Total Power Supply Current 50 mA LVDS Mode IDD3.3-OC12 3.3V 622.08Mbps Total Power Supply Current 30 mA LVDS Mode RXCLKO disabled PDD-OC1 Total Power Consumption mW LVDS Mode PDD-OC3 Total Power Consumption mW LVDS Mode PDD-OC12 Total Power Consumption 376 mW LVDS Mode PDD-OC12 Total Power Consumption 310 mW LVDS Mode RXCLKO disabled IDD1.8-OC1 1.8V 51.84Mbps Total Power Supply Current mA LVPECL Mode IDD1.8-OC3 1.8V 155.52Mbps Total Power Supply Current mA LVPECL Mode IDD1.8-OC12 1.8V 622.08Mbps Total Power Supply Current mA LVPECL Mode IDD3.3-OC1 3.3V 51.84Mbps Total Power Supply Current mA LVPECL Mode IDD3.3-OC3 3.3V 155.52Mbps Total Power Supply Current mA LVPECL Mode IDD3.3-OC12 3.3V 622.08Mbps Total Power Supply Current 386 mA LVPECL Mode IDD3.3-OC12 3.3V 622.08Mbps Total Power Supply Current 198 mA LVPECL Mode RXCLKO disabled 117 PDD-OC1 Total Power Consumption mW LVPECL Mode PDD-OC3 Total Power Consumption mW LVPECL Mode PDD-OC12 Total Power Consumption 1485 mW LVPECL Mode PDD-OC12 Total Power Consumption 865 mW LVPECL Mode RXCLKO disabled TABLE 20: LVDS/DIFFERENTIAL LVPECL INPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER VIH LVDS/LVPECL Input High Voltage VIL LVDS/LVPECL Input Low Voltage VIDIFF VICOMM MIN TYP MAX VDDIO + 100 VDDIO - 100 LVDS/LVPECL Input Differential Voltage | VIH - VIL | 0 34 mV mV 100 LVDS/LVPECL Input Common Mode Voltage UNITS CONDITIONS 1200 2400 mV VDDIO mV XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 FIGURE 19. LVDS/DIFFERENTIAL LVPECL VOLTAGE PARAMETER CONVENTION VIN_P "1" "0" "1" VIDIFF VIH VICOMM VIN_N VIL VIDIFF = | VIH - VIL | VICOMM = ( VIH + VIL ) / 2 35 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 21: LVDS OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE VOH LVDS VOL PARAMETER MIN TYP MAX UNITS CONDITIONS Output High Voltage 1100 1250 1500 mV 100 Ω line - line LVDS Output Low Voltage 700 900 1200 mV 100 Ω line - line VODIFF LVDS Output Differential Voltage | VOH - VOL | 250 450 mV 100 Ω line - line VOCOMM LVDS Output Common Mode Voltage 850 1350 mV 100 Ω line - line 1050 TABLE 22: DIFFERENTIAL LVPECL OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN TYP VOH LVPECL Output High Voltage VDDIO - 900 mV VOL LVPECL Output Low Voltage VDDIO - 1800 mV VODIFF LVPECL Output Differential Voltage | VOH - VOL | VOCOMM LVPECL Output Common Mode Voltage 600 MAX 1100 VDDIO - 1350 UNITS mV CONDITIONS Terminate with 50Ω to VDD_IO-2.0 V TABLE 23: LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified SYMBOL TYPE PARAMETER MIN VOH LVCMOS Output High Voltage VOL LVCMOS VIH TYP MAX UNITS CONDITIONS 2.4 VDD_IO V IOH = -8.0mA Output Low Voltage 0 0.4 V IOH = 8.0mA LVTTL/ LVCMOS Input High Voltage 2.0 VDD_IO V VIL LVTTL/ LVCMOS Input Low Voltage 0 0.8 V ILEAK LVTTL/ LVCMOS Input Leakage Current -10 10 µA VIN = VDD_IO or VIN = 0 ILEAK_PU LVTTL/ LVCMOS Input Leakage Current with Pull-Up Resistor -100 10 µA VIN = 0 ILEAK_PD LVTTL/ LVCMOS Input Leakage Current with Pull-Down Resistor -10 100 µA VIN = VDD_IO NOTE: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only. 36 XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 24: ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT91L34IV 128-pin Plastic Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP) -40°C to +85°C XRT91L34IV-F 128-pin Pb-Free Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP) -40°C to +85°C PACKAGE DIMENSIONS 128-PIN Low Profile QUAD FLAT PACK (14 x 14 x 1.4 mm, LQFP) Rev. 1.00 D D1 96 65 97 64 D1 D 33 128 1 32 B e A2 C A Seating Plane α L A1 SYMBOL MIN INCHES MAX MILLIMETERS MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.005 0.009 0.13 0.23 C 0.004 0.008 0.09 0.20 D 0.622 0.638 15.80 16.20 D1 0.547 0.555 13.90 14.10 e L 0.0157BSC 0.018 0.030 0.40BSC 0.45 7o 0o 0o α Note: The control dimension is in millimeter. 37 0.75 7o XRT91L34 QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR REV. 1.0.1 TABLE 25: REVISION HISTORY REVISION # 1.0.0 1.0.1 DATE DESCRIPTION September 2007 New Release October 2007 Fixed VOH, VOL and VOCOMM specs in Figure 21 as per design input and product engineering characterization. 38