SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCLS710 – MARCH 2008 FEATURES 1 • • • • • (1) • • • • • • Controlled Baseline – One Assembly Site – One Test Site – One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive up to 10 LSTTL Loads Low Power Consumption, 80 µA Max ICC Typical tpd = 15 ns ±4 mA Output Drive at 5 V Low Input Current of 1 mA Max Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION The SN74HC74 device contains two independent D-type positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C (1) (2) ODERABLE PART NUMBER TOP-SIDE MARKING SOIC – D Reel of 2500 SN74HC74MDREP HC74MEP TSSOP – PW Reel of 2000 SN74HC74MPWREP HC74MEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE INPUTS PRE CLR CLK OUTPUTS D Q L H X X H L H L X X L H L L X X H (1) H (1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 (1) Q This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCLS710 – MARCH 2008 LOGIC DIAGRAM (POSITIVE LOGIC) Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX –0.5 7 (1) UNIT V IIK Input clamp current VI < 0 or VI = 0 to VCC ±20 mA IOK Output clamp current VO < 0 or VO = 0 to VCC (1) ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 113 °C/W 150 °C Continuous current through VCC or GND θJA Package thermal impedance Tstg Storage temperature range (1) (2) (2) PW package –60 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 UNIT V 1.5 3.15 V 4.2 VCC = 2 V 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 VI Input voltage 0 VCC V VO Output voltage 0 VCC V Δt\Δv Input transition rise/fall time VCC = 6 V 1.8 VCC = 2 V TA (1) 2 1000 VCC = 4.5 V 500 VCC = 6 V 400 Operating free-air temperature V –55 125 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74HC74-EP SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCLS710 – MARCH 2008 ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA VOL ICC VI = VCC or 0, TYP 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 4.5 V 3.98 4.3 3.7 6V 5.48 5.8 MAX UNIT V 5.2 0.002 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V ±0.1 ±100 ±1000 nA 4 80 µA 3 10 10 pF IOL = 5.2 mA VI = VCC or 0 MAX MIN MIN 2V VI = VIH or VIL II TA = 25°C VCC IO = 0 Ci 6V 2 V to 6 V V TIMING REQUIREMENTS VCC fclock Clock frequency PRE or CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK↑ PRE or CLR inactive th Hold time, data after CLK↑ TA = 25°C MIN MAX MIN MAX 2V 6 4.2 4.5 V 31 21 6V 0 2V 100 36 150 0 4.5 V 20 30 6V 17 25 2V 80 120 4.5 V 16 24 6V 14 20 2V 100 150 4.5 V 20 30 6V 17 25 2V 25 40 4.5 V 5 8 6V 4 7 2V 0 0 4.5 V 0 0 6V 0 0 Product Folder Link(s): SN74HC74-EP MHz 25 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated UNIT ns ns ns 3 SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCLS710 – MARCH 2008 SWITCHING CHARACTERISTICS over operating free-air temperature range CL = 50 pF, (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK tt Q or Q Q or Q VCC TA = 25°C MIN TYP MAX MIN 2V 6 10 4.2 4.5 V 31 50 21 6V 36 60 25 MAX UNIT MHz 2V 70 230 345 4.5 V 20 46 69 6V 15 39 59 2V 70 175 250 4.5 V 20 35 50 6V 15 30 42 2V 28 75 110 4.5 V 8 15 22 6V 6 13 19 ns ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS No load Submit Documentation Feedback TYP 35 UNIT pF Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74HC74-EP SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCLS710 – MARCH 2008 PARAMETER MEASURMENT INFORMATION Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74HC74-EP 5 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN74HC74MPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/08613-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN74HC74-EP : • Catalog: SN74HC74 • Automotive: SN74HC74-Q1 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2011 • Military: SN54HC74 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74HC74MPWREP Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC74MPWREP TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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