SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC General Description Features The SM73201 is a 16-bit successive-approximation register (SAR) Analog-to-Digital converter (ADC) with a maximum sampling rate of 250 kSPS. The converter features a differential analog input with an excellent common-mode signal rejection ratio of 85 dB, making the SM73201 suitable for noisy environments. The SM73201 operates with a single analog supply (VA) and a separate digital input/output (VIO) supply. VA can range from +4.5V to +5.5V and VIO can range from +2.7V to +5.5V. This allows a system designer to maximize performance and minimize power consumption by operating the analog portion of the ADC at a VA of +5V while interfacing with a +3.3V controller. The serial data output is binary 2's complement and is SPI™ compatible. The performance of the SM73201 is guaranteed over temperature at clock rates of 1 MHz to 5 MHz and reference voltages of +2.5V to +5.5V. The SM73201 is available in a small 10-lead MSOP package. The high accuracy, differential input, low power consumption, and small size make the SM73201 ideal for direct connection to bridge sensors and transducers in battery operated systems or remote data acquisition applications. ■ ■ ■ ■ ■ ■ ■ Renewable Energy Grade Guaranteed performance from 50 to 250 kSPS Separate Digital Input/Output Supply True differential input External voltage reference range of +0.5V to VA Wide input common-mode voltage range of 0V to VA SPI™/QSPI™/MICROWIRE™ compatible Serial Interface ■ Operating temperature range of −40°C to +85°C ■ Small MSOP-10 package Key Specifications ■ ■ ■ ■ ■ ■ Conversion Rate SNR SFDR THD Power Consumption — 200 kSPS, 5V — 250 kSPS, 5V — Power-Down, 5V 50 kSPS to 250 kSPS 93.2 dBc 108 dBc − 104 dBc 5.3 mW 5.8 mW 10 µW Applications ■ ■ ■ ■ PV DC Arc Detect System I/O Modules Solar Data Acquisition Instrumentation and Control Systems Typical Application 30155482 TRI-STATE® is a trademark of National Semiconductor Corporation. MICROWIRE™ is a trademark of National Semiconductor Corporation. QSPI™ and SPI™ are trademarks of Motorola, Inc. © 2012 Texas Instruments Incorporated 301554 SNOSB89A www.ti.com SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC May 30, 2012 SM73201 Ordering Information Temperature Range Description Top Mark SM73201IMM Order Code −40°C to +85°C 10-Lead MSOP Package, 1000 Units Tape & Reel S201 SM73201IMMX −40°C to +85°C 10-Lead MSOP Package, 3500 Units Tape & Reel S201 SM73201IMME −40°C to +85°C 10-Lead MSOP Package, 250 Units Tape & Reel S201 Block Diagram 30155402 Pin Descriptions Connection Diagram Pin No. 30155405 www.ti.com 2 Symbol Description 1 VREF Voltage Reference +0.5V < VREF < VA 2 +IN Non-Inverting Input 3 −IN Inverting Input 4 GND Ground 5 GND Ground 6 CS 7 DOUT Serial Data Output 8 SCLK Serial Clock 9 VIO Digital Input/Output Power +2.7V < VREF < +5.5V 10 VA Analog Power +4.5V < VREF < +5.5V Chip Select Bar (Note 1, Note 2) −40°C ≤ TA ≤ +85°C Supply Voltage, VA +4.5V to +5.5V Supply Voltage, VIO +2.7V to +5.5V Reference Voltage, VREF +0.5V to VA Analog Input Pins Voltage Range 0V to VA Differential Analog Input Voltage −VREF to +VREF Input Common-Mode Voltage, VCM See Figure 10 (Sect 2.3) Digital Input Pins Voltage Range 0V to VIO Clock Frequency 1 MHz to 5 MHz Operating Temperature Range 2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Analog Supply Voltage VA Digital I/O Supply Voltage VIO Voltage on Any Analog Input Pin to GND Voltage on Any Digital Input Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Charge Device Model Junction Temperature Storage Temperature −0.3V to 6.5V −0.3V to 6.5V −0.3V to (VA + 0.3V) −0.3V to (VIO + 0.3V) ±10 mA ±50 mA See (Note 4) Package Thermal Resistance 2500V 250V 1250V +150°C −65°C to +150°C Package θJA 10-lead MSOP 240°C / W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) SM73201 Converter Electrical Characteristics (Note 7) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C. Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS Resolution DNL Differential Non-Linearity INL Integral Non-Linearity OE Offset Error OEDRIFT Offset Error Temperature Drift FSE GE GEDRIFT 16 Bits -0.5/+0.8 LSB ±0.8 LSB VREF = 2.5V −0.1 mV VREF = 5V −0.4 mV VREF = 2.5V 3.7 µV/°C VREF = 5V 2.5 µV/°C Positive Full-Scale Error −0.003 %FS Negative Full-Scale Error −0.002 %FS Positive Gain Error −0.002 %FS Negative Gain Error −0.0001 %FS 0.3 ppm/° C Gain Error Temperature Drift DYNAMIC CONVERTER CHARACTERISTICS SINAD SNR THD SFDR ENOB Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Effective Number of Bits VREF = 2.5V 85 88 dBc VREF = 4.5V to 5.5V 89 93.0 dBc VREF = 2.5V 85 88 dBc VREF = 4.5V to 5.5V 89 93.2 dBc VREF = 2.5V −104 dBc VREF = 4.5V to 5.5V −106 dBc VREF = 2.5V 108 dBc VREF = 4.5V to 5.5V 111 dBc VREF = 2.5V 13.8 14.3 bits VREF = 4.5V to 5.5V 14.5 15.2 bits 3 www.ti.com SM73201 Operating Ratings Absolute Maximum Ratings (Note 1, Note SM73201 Symbol Parameter Conditions Min Typ Max Units ANALOG INPUT CHARACTERISTICS VIN −VREF Differential Input Range CS high IINA CINA CMRR Analog Input Current Input Capacitance (+IN or −IN) Common Mode Rejection Ratio +VREF V ±1 µA VREF = 5V, VIN = 0V, fS = 50 kSPS 3.2 nA VREF = 5V, VIN = 0V, fS = 200 kSPS 10.3 nA In Acquisition Mode 20 pF In Conversion Mode 4 pF See the Specification Definitions for the test condition 85 dB DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage fIN = 0 Hz VIL Input Low Voltage fIN = 0 Hz IIND CIND 0.7 x VIO 1.9 V 0.3 x VIO V Digital Input Current ±1 µA Input Capacitance 4 pF 1.7 DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage ISOURCE = 200 µA VIO − 0.2 ISOURCE = 1 mA VIO − 0.03 VIO − 0.09 ISOURCE = 200 µA 0.01 ISOURCE = 1 mA 0.07 VOL Output Low Voltage IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA COUT TRI-STATE Output Capacitance Force 0V or VA V V 0.4 V ±1 µA V 4 Output Coding pF Binary 2'S Complement POWER SUPPLY CHARACTERISTICS VA Analog Supply Voltage Range VIO Digital Input/Output Supply Voltage Range VREF Reference Voltage Range Analog Supply Current, Conversion IVA (Conv) Mode IVIO (Conv) (Note 9) 4.5 5 5.5 V 2.7 3 5.5 V 0.5 5 VA V VA = 5V, fSCLK = 4 MHz, fS = 200 kSPS 1060 VA = 5V, fSCLK = 5 MHz, fS = 250 kSPS 1160 VIO = 3V, fSCLK = 4 MHz, Digital I/O Supply Current, Conversion fS = 200 kSPS Mode VIO = 3V, fSCLK = 5 MHz, fS = 250 kSPS 100 µA VA = 5V, fSCLK = 4 MHz, fS = 200 kSPS 80 µA VA = 5V, fSCLK = 5 MHz, fS = 250 kSPS 100 fSCLK = 5 MHz, VA = 5V 7 IVA (PD) Analog Supply Current, Power Down Mode (CS high) fSCLK = 0 Hz, VA = 5V (Note 8) 2 IVIO (PD) Digital I/O Supply Current, Power Down fSCLK = 5 MHz, VIO = 3V Mode (CS high) fSCLK = 0 Hz, VIO = 3V (Note 8) 1 Reference Current, Power Down Mode fSCLK = 5 MHz, VREF = 5V IVREF (PD) (CS high) fSCLK = 0 Hz, VREF = 5V (Note 8) www.ti.com µA µA Reference Current, Conversion Mode Power Consumption, Conversion Mode 1340 80 IVREF (Conv) PWR (Conv) µA 0.3 0.5 5.3 VA = 5V, fSCLK = 5 MHz, fS = 250 kSPS, and fIN = 20 5.8 µA µA 3 µA µA 0.5 0.5 VA = 5V, fSCLK = 4 MHz, fS = 200 kSPS, and fIN = 20 kHz, 4 170 µA µA 0.7 µA mW 6.7 mW Parameter Conditions Power Consumption, Power Down PWR (PD) Mode (CS high) PSRR Power Supply Rejection Ratio Min Typ fSCLK = 5 MHz, VA = 5.0V (Note 8) 35 fSCLK = 0 Hz, VA = 5.0V (Note 8) 10 See the Specification Definitions for the test condition −78 Max Units µW 15 µW dB AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency fS Maximum Sample Rate tACQ Acquisition/Track Time tCONV Conversion/Hold Time tAD Aperture Delay (Note 10) 1 5 MHz 50 250 kSPS 17 SCLK cycles 600 ns See the Specification Definitions 6 ns SM73201 Timing Specifications (Note 7) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, VREF = 2.5V to 5.5V, fSCLK = 1Mz to 5MHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C. Symbol Min Typ tCSS CS Setup Time prior to an SCLK rising edge Parameter 8 3 tCSH CS Hold Time after an SCLK rising edge 8 3 tDH DOUT Hold Time after an SCLK falling edge 6 11 Max Units ns ns tDA DOUT Access Time after an SCLK falling edge 18 41 ns tDIS DOUT Disable Time after the rising edge of CS (Note 11) 20 30 ns tCS Minimum CS Pulse Width tEN DOUT Enable Time after the 2nd falling edge of SCLK 20 70 tCH SCLK High Time 20 ns tCL SCLK Low Time 20 ns tr DOUT Rise Time 7 ns tf DOUT Fall Time 7 ns 20 ns ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the SM73201 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 9: The value of VIO is independent of the value of VA. For example, VIO could be operating at 5.5V while VA is operating at 4.5V or VIO could be operating at 2.7V while VA is operating at 5.5V. Note 10: While the maximum sample rate is fSCLK / 20, the actual sample rate may be lower than this by having the CS rate slower than fSCLK / 20. Note 11: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit. 5 www.ti.com SM73201 Symbol SM73201 Timing Diagrams 30155401 FIGURE 1. SM73201 Single Conversion Timing Diagram 30155410 FIGURE 5. Valid CS Assertion Times 30155408 FIGURE 2. Timing Test Circuit 30155412 30155406 FIGURE 6. Voltage Waveform for tDIS FIGURE 3. DOUT Rise and Fall Times 30155411 FIGURE 4. DOUT Hold and Access Times www.ti.com 6 APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive FullScale Error and Negative Full-Scale Error and can be calculated as: PSRR = 20 LOG (ΔOutput Offset / ΔVA) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below one-half the sampling frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as Gain Error = Positive Full-Scale Error − Negative Full-Scale Error INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from ½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The SM73201 is guaranteed not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from code 0x8001h to 0x8000h and −VREF + 1 LSB. NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. 7 www.ti.com SM73201 OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 0x0000h to 0x0001h and 1 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from code 0xFFFEh to 0xFFFFh and VREF - 1 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the SM73201, VA is changed from 4.5V to 5.5V. Specification Definitions SM73201 Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. VA THD vs. VA 30155433 30155432 SINAD vs. VREF THD vs. VREF 30155437 30155436 SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY 30155441 www.ti.com 30155440 8 SM73201 SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY 30155449 30155448 SINAD vs. TEMPERATURE THD vs. TEMPERATURE 30155472 30155471 VA CURRENT vs. VA VA CURRENT vs. SCLK FREQUENCY 30155435 30155455 9 www.ti.com SM73201 VA CURRENT vs. TEMPERATURE VREF CURRENT vs. VREF 30155454 30155434 VREF CURRENT vs. SCLK FREQUENCY VREF CURRENT vs. TEMPERATURE 30155452 30155451 VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY 30155444 www.ti.com 30155442 10 SM73201 VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS 30155414 30155443 11 www.ti.com SM73201 peak-to-peak input range is limited to (2 x VREF). See Section 2.3 for more details. Reducing VREF also reduces the size of the least significant bit (LSB). For example, the size of one LSB is equal to [(2 x VREF) / 2n], which is 152.6 µV where n is 16 bits and VREF is 5V. When the LSB size goes below the noise floor of the SM73201, the noise will span an increasing number of codes and overall performance will suffer. Dynamic signals will have their SNR degrade; while, D.C. measurements will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results of a number of consecutive conversions. VREF and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input is sampled. Hence, IREF, I+IN, and I-IN are a series of transient spikes that occur at a frequency dependent on the operating sample rate of the SM73201. IREF changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and “Reference Current vs. Temperature” in the Typical Performance Curves section for additional details. Functional Description The SM73201 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sampleand-hold function. The differential nature of the analog inputs is maintained from the internal sample-and-hold circuits throughout the A/D converter to provide excellent commonmode signal rejection. The SM73201 operates from independent analog and digital supplies. The analog supply (VA) can range from 4.5V to 5.5V and the digital input/output supply (VIO) can range from 2.7V to 5.5V. The SM73201 utilizes an external reference (VREF), which can be any voltage between 0.5V and VA. The value of VREF determines the range of the analog input, while the reference input current (IREF) depends upon the conversion rate. The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry while a conversion is in progress. The SM73201 features a zero-power track mode (ZPTM) where the ADC is consuming the minimum amount of power (Power-Down Mode) while the internal sampling capacitor array is tracking the applied analog input voltage. The converter enters ZPTM at the end of each conversion window and experiences no delay when the ADC enters into Conversion Mode. This feature allows the user an easy means for optimizing system performance based on the settling capability of the analog source while minimizing power consumption. ZPTM is exercised by bringing chip select bar (CS) high or when CS is held low after the conversion is complete (after the 18th falling edge of the serial clock). The SM73201 communicates with other devices via a Serial Peripheral Interface (SPI™), a synchronous serial interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out (DOUT). The external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by internal capacitor leakage. Each conversion requires a minimum of 18 SCLK cycles to complete. If less than 16 bits of conversion data are required, CS can be brought high at any point during the conversion. This procedure of terminating a conversion prior to completion is commonly referred to as short cycling. The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB) first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in progress and thus there is no pipe line delay or latency. 2.0 ANALOG SIGNAL INPUTS The SM73201 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN). 2.1 Differential Input Operation The transfer curve of the SM73201 for a fully differential input signal is shown in Figure 7. A positive full scale output code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained when (+IN) − (−IN) is greater than or equal to (VREF − 1 LSB). A negative full scale code (1000 0000 0000 0000b or 8000h or -32,768d) will be obtained when [(+IN) − (−IN)] is less than or equal to (−VREF + 1 LSB). This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will determine any given output code. 1.0 REFERENCE INPUT (VREF) The externally supplied reference voltage (VREF) sets the analog input range. The SM73201 will operate with VREF in the range of 0.5V to VA. Operation with VREF below 2.5V is possible with slightly diminished performance. As VREF is reduced, the range of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (VCM), the differential www.ti.com 30155499 FIGURE 7. ADC Transfer Curve 12 SM73201 Both inputs should be biased at a common mode voltage (VCM), which will be thoroughly discussed in Section 2.3. Figure 8 shows the SM73201 being driven by a full-scale differential source. 30155461 30155480 FIGURE 10. VCM range for Differential Input operation FIGURE 8. Differential Input 2.2 Single-Ended Input Operation For single-ended operation, the non-inverting input (+IN) of the SM73201 can be driven with a signal that has a peak-topeak range that is equal to or less than (2 x VREF). The inverting input (−IN) should be biased at a stable VCM that is halfway between these maximum and minimum values. In order to utilize the entire dynamic range of the SM73201, VREF is limited to (VA / 2). This allows +IN a maximum swing range of ground to VA. Figure 9 shows the SM73201 being driven by a full-scale single-ended source. 30155462 FIGURE 11. VCM range for single-ended operation TABLE 1. Allowable VCM Range Input Signal 30155481 Differential Single-Ended FIGURE 9. Single-Ended Input Since the design of the SM73201 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only be used if the performance degradation (compared with differential operation) is acceptable. Minimum VCM Maximum VCM VREF / 2 VA − VREF / 2 VREF VA − VREF 2.4 CMRR By using this differential input, small signals common to both inputs are rejected. As shown in Figure 12, noise is immune at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency increases to 1 MHz, the CMRR rolls off to 40 dB . In general, operation with a fully differential input signal or voltage will provide better performance than with a single-ended input. However, if desired, the SM73201 can be presented with a single-ended input. 2.3 Input Common Mode Voltage The allowable input common mode voltage (VCM) range depends upon VA and VREF used for the SM73201. The ranges of VCM are depicted in Figure 10 and Figure 11. Note that these figures only apply to a VA of 5V. Equations for calculating the minimum and maximum VCM for differential and singleended operations are shown in Table 1. 13 www.ti.com SM73201 and a series resistor (RSAMPLE), as shown in Figure 13. Typical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms respectively. If there is not a large external capacitor (CEXT) at the analog input of the ADC, a voltage spike will be observed at the input pins. This is a result of CSAMPLE and CEXT being at different voltage potentials. The magnitude and direction of the voltage spike depend on the difference between the voltage of CSAMPLE and CEXT. If the voltage at CSAMPLE is greater than the voltage at CEXT, a positive voltage spike will occur. If the opposite is true, a negative voltage spike will occur. It is not critical for the performance of the SM73201 to filter out the voltage spike. Rather, ensure that the transient of the spike settles out within tACQ; for recommended solutions, see Section 4.0 in the Application Information. 30155475 FIGURE 12. Analog Input CMRR vs. Frequency 2.5 Input Settling When the SM73201 enters acquisition (tACQ) mode at the end of the conversion window, the internal sampling capacitor (CSAMPLE) is connected to the ADC input via an internal switch www.ti.com 30155485 FIGURE 13. ADC Input Capacitors 14 3.2 SCLK Input The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The SM73201 offers guaranteed performance with the clock rates indicated in the electrical table. The SM73201 enters acquisition mode on the 18th falling edge of SCLK during a conversion frame. Assuming that the LSB is clocked into a controller on the 18th rising edge of SCLK, there is a minimum acquisition time period that must be met before a new conversion frame can begin. Other than the 18th rising edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the controller. 3.3 Data Output The data output format of the SM73201 is two’s complement as shown in Figure 7. This figure indicates the ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or noise. Each data output bit is output on the falling edges of SCLK. DOUT is in a high impedance state for the 1st falling edge of SCLK while the 2nd SCLK falling edge clocks out a leading zero. The 3rd to 18th SCLK falling edges clock out the conversion result, MSB first. While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of SCLK may be used to capture the conversion result if the minimum hold time for DOUT is acceptable. See Figure 4 for DOUT hold (tDH) and access (tDA) times. DOUT is enabled on the second falling edge of SCLK after the assertion of CS and is disabled on the rising edge of CS. If CS is raised prior to the 18th falling edge of SCLK, the current conversion is aborted and DOUT will go into its high impedance state. A new conversion will begin when CS is driven LOW. 3.1 CS Input The CS (chip select bar) input is active low and is CMOS compatible. The SM73201 enters conversion mode when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the SM73201 is always in acquisition mode and thus consuming the minimum amount of power. Since CS must be asserted to begin a conversion, the sample rate of the SM73201 is equal to the assertion rate of CS. Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs 30155401 FIGURE 14. SM73201 Single Conversion Timing Diagram 15 www.ti.com SM73201 during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time (the 3rd falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the Timing Specification table. 3.0 SERIAL DIGITAL INTERFACE The SM73201 communicates via a synchronous 3-wire serial interface as shown in Figure 1 or re-shown in Figure 14 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of the serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The SM73201's DOUT pin is in a high impedance state when CS is high and for the first clock period after CS is asserted; DOUT is active for the remainder of time when CS is asserted. The SM73201 samples the differential input upon the assertion of CS. Assertion is defined as bringing the CS pin to a logic low state. For the first 17 periods of the SCLK following the assertion of CS, the SM73201 is converting the analog input voltage. On the 18th falling edge of SCLK, the SM73201 enters acquisition (tACQ) mode. For the next three periods of SCLK, the SM73201 is operating in acquisition mode where the ADC input is tracking the analog input signal applied across +IN and -IN. During acquisition mode, the SM73201 is consuming a minimal amount of power. The SM73201 can enter conversion mode (tCONV) under three different conditions. The first condition involves CS going low (asserted) with SCLK high. In this case, the SM73201 enters conversion mode on the first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the SM73201 automatically enters conversion mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the SM73201 enters conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, there are minimum setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. See Figure 5 in the Timing Diagram section for more information. SM73201 Applications Information nated by pulling CS high after the 10th bit has been clocked out. OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the SM73201: −40°C ≤ TA ≤ +85°C +4.5V ≤ VA ≤ +5.5V +2.7V ≤ VIO ≤ +5.5V +0.5V ≤ VREF ≤ +5.5V 1 MHz ≤ fSCLK ≤ 5 MHz VCM: See Section 2.3 5.2 Burst Mode Operation Normal operation of the SM73201 requires the SCLK frequency to be 20 times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 250 kSPS, the SM73201 should be run with an SCLK frequency of 5 MHz and a CS rate as slow as the system requires. When this is accomplished, the SM73201 is operating in burst mode. The SM73201 enters into acquisition mode at the end of each conversion, minimizing power consumption. This causes the converter to spend the longest possible time in acquisition mode. Since power consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy the requirements of the system. 4.0 ANALOG INPUT CONSIDERATIONS As stated previously in Section 2.5, it is not critical for the performance of the SM73201 to filter out the voltage spike that occurs when the SM73201 enters acquisition (tACQ) mode at the end of the conversion window. However, it is critical that a system designer ensures that the transients of the spike settle out within tACQ. The burden of this task can be placed on the analog source itself or the burden can be shared by the source and an external capacitor, CEXT as shown in Figure 13. The external capacitor acts as a local charge reservoir for the internal sampling capacitor and thus reduces the size of the voltage spike. For low frequency analog sources such as sensors with DC-like output behaviors, CEXT values greater than 1 nF are recommended. However, some sensors and signal conditioning circuitry will not be able to maintain their stability in the presence of the external capacitive load. In these instances, a series resistor (REXT) is recommended. The magnitude of REXT is dependent on the output capability of the analog source and the settling requirement of the ADC. Independent of the presence of an external capacitor, the system designer always has the option of lowering the sample rate of the SM73201 which directly controls the amount of time allowed for the voltage spike to settle. The slower the sample rate, the longer the tACQ time or settling time. This is possible with the SM73201 since the converter enters tACQ at the end of the prior conversion and thus is tracking the analog input source the entire time between conversions. 6.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS For best performance, care should be taken with the physical layout of the printed circuit board. This is especially true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so it is important that any noise settles out before the conversion begins. 6.1 Analog and Digital Power Supplies Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. Power to the SM73201 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor should be used to bypass the SM73201 supply, with the 0.1 µF capacitor placed as close to the SM73201 package as possible. Since the SM73201 has both the VA and VIO pins, the user has three options on how to connect these pins. The first option is to tie VA and VIO together and power them with the same power supply. This is the most cost effective way of powering the SM73201 but is also the least ideal. As stated previously, noise from VIO can couple into VA and adversely affect performance. The other two options involve the user powering VA and VIO with separate supply voltages. These supply voltages can have the same amplitude or they can be different. VA can be set to any value between +4.5V and +5.5V; while VIO can be set to any value between +2.7V and +5.5V. Best performance will typically be achieved with VA operating at 5V and VIO at 3V. Operating VA at 5V offers the best linearity and dynamic performance when VREF is also set to 5V; while operating VIO at 3V reduces the power consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the noise created by charging and discharging the capacitance of the digital interface pins. 5.0 POWER CONSUMPTION The architecture, design, and fabrication process allow the SM73201 to operate at conversion rates up to 250 kSPS while consuming very little power. The SM73201 consumes the least amount of power while operating in acquisition (powerdown) mode. For applications where power consumption is critical, the SM73201 should be operated in acquisition mode as often as the application will tolerate. To further reduce power consumption, stop the SCLK while CS is high. 5.1 Short Cycling Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can be used to lower the power consumption in those applications that do not need a full 16-bit resolution, or where an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be terminated after the first few bits. This will lower power consumption in the converter since the SM73201 spends more time in acquisition mode and less time in conversion mode. Short cycling is accomplished by pulling CS high after the last required bit is received from the SM73201 output. This is possible because the SM73201 places the latest converted data bit on DOUT as it is generated. If only 10-bits of the conversion result are needed, for example, the conversion can be termi- www.ti.com 6.2 Voltage Reference The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the SM73201 draws very little current from the reference on average, there are higher instantaneous current spikes at the reference. VREF of the SM73201, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if VREF is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external reference circuitry will appear in the digital results. The use of an active reference source is recommended. The LM4040 and LM4050 shunt ref16 cated within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane. Furthermore, the GND pins on the SM73201 and all the components in the reference circuitry and input signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other high power digital device. 6.3 PCB Layout Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the SM73201 due to supply noise, avoid using the same supply for the VA and VREF of the SM73201 that is used for digital circuitry on the board. Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. A single, uniform ground plane and the use of split power planes are recommended. The power planes should be lo- 7.0 APPLICATION CIRCUITS The following figures are examples of the SM73201 in typical application circuits. These circuits are basic and will generally require modification for specific circumstances. 7.1 Data Acquisition Figure 15 shows a typical connection diagram for the SM73201 operating at VA of +5V. VREF is connected to a 2.5V shunt reference, the LM4020-2.5, to define the analog input range of the SM73201 independent of supply variation on the +5V supply line. The VREF pin should be de-coupled to the ground plane by a 0.1 µF ceramic capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close as possible to the VREF pin while the placement of the tantalum capacitor is less critical. It is also recommended that the VA and VIO pins of the SM73201 be decoupled to ground by a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. 30155463 FIGURE 15. Low cost, low power Data Acquisition System 17 www.ti.com SM73201 erence families and the SM74601, LM4120, and LM4140 series reference families are excellent choices for a reference source. SM73201 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Number SM73201CIMM NS Package Number MUB10A www.ti.com 18 SM73201 Notes 19 www.ti.com SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated