HYNIX HY5S5B6GLF-H

256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Specification of
256M (16Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Apr. 2006
1
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Draft
Feb. 2006
Preliminary
0.2
1. Changed
166MHz IDD1 : 60mA --> 75mA
133MHz IDD1 : 55mA --> 65mA
105MHz IDD1 : 50mA --> 55mA
2. Remove
CL2 operation (Page 13 to 14)
Mar. 2006
Preliminary
1.0
1. Release
Apr. 2006
Final
Rev 1.0 / Apr. 2006
2
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
DESCRIPTION
The Hynix HY5S5B6GLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the
main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of
4,194,304x16.
Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch
each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the
input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/
Output bus. All the commands are latched in synchronization with the rising edge of CLK.
The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8
locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Mobile SDRAM uses an internal pipelined architecture to achieve high-speed
operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randonaccess operation.
Read and write accesses to the Hynix Mobile SDRAMs are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access. A burst of Read or Write cycles in progress can be terminated by a
burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any
cycle(This pipelined design is not restricted by a 2N rule).
The Hynix Mobile SDR also provides for special programmable options including Partial Array Self Refresh of full array,
half array, quarter array Temperature Compensated Self Refresh of 40 or 85 degrees oC.
The Hynix Mobile SDR has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to
reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically
adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power
reduction by removing power to the memory array within each Mobile SDR. By using this feature, the system can cut
off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout
flexibility.
All inputs are LV-CMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
Rev 1.0 / Apr. 2006
3
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
FEATURES
●
Standard SDRAM Protocol
●
Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
●
MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
●
Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
●
LVCMOS compatible I/O Interface
●
Low Voltage interface to reduce I/O power
●
Programmable burst length: 1, 2, 4, 8 or full page
●
Programmable Burst Type : sequential or interleaved
●
Programmable CAS latency of 3
●
Programmable Drive Strength
●
●
●
Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
-25oC ~ 85oC Operation Temperature
- Extended Temp. : -25oC ~ 85oC
Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead), 8 x 10 [mm2], t=0.1mm max
HY5S5B6GLFP : Lead Free
HY5S5B6GLF : Leaded
Rev 1.0 / Apr. 2006
4
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
256Mb Mobile SDR SDRAM ORDERING INFORMATION
Part Number
Clock Frequency
HY5S5B6GLF-6
166MHz
3
HY5S5B6GLF-H
133MHz
3
HY5S5B6GLF-S
105MHz
3
HY5S5B6GLFP-6
166MHz
3
HY5S5B6GLFP-H
133MHz
3
HY5S5B6GLFP-S
105MHz
3
HY5S5B6GLF-6E
166MHz
3
HY5S5B6GLF-HE
133MHz
3
HY5S5B6GLF-SE
105MHz
3
HY5S5B6GLFP-6E
166MHz
3
HY5S5B6GLFP-HE
133MHz
3
HY5S5B6GLFP-SE
105MHz
3
Rev 1.0 / Apr. 2006
CAS
Operation
Organization Interface
Latency
temperature
54Ball
FBGA
Leaded
Commercial
Temp
(-0oC ~ 70oC)
Lead Free
4banks x 4Mb x
16
LVCMOS
Leaded
Extended Temp
(-25oC ~ 85oC)
Lead Free
5
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BALL DESCRIPTION
1
2
3
A
VSS
DQ15
B
DQ14
C
4
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
/CAS
/RAS
/WE
G
A12
A11
A9
BA0
BA1
/CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
TOP
VIEW
Top view
Rev 1.0 / Apr. 2006
6
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BALL DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
CLK
INPUT
Clock : The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
INPUT
Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
CS
INPUT
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
INPUT
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A12
INPUT
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
INPUT
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
INPUT
Data Mask : Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
I/O
VDD/VSS
SUPPLY
Power supply for internal circuits
VDDQ/VSSQ
SUPPLY
Power supply for output buffers
NC
-
Rev 1.0 / Apr. 2006
Data Input/Output : Multiplexed data input/output pin
No connection
7
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
ABSOLUTE MAXIMUM RATING
Symbol
Rating
Ambient Temperature
Parameter
TA
-25 ~ 85
o
Storage Temperature
TSTG
-55 ~ 125
o
VIN, VOUT
VDD
VDDQ
IOS
PD
-1.0 ~ 2.6
-1.0 ~ 2.6
-1.0 ~ 2.6
50
1
TSOLDER
260 . 10
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Short Circuit Output Current
Power Dissipation
Soldering Temperature . Time
Unit
C
C
V
V
V
mA
W
oC . Sec
DC OPERATING CONDITION (TA= -25 to 85oC )
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD
VDDQ
VIH
VIL
Min
1.7
1.7
0.8*VDDQ
-0.3
Typ
1.8
1.8
-
Max
1.95
1.95
VDDQ+0.3
0.3
Unit
V
V
V
V
Note
1
1, 2
1, 2
1, 2
Note :
1. All Voltages are referenced to VSS = 0V
2. VDDQ must not exceed the level of VDD
AC OPERATING TEST CONDITION (TA= -25 to 85 oC, VDD = 1.8V, VSS = 0V)
Parameter
AC Input High/Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise/Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Symbol
VIH / VIL
Vtrip
tR / tF
Voutref
CL
Value
0.9*VDDQ/0.2
0.5*VDDQ
1
0.5*VDDQ
30
Unit
V
V
ns
V
pF
Note
1
Note 1.
Vtt=0.5xVDDQ
50Ω
Output
ZO=50Ω
30pF
Rev 1.0 / Apr. 2006
8
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CAPACITANCE (TA= 25 oC, f=1MHz)
Parameter
Input capacitance
Pin
Symbol
CLK
6/H/S
Unit
Min
Max
CI1
2
4.0
pF
A0~A12, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM
CI2
2
4.0
pF
DQ0 ~ DQ15
CI/O
2
4.5
pF
Data input/output capacitance
DC CHARACTERRISTICS I (TA= -25 to 85oC)
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
ILI
-1
1
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
VDDQ-0.2
-
V
3
Output Low Voltage
VOL
-
0.2
V
4
Note :
1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.
2. DOUT is disabled. VOUT= 0 to 1.95V.
3. IOUT = - 0.1mA
4. IOUT = + 0.1mA
Rev 1.0 / Apr. 2006
9
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
DC CHARACTERISTICS II (TA= -25 to 85oC)
Parameter
Operating Current
Symbol
IDD1
Test Condition
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
Speed
6
H
S
75
65
55
Unit Note
mA
CKE ≤ VIL(max), tCK = min
0.3
mA
CKE ≤ VIL(max), tCK = ∞
0.3
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
10
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
1.0
IDD3P
CKE ≤ VIL(max), tCK = min
IDD3PS
CKE ≤ VIL(max), tCK = ∞
1.0
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
15
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
Self Refresh Current
IDD6
CKE ≤ 0.2V
Standby Current in
Deep Power Down Mode
IDD7
See p.43~44, 50~51
Precharge Standby Current IDD2P
in Power Down Mode
IDD2PS
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
IDD2N
tRFC ≥ tRFC(min),
1
mA
3
mA
mA
65
60
55
mA
85
mA
See Next Page
mA
1
2
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
Rev 1.0 / Apr. 2006
10
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
DC CHARACTERISTICS III - Low Power (IDD6)
Memory Array
Temp.
( oC)
4 Banks
2 Banks
1 Bank
45
200
140
100
uA
85
400
280
200
uA
Unit
Notes:
1. VDD / VDDQ = 1.8V
2. Related numerical values in this 45oC are examples for reference sample value only.
3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self refresh will automatically
adjust the interval of self-refresh operation according to ambient temperature variations.
Rev 1.0 / Apr. 2006
11
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
6
H
S
Min
Max
Min
Max
Min
Max
Unit
Note
System Clock Cycle Time CAS Latency=3
tCK3
6.0
1000
7.5
1000
9.5
1000
ns
Clock High Pulse Width
tCHW
2.0
-
2.5
-
3.0
-
ns
1
Clock Low Pulse Width
tCLW
2.0
-
2.5
-
3.0
-
ns
1
Access Time From Clock CAS Latency=3
tAC3
-
5.4
-
6.5
-
7.0
ns
2
Data-out Hold Time
tOH
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
tDS
2.0
-
2.0
-
2.0
-
ns
1
Data-Input Hold Time
tDH
1.0
-
1.0
-
1.0
-
ns
1
Address Setup Time
tAS
2.0
-
2.0
-
2.0
-
ns
1
Address Hold Time
tAH
1.0
-
1.0
-
1.0
-
ns
1
CKE Setup Time
tCKS
2.0
-
2.0
-
2.0
-
ns
1
CKE Hold Time
tCKH
1.0
-
1.0
-
1.0
-
ns
1
Command Setup Time
tCS
2.0
-
2.0
-
2.0
-
ns
1
Command Hold Time
tCH
1.0
-
1.0
-
1.0
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1.0
-
1.0
-
1.0
-
ns
CLK to Data Output in
High-Z Time
tOHZ3
7.0
ns
CAS Latency=3
5.4
6.5
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev 1.0 / Apr. 2006
12
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
6
H
S
Min
Max
Min
Max
Min
Max
Unit Note
RAS Cycle Time
tRC
60
-
72.5
-
74
-
ns
RAS to CAS Delay
tRCD
18
-
22.5
-
28.5
-
ns
RAS Active Time
tRAS
42
100K
50
100K
60
100K
ns
RAS Precharge Time
tRP
18
-
22.5
-
28.5
-
ns
RAS to RAS Bank Active Delay
tRRD
12
-
15
-
19
-
ns
AUTO REFRESH Period
tRFC
80
-
80
-
80
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
tWTL
0
-
0
-
0
-
CLK
Data-in to Precharge Command
tDPL
2
-
2
-
2
-
CLK
Data-In to Active Command
tDAL
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
CLK
Precharge to Data Output
CAS Latency=3
High-Z
tPROZ3
3
-
3
-
3
-
CLK
Power Down Exit Time
tDPE
1
-
1
-
1
-
CLK
Exit Self Refresh Time
tXSR
80
-
80
-
80
-
ns
Refresh Time
tREF
-
64
-
64
-
64
ms
Rev 1.0 / Apr. 2006
tDPL+tRP
13
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Mobile Synchronous DRAM
PASR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
16
Output Buffer & Logic
Column
Pre
Decoder
LDQM,
UDQM
Memory
Cell
Array
Sense AMP & I/O Gate
Column Active
/WE
Row decoders
Refresh
4Mx16 Bank3
4Mx16 Bank2
4Mx16 Bank1
4Mx16 Bank0
Row decoders
/CAS
Row decoders
/RAS
State Machine
/CS
Row
Pre
Decoder
Row Active
DQ0
16
DQ15
Column decoders
Column Add
Counter
Bank Select
A0
BA0
Rev 1.0 / Apr. 2006
Address
Register
Burst
Counter
Burst
Length
A12
BA1
Address Buffers
A1
Mode Register
CAS
Latency
Data Out Control
14
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
BA0
A12
A11
A10
A9
A8
A7
0
0
0
0
0
OP Code
0
0
A6
A5
A4
A3
CAS Latency
OP Code
BT
A2
A1
A0
Burst Length
Burst Type
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
CAS Latency
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
0
1
0
1
1
0
1
0
A2
A1
A0
Reserved
0
0
0
Reserved
0
1
3
0
Reserved
1
Burst Length
A3 = 0
A3=1
0
1
1
0
1
2
2
0
1
0
4
4
0
1
1
8
8
Reserved
1
0
0
Reserved
Reserved
0
1
Reserved
Reserved
1
1
0
Reserved
1
1
1
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full page
Reserved
Rev 1.0 / Apr. 2006
15
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register
BA1
BA0
A12
A11
A10
A9
A8
A7
1
0
0
0
0
0
0
0
DS (Driver Strength)
A6
A5
0
0
0
1
1
1
Driver Strength
A6
A5
DS
A4
A3
0
0
A2
A1
A0
PASR
PASR (Partial Array Self Refresh)
A2
A1
A0
Full
0
0
0
All Banks
1/2 Strength
0
0
1
Half of Total Bank (BA1=0 or Bank 0,1)
0
1/4 Strength
0
1
0
Quarter of Total Bank (BA1=BA0=0 or Bank 0)
1
Reserved
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Half of Bank 0(Bank 0 and Row Address MSB=0)
1
1
0
Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0)
1
1
1
Reserved
Rev 1.0 / Apr. 2006
Self Refresh Coverage
16
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
COMMAND TRUTH TABLE
Function
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
Op Code
2
Extended Mode Register
Set
H
X
L
L
L
L
X
Op Code
2
No Operation
H
X
L
H
H
H
X
X
Device Deselect
H
X
H
X
X
X
X
X
Bank Active
H
X
L
L
H
H
X
Read
H
X
L
H
L
H
Read with Autoprecharge
H
X
L
H
L
H
Write
H
X
L
H
L
L
Write with Autoprecharge
H
X
L
H
L
Precharge All Banks
H
X
L
L
H
Precharge selected Bank
H
X
L
L
H
Burst stop
H
X
L
H
H
Data Write/Output Enable
H
X
X
Data Mask/Output Disable
H
X
X
Auto Refresh
H
H
Self Refresh Entry
H
L
Self Refresh Exit
L
H
Precharge Power Down
Entry
H
L
Precharge Power Down Exit
L
H
Clock Suspend Entry
H
L
Clock Suspend Exit
L
H
Deep Power Down Entry
H
L
Deep Power Down Exit
L
H
L
L
Row Address
BA
L
V
X
Column
H
V
X
Column
L
V
L
X
Column
H
V
L
X
X
H
X
L
X
X
L
V
L
X
X
X
X
V
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
H
H
L
X
Note
V
Column
H
X
ADDR
A10
/AP
CKEn-1
X
X
X
X
X
X
1
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev 1.0 / Apr. 2006
17
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 1 of 4)
Current
State
Idle
Row
Active
Read
Command
CS RAS CAS WE
BA0/
BA1
L
L
L
L
L
L
L
H
X
L
L
H
L
L
L
H
L
H
L
Amax-A0
Notes
Mode Register Set
Set the Mode Register
14
X
Auto or Self Refresh
Start Auto or Self Refresh
5
BA
X
Precharge
No Operation
H
BA
Row Add.
Bank Activate
Activate the specified
bank and row
L
L
BA
Col Add.
A10
Write/WriteAP
ILLEGAL
4
H
L
H
BA
Col Add.
A10
Read/ReadAP
ILLEGAL
4
L
H
H
H
X
X
No Operation
No Operation
3
H
X
X
X
X
X
Device Deselect
No Operation or Power
Down
3
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
Precharge
7
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Start Write : optional
AP(A10=H)
6
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Start Read : optional
AP(A10=H)
6
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
Termination Burst: Start
the Precharge
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Termination Burst: Start
Write(optional AP)
8,9
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Termination Burst: Start
Read(optional AP)
8
L
H
H
H
X
X
No Operation
Continue the Burst
Rev 1.0 / Apr. 2006
OP CODE
Action
Description
OP CODE
OP CODE
4
18
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 2 of 4)
Current
State
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Command
CS RAS CAS WE
BA0/
BA1
Amax-A0
X
X
Action
Description
H
X
X
X
L
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
Termination Burst: Start
the Precharge
10
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Col Add.
A10
Write/WriteAP
Termination Burst: Start
Write(optional AP)
8
L
H
L
H
BA
Col Add.
A10
Read/ReadAP
Termination Burst: Start
Read(optional AP)
8,9
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Rev 1.0 / Apr. 2006
OP CODE
OP CODE
OP CODE
Device Deselect
Continue the Burst
Mode Register Set
ILLEGAL
Notes
13,14
13
13,14
13
13,14
13
19
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 3 of 4)
Current
State
Precharging
Row
Activating
Write
Recovering
Command
CS RAS CAS WE
BA0/
BA1
Amax-A0
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
No Operation:
Bank(s) idle after tRP
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation:
Bank(s) idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation:
Bank(s) idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,11,1
2
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation: Row
Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation: Row
Active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
Start Write:
Optional AP(A10=H)
L
H
L
H
BA
Col Add. A10
Read/ReadAP
Start Read: Optional
AP(A10=H)
L
H
H
H
X
X
No Operation
No Operation:
Row Active after tDPL
OP CODE
OP CODE
Mode Register Set
ILLEGAL
Notes
L
Rev 1.0 / Apr. 2006
OP CODE
Action
Description
13,14
13
13,14
13
13,14
13
9
20
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Write
Recovering
Write
Recovering
with Auto
Precharge
Refreshing
Mode
Register
Accessing
Command
CS RAS CAS WE
BA0/
BA1
Amax-A0
X
X
Action
Description
Device Deselect
No Operation:
Row Active after tDPL
Mode Register Set
ILLEGAL
Notes
H
X
X
X
L
L
L
L
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
4,12
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
4,9,12
L
H
H
H
X
X
No Operation
No Operation:
Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation:
Precharge after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
13
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation:
idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation:
idle after tRC
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add. A10
Write/WriteAP
ILLEGAL
13
L
H
L
H
BA
Col Add. A10
Read/ReadAP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation:
idle after 2 clock cycles
H
X
X
X
X
X
Device Deselect
No Operation:
idle after 2 clock cycles
Rev 1.0 / Apr. 2006
OP CODE
OP CODE
OP CODE
13,14
13
13,14
13,14
21
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
Rev 1.0 / Apr. 2006
22
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 1)
Current
State
Self
Refresh
CKE
Command
Previous Current
Cycle
Cycle
CS
RAS
CAS
WE
Notes
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with
Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with
No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
L
H
H
H
X
X
Power Down mode exit,
all banks idle
2
L
X
X
X
X
X
L
X
X
X
ILLEGAL
2
X
X
L
X
X
Power
Down
L
Deep
Power
Down
Action
BA0, AmaxBA1
A0
H
L
L
L
X
X
X
X
X
X
Maintain Power Down Mode
H
X
X
X
X
X
X
X
INVALID
1
L
H
X
X
X
X
X
X
Deep Power
Down mode exit
5
L
L
X
X
X
X
X
X
Maintain Deep
Power Down Mode
Rev 1.0 / Apr. 2006
23
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Current
State
All
Banks
Idle
Any State
other than
listed above
CKE
Command
Previous Current
Cycle
Cycle
CS
RAS
CAS
WE
BA0, AmaxBA1
A0
Action
H
H
H
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
L
L
L
H
X
H
H
L
L
L
L
OP CODE
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
X
X
Entry Self Refresh
H
L
L
L
L
L
OP CODE
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
H
H
X
X
X
X
X
X
Refer to operations of
the Current State
Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend
next cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend
next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
Refer to the idle State section
of the Current State
Truth Table
X
Notes
3
3
3
Auto Refresh
Mode Register Set
Refer to the idle State section
of the Current State
Truth Table
4
3
3
3
4
4
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Rev 1.0 / Apr. 2006
24
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Mobile SDR SDRAM OPERATION
State Diagram
Power
On
ACT :
Active
DPDSX
Precharge
All
Bank
DPDS :
Enter Deep
Power-Down
Auto
Refresh
DPDSX :
Exit Deep PowerDownEMRS
FA
RE
(E)MRS
REFS
IDLE
REFX
Power
Down
W
RI
TE
A
CK
EL
ow
ROW
ACTIVE
Write
E
CK w
Lo
WRITE
WRITE
SUSPEND
PRE
REFS :
Enter Self Refresh
REFSX :
Exit Self Refresh
READA :
Read with Auto
Precharge
WRITE :
Write w/o Auto
Precharge
WRITEA :
Write with Auto
Precharge
PR
E
PR
E
Automatic Sequence
REFA :
Auto Refresh
READ :
Read w/o Auto
Precharge
E
CK igh
H
C
H i KE
gh
READ
SUSPEND
Manual input
WRITE
with AP
WRITEA
SUSPEND
igh
READ
CK
EH
A
Write
AD
RE
Read
PREALL :
Precharge All
Banks
C
Hi KE
gh
E
CK igh
H
Active
Power
Down
ACT
E
CK w
Lo
READ
with AP
Read
C
Lo KE
w
PRE :
Precharge
E
CK w
Lo
DEEP
POWER
DOWN
Rev 1.0 / Apr. 2006
MRS :
Mode Register Set
E
CK igh
H
DS
DP
READA
SUSPEND
EMRS :
Ext. Mode Reg.
Set
Self
Refresh
C
Lo KE
w
(EXTENDED)
Mode Register
Set
Precharge
All
25
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
DESELECT
The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile
SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile SDRAM that is selected (CS = Low, RAS =
CAS = WE = High). This command is not an execution command. However, the internal operations continue. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not
affected. (see to next figure)
ACTIVE
The Active command is used to activate a row in particular bank for a subsequent Read or Write access. The value of
the BA0,BA1 inputs selects the bank, and the address provided on A0-A12(or the highest address bit) selects the row.
This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. (see to next figure)
CLK
CKE
CLK
CKE
High-Z
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0~A9,
A12
A0~A9,
A12
BA0,1
BA0,1
High-Z
RA
Row Address
BA
Bank Address
Don't Care
NOP command
Rev 1.0 / Apr. 2006
Don't Care
ACTIVATING A SPECIFIC
ROW IN A SPECIFIC BANK
26
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ / WRITE COMMAND
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input.
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and
address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open
for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank
and address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If auto-precharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open
for subsequent access.
CLK
CKE
CLK
CKE
H ig h -Z
CS
CS
RAS
RAS
CAS
CAS
WE
A0 ~ A8
WE
CA
E n a b le
A u to
P re c h a rg e A 0 ~ A 8
CA
D is a b le
A u to
A10
P re c h a rg e
A10
B A 0 ,1
H ig h -Z
BA
Read Com m and
O p e ra tio n
B A 0 ,1
D o n 't C a r e
BA
W rite C o m m a n d
O p e ra tio n
READ / WRITE COMMAND
Rev 1.0 / Apr. 2006
27
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and
the bank select address at the read command set cycle. In a read operation, data output starts after the number of
clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
tCK
CLK
Command
REA
D
NOP
NOP
tLZ
DQ
tOH
Do0
Do1
Do2
Do3
Do1
Do2
tAC
CL = 2
Command
REA
D
NOP
NOP
NOP
tLZ
tOH
Do0
DQ
Do3
tAC
CL = 3
Undefined
Don't Care
Read Burst Showing CAS Latency
Rev 1.0 / Apr. 2006
28
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ to READ
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
being truncated.
When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK
Command
Address
READ
BA, Col
a
NOP
NOP
READ’
BA, Col
b
CL =2
DQ
Do a0
Do a1
Do b0
Do b1
Do a1
Do b0
CL =3
DQ
Do a0
Don't Care
Consecutive Read Bursts
A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are
shown in Figure. Full-speed random read accesses within a page or pages can be performed as shown in Fig.
Rev 1.0 / Apr. 2006
29
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CLK
Command
Address
READ
READ
BA, Col
BA, Col
n
b
CL =2
DQ
Dob
Don
CL =3
Dob
Don
DQ
Don't Care
1) Don (or b): Data out from column n
2) BA, Col n (b) = Bank A, Column n (b)
3) Burst Length = 4 : 3 subseqnent elements of Data Out appear in the programmed order following Do n (b)
Non-Consective Read Bursts
CLK
Command
READ
READ
READ
READ
Address
BA, Col
BA, Col
BA, Col
BA, Col
n
x
g
b
CL =2
DQ
Don
Don'
Dox
Dox'
Dob
Dob'
Dog
Dog'
Don
Don'
Dox
Dox'
Dob
Dob'
Dog
CL =3
DQ
1) Don, etc: Data out from column n, etc
n', x', etc : Data Out elements, accoding to the programmd burst order
2) BA, Col n = Bank A, Column n
3) Burst Length = 1, 2, 4, 8 or full page in cases shown
4) Read are to active row in any banks
Dog’
Don't Care
Randum Read Bursts
Rev 1.0 / Apr. 2006
30
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ BURST TERMINATE
Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is
equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element.
CLK
Com m and
Address
READ
BURST
BA, Col
n
CL =2
DQ
Do n
Do n'
CL =3
Do n
DQ
Do n'
1) Do n : Data out from colum n n
2) BA, Col n = Bank A, Colum n n
3) Cases shown are bursts of 4, 8, or full page terminated after 2 data elements
Don't Care
Terminating a Read Burst
Rev 1.0 / Apr. 2006
31
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ to WRITE
Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in next fig.
CLK
Com m and
Address
READ
BURST
W RITE
BA, Col
BA, Col
n
b
CL = 2
DQ
Do n
Do n'
D I b0
D I b1
D I b2
DI b3
D I b0
D I b1
D I b2
DI b3
CL = 3
Do n
DQ
Do n'
1) DO n = Data O ut from colum n n; DI b = Data In to colum n b
Don't Care
Read to Write
Note :
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High
so that the output buffer becomes High-Z before data input.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided
that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data
input.
Rev 1.0 / Apr. 2006
32
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
READ to PRECHARGE
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note that part of the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time
(as described above) provides the same operation that would result from the same fixed-length burst with auto precharge.
The disadvantage of the PRECHARGEcommand is that it requires that the command and address buses be available at
the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
CLK
Com m and
READ
PRE
ACT
tRP
Address
Bank
A, All
BA, Col
n
BA,
Row
CL = 2
DQ
D on
CL = 3
Don
DQ
D on't Care
1) D O n = D ata O ut from colum n n
2) Note that Precharge m ay not be issued before tRAS ns after the ACTIVE com m and for applicable banks.
3) The ACTIVE com m and m ay be applied if tRC has been m et.
READ to PRECHARGE
Rev 1.0 / Apr. 2006
33
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
During WRITE bursts, the first valild data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will
be ignored. A full-page burst will continue until terminated.
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data provided coincident with the new command applies to the
new command.
CLK
Command
WRITE
Address
BA, Col
b
DQ
D Ib0
DQ
D Ib0
D Ib1
DQ
D Ib0
D Ib1
D Ib2
D Ib3
DQ
D Ib0
D Ib1
D Ib2
D Ib3
BL = 1
BL = 2
BL = 4
D Ib4
D Ib5
D Ib6
D Ib7
BL = 8
CL = 2 or 3
Basic Write timing parameters for
Don't Care
Write Burst Operation
Note :
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the
preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes,
the second write command has priority.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that
the other bank is in the bank active state. In the case of burst write, the second write command has priority.
Rev 1.0 / Apr. 2006
34
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
WRITE to WRITE
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,
a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of
the clock following the previous WRITE command. The first data-in element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The
new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of
desired data-in element.
CLK
Command
WRITE
WRITE
Address
BA, Col
BA, Col
b
DQ
D Ib0
n
D Ib1
D Ib2
D Ib3
D In0
D In1
D In2
D In3
DM
CL = 2 or 3
Don't Care
Concatenated Write Bursts
CLK
Com m and
W RITE
W RITE
W RITE
W RITE
W RITE
Address
BA, Col
BA, Col
BA, Col
BA, Col
BA, Col
DQ
b
D Ib
x
D I b'
D Ix
n
D I x’
D In
a
D I n’
D Ia
NOP
g
D I a’
D Ig
D I g’
DM
CL = 2 or 3
Don't Care
Random Write Cycles
Rev 1.0 / Apr. 2006
35
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
WRITE to READ
CLK
Command
WRITE
READ
Address
BA, Col
BA, Col
b
n
DIb0
DIb1
DIb0
DIb1
DOn0
DOn1
D On2
DOn0
DOn1
CL = 2
DOn3
BL = 4
DQ
DQ
DOn2
DOn3
CL = 3 BL = 4
Don't Care
The preceding burst write operation can be aborted and a new burst read operation can be started by inputting a new
read command in the write cycle. The data of the read command (READ) is output after the lapse of the /CAS latency.
The preceding write operation (WRIT) writes only the data input before the read command.
The data bus must go into a high-impedance state at least one cycle before output of the latest data.
Note:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst
write, data will continue to be written until one clock before the read command is executed.
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided
that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock
before the read command is executed (as in the case of the same bank and the same address).
Rev 1.0 / Apr. 2006
36
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). When the precharge command is executed for the same bank as the write command
that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is
unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a
WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.
CLK
Command
WRITE
Address
BA, Col
DQ
PRE
b
D Ib0
D Ib1
D IO b2
CL = 2 or 3
D Ib3
BL = 4
tDPL
Non-Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent
data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
CLK
Command
WRITE
Address
BA, Col
PRE
b
DIb0
DIb1
CL = 2 or 3
DIOb2
BL = 4
DQ
tDPL
Interrupting Write to Precharge
Rev 1.0 / Apr. 2006
37
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The most recently
registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used
to terminate write bursts.
CLK
CKE
High-Z
CS
RAS
CAS
WE
A0 ~ A9
A11, A12
Don't Care
BA0, 1
BURST TERMINATE COMMAND
Rev 1.0 / Apr. 2006
38
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is
completed.
If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,
A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of precharging.
CKE
High-Z
A10 defines the precharge
mode when a precharge
command, a read command
or a write command is
issued.
CS
RAS
If A10 = High when a
precharge command is
issued, all banks are
precharged.
CAS
If A10 = Low when a
precharge command is
issued, only the bank that is
selected by BA1/BA0 is
precharged.
WE
A0~A9
A11, A12
If A10 = High when read or
write command, autoprecharge function is
enabled.
While A10 = Low, autoprecharge function is
disabled.
A10
BA0,1
BA
Bank Address
Don't Care
PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command.
This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write
command. This precharges the bank/row after the Read or Write burst is complete.
Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is
desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.
The user must not issue another command to the same bank until the precharge time (tRP) is completed.
Rev 1.0 / Apr. 2006
39
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
AUTO REFRESH AND SELF REFRESH
Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two
ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:
- AUTO REFRESH.
This command is used during normal operation of the Mobile SDRAM. It is non persistent, so must be issued each time
a refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile SDRAM requires
AUTO REFRESH commands at an average periodic interval of tREF.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile SDRMA, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8*tREF.
-SELF REFRESH.
This state retains data in the Mobile SDRAM, even if the rest of the system is powered down. Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile SDRAM and may vary and may not meet tREF time.
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh
operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh
exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF
(max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all
refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting
from self-refresh mode.
Note: tREF (max.) / refresh cycles.
The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recommended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self
Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section.
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile
SDRAM operates refresh cycle asynchronously.
The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM
can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the
value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these
two modes.
Rev 1.0 / Apr. 2006
40
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CLK
CLK
CKE
CKE
High-Z
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0 ~ A9
A11, 12
A0 ~ A9
A11, 12
Don't Care
BA0, 1
Low-Z
Don't Care
BA0, 1
AUTO REFRESH COMMAND
SELF REFRESH ENTRY COMMAND
Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set.
Function
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Auto Refresh
H
H
L
L
L
H
X
X
Self Refresh Entry
H
L
L
L
L
H
X
X
Rev 1.0 / Apr. 2006
ADDR
A10/AP
BA
41
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
MODE REGISTER SET
The mode registers are loaded via the address bits.
BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register
description in the register definition section. The MODE REGISTER SET command can only be issued when all banks
are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met.
CLK
CKE
H igh-Z
CS
R AS
CAS
WE
C ode
A0 ~ A9
A11, 12
D on 't Care
C ode
BA0, 1
MODE REGISTER SET COMMAND
Note:
BA0=BA1=Low loads the Mode Register, whereas BA0=Low and BA1=High loads the Extended Mode Register.
CLK
Command
MRS
NOP
Valid
tMRD
Address
Code
Valid
Don't Care
Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - An)
tMRD DEFINITION
Rev 1.0 / Apr. 2006
42
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
POWER DOWN
Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in
progress. If power down occurs when all banks are idle, it is Precharge Power Down.
If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot
stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is
exited by setting CKE high while issuing a Device Deselect or NOP command.
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down
occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby.
DEEP POWER-DOWN
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
Mobile SDRAM are stopped and all memory data is lost in this mode.
All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER-DOWN
COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus
prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least
200 us. After 200 us a complete re-initialization routing is required defined for the initialization sequence.
CLK
CLK
CKE
CKE
CKE_Low
CS
CS
RAS
RAS
CAS
CAS
WE
WE
A0 ~ A9
A11, 12
A0 ~ A9
A11, 12
BA0, 1
BA0, 1
Don't Care
POWER-DOWN COMMAND
Rev 1.0 / Apr. 2006
CKE_Low
Don't Care
DEEP POWER-DOWN COMMAND
43
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
CLK
CKE
COMMAND
NOP
NOP
ACTIVE
All banks idle
tRCD
Input buffers gated off
Enter power-down mode.
tRAS
Exit power-down mode.
tRC
DON’T CARE
CLK
CKE
tCKS
tCKS
COMMAND
PCG
NOP
NOP
NOP
Input buffers gated off
Pre-charge all
Deep Power down entry
APCG
200us(min)
Deep Power down Exit
DON’T CARE
Rev 1.0 / Apr. 2006
44
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
tCK
tCH
CLK
tCKS
tCL
tCKS
tCKH
tRAS(MIN)
CKE
tCMS
tCMH
PRECHARGE
COMMAND
NOP
AUTO
REFRESH
NOP
or COMMAND
INHIBIT
Any COM
DQM
A0A9,Amax
ALL BANKS
A10
SINGLE BANK
tAS
BANKS
BA0, BA1
DQ
tAH
High-Z
Precharge all
active banks
Rev 1.0 / Apr. 2006
tRP
Enter self refresh mode
tXSR
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
45
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Power-up and Initialization
Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined manner. Power must be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time.
After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile
SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode
register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.)
And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR).
The following these cycles, the Mobile SDRAM is ready for normal opeartion.
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of
a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before
any activate command after the power up sequence. Any contents of the mode register be altered by re-programming
the mode register through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the Mobile SDRAM. This register
includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set
must be done before any activate command after the power up sequence. Any contents of the mode register be altered
by re-programming the mode register through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by
activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects
the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge
command is issued to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and
deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A9-A0 address inputs select
the sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not
selected, the row will remain active for subsequent accesses.
The length of burst and the CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE
and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A9-A0 address inputs select
the starting column location. The value on input A10 determines whether or not Auto Precharge is used.
If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
Rev 1.0 / Apr. 2006
46
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the
precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open
row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the
precharge command is issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If
A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst
Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts
a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the
bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is
issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When
this command is issued, data inputs can't be written with no clock delay.
If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled.
If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During
the write cycle, DQM mask data input with zero latency
CK
W RIT
CM D
DM
Data M asking
H i- Z
D0D IN0 D 1
DQ
Data M asking
0 Latency
D0 MK
D1
0 Latency
D 0D IN2 D1
D0 M K D 1
W rite Data M asking
CK
CMD
READ
DM
D ata M askin g
2 Laten cy
H i- Z
DQ
D0
D O U T 0D 1
D0
D O U T1D 1
D0
D D O T 2D 1
D0 MK
D1
R ea d D ata M askin g
Rev 1.0 / Apr. 2006
47
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Clock Suspend
The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation
stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation
of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures)
CLK
Command
RD
CKE
Masked by CKE
Internal CLK
Frozen Int. CLK by CKE
(CKE = Fixed Low)
Q1
DQ
Q2
Q3
Q4
Clock Suspend
Mode
Command
WR
CKE
Masked by CKE
Internal CLK
Frozen Int. CLK by CKE
(CKE = Fixed Low)
DQ
D1
D2
D3
D4
Clock Suspend
Mode
Rev 1.0 / Apr. 2006
48
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Power Down
The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping
CKE low, all of the input buffer except CKE are gated off.
Auto Refresh
The Auto Refresh command is used during normal operation and is similar to CBR refresh in Conventional DRAMs.
This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address
bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter.
Self Refresh
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM
operates refresh cycle asynchronously.
The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM
can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers.
The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature
Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of
PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two
modes.
Deep Power Down
The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory
array of the devices.
For more information, see the special operation for Low Power consumption of this data sheet.
Rev 1.0 / Apr. 2006
49
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole
memory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Current State
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Idle
Deep Power Down Entry
H
L
L
H
H
L
Deep Power Down
Deep Power Down Exit
L
H
X
X
X
X
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
CKE
CS
RAS
CAS
WE
tRP
Pre-charge
if needed
Rev 1.0 / Apr. 2006
Deep Power
Down Entry
50
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
Deep Power Down Mode (Continued)
Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command.
1. Maintain NOP input conditions for a minimum of 200usec
2. Issue precharge commands for all banks of the device
3. Issue 8 or more auto refresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down mode exit sequence.
CLK
CKE
CS
RAS
CAS
WE
200us
Deep Power Down
Exit
Rev 1.0 / Apr. 2006
tRP
All Banks
Precharge
tRC
Auto
Refresh
Auto
Refresh
Mode
Register
Set
Extended
Mode
Register
Set
New
Command
Accepted
Here
51
11
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLF(P)-xE Series
PACKAGE INFORMATION
54 Ball FBGA 0.8mm pitch (Size 8.0mm x 10.0mm, t=1.0mm max)
A1 INDEX MARK
8.00 Typ.
3.20
Unit
[mm]
0.80
1.60
0.80 Typ.
10.0
Typ.
Bottom
View
0.40
0.45
+/- 0.05
0.34
+/- 0.05
1.80
1.375
Rev 1.0 / Apr. 2006
0.80
Typ.
1.00 max
52