TP5208 64K SRAM ECHO PROCESSOR General Description Features The TP5208 is a developed processor for producing Built-in echo effects added to voice signals picked up by converters and memory realize a delay system microphone for karaoke applications. The IC has the with only a single chip largest memory among the digital delay series. As input/output Capable of filters, composing A-D and low-noise D-A and its design is aimed at high performance, it is best low-distortion delay system at low cost by ADM suited to provide radio cassette tape recorders and system (No = -88dB typ, THD = 0.17% typ) miniature unit audio system with quality echo function. Control mode selections available from 2 kinds: easy mode using parallel data and microcomputer With pins compatible with the Mitsubishi mode using serial data M65831AP/FP, M65830CP/FP, and M65843AP/FP, Sleep mode can be selected to stop IC functions the TP5208 is suitable for upgrading the series. Built-in automatic reset circuit Pin Configuration VDD 1 24 VCC XIN 2 23 LPF1 IN XOUT 3 22 LPF1 OUT D1/REQ 4 21 OP1 OUT D2/SCK 5 20 OP1 IN D3/DATA 6 19 REF D4/IDSW 7 18 CC1 TEST 8 17 CC2 EASY/U-COM 9 16 OP2 IN SLEEP 10 15 OP2 OUT D-GND 11 14 LPF2 IN A-GND 12 13 LPF2 OUT 24 PINS DIP/SOP Data Sheet - Version 1.1 January 2005 Page 1 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Pin Description Pin No. 1 2 3 Symbol VDD XIN XOUT Pin Name Digital VDD Oscillator input Oscillator input I/O I O 4 D1/REQ Delay1/Request I 5 D2/SCK Delay2/Shift clock I 6 D3/DATA Delay3/Serial data I 7 D4/IDSW Delay4/ID switch I 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TEST EASY/U-COM SLEEP DGND AGND LPF2 OUT LPF2 IN OP2 OUT OP2 IN CC2 CC1 REF OP1 IN OP1 OUT LPF1 OUT LPF1 IN VCC Test EASY/U-COM Sleep Digital GND Analog GND Low pass filter2 output Low pass filter2 input OP-AMP2 output OP-AMP2 input Current control 2 Current control 1 Reference OP-AMP1 input OP-AMP1 output Low pass filter1 output Low pass filter1 input Analog VCC I I I O I O I I O O I - Description Supply voltage Connects to 2MHz ceramic filter Easy mode: inputs D1 data U-COM mode: inputs request data Easy mode: inputs D2 data U-COM mode: inputs shift clock Easy mode: inputs D3 data U-COM mode: inputs shift data Easy mode: inputs D4 data U-COM mode: controls ID code L = normal mode H = Easy mode; L = U-COM mode H = sleep mode; L = normal mode Connects to analog GND at one point Connects to analog GND Forms low pass filter with external C, R Forms integrator with external C, R = 1/2 VCC Forms integrator with external C, R Forms low pass filter with external C, R Supply voltage Functional Description EASY Mode (EASY/U-COM = H) D4 D3 D2 D1 fs Td L L L L 666 12.3 L L L H 666 24.6 L L H L 666 36.9 L L H H 666 49.2 L H L L 666 61.4 L H L H 666 73.7 L H H L 666 86.0 L H H H 666 98.3 H L L L 333 110.6 H L L H 333 122.9 H L H L 333 135.2 H L H H 333 147.5 H H L L 333 159.7 H H L H 333 172.0 H H H L 333 184.3 H H H H 333 196.6 Data Sheet - Version 1.1 January 2005 NOTES: f s: Sampling Frequency (KHz) Td: Delay Time (msec) Page 2 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR U-COM Mode (EASY/U-COM = L) H Delay Time = SLEEP Mode H ID Code = MUTE This timing chart shows that delay time is set by serial data from U-COM. DATA signal is latched at the falling edge of SCK signal; the last ten data are set at the rising edge of REQ signal when ID codes are satisfied. ID1, ID3: L ID2: H ID4: equal to IDSW REQ, SCK, DATA Input Timing Symbol Parameter t1 ds t2 t3 t4 t5 SCK Pulse Width SCK Pulse Duty DATA Setup Time DATA Hold Time REQ Hold Time REQ Pulse Width Min 250 100 100 100 250 Limit Typ 50 t1/2 t1/2 - Max - Unit ns % ns ns ns ns MUTING EASY mode Automatic mute upon changing delay time, canceling SLEEP mode and power-on. U-COM mode MUTE = H: mute MUTE = L: automatic mute Data Sheet - Version 1.1 January 2005 Page 3 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Automatic Mute 1. Upon Changing Delay Time Delay Signal Before Change Mode 2. Delay Signal After Change Mode Upon Canceling SLEEP Mode Delay Signal 3. Upon Power-On Delay Signal Power On SLEEP Mode SLEEP data is H: clock and RAM stop to reduce circuit current (SLEEP mode) L: normal operation System Reset Automatically reset power-on. Data Sheet - Version 1.1 January 2005 The reset time is about 120msec and the delay time is set at 147.5msec. Page 4 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Absolute Maximum Ratings (Ta = 25℃, unless otherwise noted) Parameter Supply Voltage Supply Current Power Dissipation Operating Temperature Storage Temperature Symbol Vcc Icc Pd Topr Tstg Ratings 6.5 100 1.7 -20 ~ +75 -25 ~ +125 Unit V mA W ℃ ℃ Recommended Operating Conditions Parameter Supply Voltage Supply Voltage Difference Voltage Clock Frequency High Input Voltage Low Input Voltage Symbol VCC VDD VCC - VDD fck VIH VIL Limit Min 4.5 4.5 -0.3 1 0.7VDD - Typ 5 5 0 2 - Max 5.5 5.5 0.3 3 0.3VDD Unit V V V MHz V V AC Electrical Characteristics (VCC = 5.0V, fin = 1KHz, Vi = 100mVrms, fck = 2MHz, Ta = 25℃, unless otherwise noted) Parameter Circuit Current Voltage gain Maximum Output Voltage Output Distortion Mute Time Output Noise Voltage Symbol Icc Gv Vomax THD TMUTE No Limit Min 1.0 508 508 - Typ 36 -0.5 1.6 0.17 0.4 528 528 -88 Max 50 2.5 0.8 1.2 548 548 -80 Unit mA dB Vrms % % ms ms dBV Test Condition No Signal RL = 47KΩ THD = 10% fs = 666KHz 30KHz L.P.F. fs = 333Khz Upon Changing Delay Time Upon Canceling Sleep Mode DIN-AUDIO (fs = 333KHz) DC Electrical Characteristics Parameter Supply Voltage Supply Current High Input Voltage Low Input Voltage Data Sheet - Version 1.1 January 2005 Symbol Vcc Icc VIH VIL Limit Min 4.5 0.7VDD - Typ 5 60 - Max 5.5 80 0.3VDD Page 5 of 7 Unit V mA V V http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Application EASY Mode IN 1u 22nF 100u 20k 0.01u 30k 3k 22nF 0.01u 10k 10k 10k 0.047u 0.047u 47u 620 CC2 EASY/u_com OP2_in OP2_out TEST SLEEP DGND AGND 3 4 5 6 7 8 9 10 11 12 2M Hz 100p OUT LPF2_out LPF2_in CC1 2 LPF1_out 1 0.1u 2.7k 13 D4 14 REF 15 D3 16 OP1_in 17 D2 18 D1 19 XOUT 20 LPF1_in 21 XIN 22 Vcc 23 1u VDD 24 10k 2.2nF 620 0.33u 0.33u 2.2nF OP1_out 1u SETING DELAY TIME 100p U-COM Mode 20k IN 1u Data Sheet - Version 1.1 January 2005 10k 0.01u 0.047u 47u 10k 2.2nF 620 0.33u 0.33u 1u 2.7k OUT 2.2nF 8 9 13 LPF2_out 7 14 AGND 6 15 LPF2_in EASY/u_com OP2_in 5 CC2 TEST 4 CC1 3 REF 2 OP1_out 1 LPF1_out IDSW 16 DATA 17 SCK 18 REQ 19 DGND 20 XOUT 21 XIN 22 VDD LPF1_in 23 0.047u OP2_out 620 Vcc 100u 0.1u 22nF 10k 10k 24 3k SLEEP 22nF 0.01u 30k OP1_in 1u 10 11 12 2M Hz 100p 100p u-COM Page 6 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Package Information TP5208P (24-pin DIP) ◎Headquarters 5 F, No. 10, Prosperity Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C. Tel.: +886-3-563-2515 Fax: +886-3-564-1728 ◎Taipei Office 2 F, No. 26, Lane 583, Ruiguang Rd., Neihu, Taipei, Taiwan 114, R.O.C. Tel.: +886-2-2627-6222 Fax: +886-2-2657-0256 ◎Shenzhen Office Room 802, Tower A, World Trade Plaza, No. 9, Fuhong Rd., Futian, Shenzhen, China Tel.: +86-755-8367-9985 Fax: +86-755-8367-9518 Data Sheet - Version 1.1 January 2005 Page 7 of 7 http://www.topro.com.tw