Am79Q4457/5457 Quad Subscriber Line Audio Processing CircuitNon-Programmable (QSLAC™-NP) Devices DISTINCTIVE CHARACTERISTICS n n n n Performs the function of four Codec/Filters n A-law or µ-law coding Additional Am79Q4457 device capabilities (per channel, set external) Single PCM port — Three selectable transmit gains — Up to 4.096 MHz operation (64 channels) — Three selectable receive gains Hardware programmable (via external components) — Transhybrid balance impedance — Transmit and receive gains — Two selectable balance networks n n n n — Simple serial control interface Separate PCM and Master clocks 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz master clock options — Internal timing automatically adjusted based on MCLK and frame sync signal Low power 5.0 V CMOS technology 5.0 V only operation GENERAL DESCRIPTION The Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) device integrates the key functions of analog linecards into a high-performance, four-channel Codec/Filter device. The QSLAC-NP devices are based on the proven design of the reliable Am79C02/03/031(A) Dual Sub scr ibe r Line Aud io-Processing Circu it (DSLAC ™ ) devices, and the Am79C202 Advanced Subscriber Line Audio-Processing Circuit (ASLAC ™) device. The advanced architecture of the QSLAC-NP devices implements four independent channels in a single integrated circuit, providing a cost-effective solution for the audio-processing function of Plain Old Telephone Service (POTS) linecards. The Am79Q4457/5457 QSLAC-NP device provides four industry-standard Codec/Filter devices in a single integrated circuit. The Am79Q4457/5457 device provides a transmit and receive frame synchronization input per channel. A-law or µ-law compression is selected via a device pin. Although the name and logo have changed, the data contained herein remains the same as the most recent AMD revision of this document. In addition, the Am79Q4457 device provides the ability to select one of three independent gain settings (both transmit and receive) and one of two balance networks on a per-channel basis. The transmit and receive gain leve ls ar e set once fo r th e device via exte r na l components. Gain level selection and the balance network selection is achieved through an integrated serial shift register and latch per channel. The Am79Q5457 device provides four industr ystandard Codec/Filter devices in a 32-pin PLCC or 44pin TQFP package. The Am79Q4457 device provides four industr y-standard Codec/Filter devices and selectable gain and balance functions in a 44-pin PLCC or 44-pin TQFP package. Advanced submicron CMOS technology enables the Am79Q4457/5457 QSLAC-NP device to have both the functionality and the low power consumption required in linecard designs, maximizing linecard density at a minimum cost. When used with four Legerity SLICs, a QSLAC-NP device provides a complete solution to the BORSCHT function of a POTS linecard. Publication# 20031 Rev: D Amendment: /0 Issue Date: January 2000 TABLE OF CONTENTS Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams (PLCC packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams (44-pin TQFP packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply for the Am79Q4457/5457 Devices: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics over operating ranges (unless otherwise noted) . . . . . . . . . . . . . . . . . 12 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Variation of Gain with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Total Distortion, Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Discrimination against 12 kHz and 16 kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . 19 Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Switching Characteristics over operating ranges (unless otherwise noted). . . . . . . . . . . . . . . . . 20 Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input and Output Waveforms for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Control Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCM Highway Timing (Short Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM Highway Timing (Long Frame Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating The QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control of the Am79Q4457/5457 QSLAC-NP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Parallel Control (Am79Q5457 Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Control Register (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Setting Gain Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q4457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Gain Settings for the Am79Q5457 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Calculation of Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Considerations For Connection To Slics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Effects of CRX and CTX Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Placement of the Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SLIC Connection Consideration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PL044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PQT044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2 Am79Q4457/5457 Data Sheet List of Figures Figure 1. Figure 2. Figure 3a. Figure 3b. Figure 4a. Figure 4b. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9a. Figure 9b. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 A-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 m-law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . 16 A-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 m-law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . 17 Discrimination against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Am79Q4457 QSLAC-NP Device Serial Control Interface . . . . . . . . . . . . . . . . . 26 QSLAC-NP Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Am79Q4457JC Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Am79Q5457 Device (Channel 1 Shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Am79Q4457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Am79Q5457JC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Balance Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alternate Balance Network Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 List of Tables Table 1. Table 2. Table 3. 0 dBm0 Voltage Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmit Gain Select (Am79Q4457 Device Only). . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Gain Select (Am79Q4457 Device Only) . . . . . . . . . . . . . . . . . . . . . . . . 29 SLAC Products 3 BLOCK DIAGRAM Quad SLAC-NP Device Single PCM Highway Analog I1 IN1 I2IN1 VOUT1 *2 I1IN2 I2IN2 VOUT2 *2 Signal Processing Channel 2 (CH 2) *2 Signal Processing Channel 3 (CH 3) *2 Signal Processing Channel 4 (CH 4) I1IN3 I2IN3 VOUT3 I1 IN4 I2IN4 VOUT4 DXA Signal Processing Channel 1 (CH 1) DRA TSCA PCM Interface A/µ Clock & Reference Circuits FSR1–4 FSX1–4 PCLK MCLK IREF1 IREF2*2 IREF3*2 VREF1 VREF2*2 VREF3*2 PDN1–4*1 Control Interface 20031A-001 VCCA AGND VCCD DGND CO CS1–4 CI CCLK *2 *2 *2 *2 Notes: *1 = Am79Q5457 only. *2 = Am79Q4457 only. 4 Am79Q4457/5457 Data Sheet ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79Q4457/5457 J C TEMPERATURE RANGE *C = Commercial (0°C to 70°C; Relative Humidity = 15% to 95%) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) —Am79Q4457 Only 32-Pin Plastic Leaded Chip Carrier (PL 032) —Am79Q5457 Only V = 44-Pin Thin Quad Flat Pack (PQT 044) —Am79Q4457 and Am79Q5457 DEVICE NUMBER/DESCRIPTION Am79Q4457/5457 Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Device Valid Combinations Valid Combinations Am79Q4457 JC Am79Q5457 JC Am79Q4457 VC Am79Q5457 VC Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military–grade products. Note: * The performance specifications contained in this data sheet for 0°C to +70°C operation are guaranteed by 100% factory testing at 65°C. Extended temperature range specifications (–40°C to +85°C) are guaranteed by characterization and periodic sampling of production units. SLAC Products 5 CS4 MCLK PCLK VREF2 CS1 CS2 CS3 I1IN1 VOUT1 I2IN1 VREF1 CONNECTION DIAGRAMS (PLCC PACKAGES) Top View 6 5 4 3 2 1 44 43 42 41 40 I1IN2 VOUT2 I2IN2 IREF2 39 38 37 36 35 34 33 32 31 30 29 28 CI CCLK TSCA DGND CO DXA VCCD DRA FSX4 FSR4 FSX3 FSR3 FSX2 FSR1 FSX 1 FSR 2 PDN1 PDN2 PDN3 MCLK VOUT1 PDN4 20031A-002 VREF1 I1IN4 VOUT4 I2IN4 AGND IREF3 I2IN3 VOUT3 I1IN3 A/µ RSRVD VCCA IREF1 VREF3 7 8 9 10 11 Am79Q4457JC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 4 3 2 1 32 31 30 I1IN1 5 29 PCLK I1IN2 VOUT2 6 28 TSCA 7 27 DGND 8 26 VCCA 25 DXA VCCD AGND VOUT3 10 24 DRA 11 23 FSR1 I1IN3 12 22 FSX1 I1IN4 13 21 FSR2 IREF1 Am79Q5457JC 9 FSX2 FSR3 FSX3 FSR4 FSX4 A/µ VOUT4 14 15 16 17 18 19 20 20031A-003 Note: Pin 1 is marked for orientation. 6 Am79Q4457/5457 Data Sheet MCLK PCLK CS4 CS2 CS3 CS1 VREF2 VOUT1 I2IN1 VREF1 I1IN1 CONNECTION DIAGRAMS (44-PIN TQFP PACKAGES) Top View 44 43 42 41 40 39 38 37 36 35 34 I1IN2 1 33 CI VOUT2 2 32 CCLK I2IN2 3 31 TSCA IREF2 VCCA IREF1 4 30 DGND 5 29 CO 28 AGND 7 27 DXA VCCD IREF3 I2IN3 8 26 DRA 9 25 VOUT3 10 24 FSR1 FSX1 I1IN3 11 23 FSR2 Am79Q4457VC 6 FSR3 FSX2 PCLK MCLK FSX3 PDN2 PDN3 PDN4 A/U N/C N/C FSX4 FSR4 VREF3 VREF1 PDN1 I2IN4 VOUT4 VOUT1 N/C I1IN1 I1IN4 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 I1IN2 1 33 N/C VOUT2 N/C 2 32 N/C 3 31 TSCA N/C 4 30 DGND VCCA 5 29 N/C IREF1 6 28 DXA AGND N/C 7 8 27 VCCD 26 DRA N/C 9 25 FSR1 VOUT3 10 24 FSX1 I1IN3 11 23 FSR 2 Am79Q5457VC FSX3 FSR3 FSX2 FSR4 FSX4 N/C A/U VOUT4 N/C N/C I1IN4 12 13 14 15 16 17 18 19 20 21 22 Note: Pin 1 is marked for orientation. SLAC Products 7 PIN DESCRIPTIONS Pin Name Type Description A/µ Input A-law or µ-law Select. The A-law/µ-law select pin is used to inform the QSLAC-NP device which compression/expansion standard to use. A logic Low signal (0 V) on the A-law/µ-law pin selects the µ-law standard, and a logic High (+5 V) selects the A-law standard. The A-law/µ-law input can be connected to VCCD directly, eliminating the need for a external pull-up resistor. Therefore, the device can be programmed for A-law by connecting the A/µ input to V CCD and can be programmed for µ-law by connecting the device pin to DGND. CCLK Input (Am79Q4457 Device Only) Control Clock. The Control Clock input shifts data into and out of the Serial Interface of the QSLAC-NP device. The maximum clock rate is 4.096 MHz. (Serial control on the Am79Q4457 device only.) CI Input (Am79Q4457 Device Only) Control Data. Control Data is written into the selected Channel Control Register (see CSN) via the CI pin. The data is shifted in the Most Significant Bit (MSB) first. The data rate is determined by CCLK. (Serial control on the Am79Q4457 device only.) CO Output (Am79Q4457 Device Only) Control Data. Control Data is read in serial form from the Enabled Channel Register (see CSN) via the CO pin. Data is shifted out with the MSB first. The data rate is determined by the Control Clock (CCLK). (Serial control available on the Am79Q4457 device only.) CS1, CS2, CS3, CS4 Input (Am79Q4457 Device Only) Chip Select. The Chip Select (CSN) input (active Low) enables Channel N of the device so that control data can be written to or read from the channel. CS1 enables Channel 1, CS2 enables Channel 2, CS3 enables Channel 3, and CS4 enables Channel 4. (Serial control on the Am79Q4457 device only.) DRA Input PCM. The PCM data for Channels 1, 2, 3, and 4 is serially received on the DRA port during the time slot determined by the Receive Frame Sync Signal (FSRN). Data is always received with the MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate. Output PCM. The transmit data from Channels 1, 2, 3, and 4 is sent serially out the DXA port during time slots determined by the Transmit Frame Sync (FSXN ) signal for that channel. Data is always transmitted with the MSB first. The output is available every 125 µs and the data is shifted out in 8-bit bursts at the PCLK rate. DXA is high impedance between time slots. Input Receive Frame Sync. The Receive Frame Sync pulse for Channel N is an 8 kHz signal that identifies the receive time slot for Channel N on a system’s receive PCM frame. The QSLACNP device references channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long-Frame Sync and Short-Frame Sync modes available on the QSLAC-NP device. Input Transmit Frame Sync. The Transmit Frame Sync pulse for Channel N is an 8 kHz signal that identifies the transmit time slot for Channel N during the system’s transmit PCM frame. The QSLAC-NP device references individual channel time slots with respect to this input, which must be synchronized to PCLK. There are both Long Frame Sync and Short Frame Sync modes available on the QSLAC-NP device. DXA FSR1, FSR2, FSR3, FSR4 FSX1, FSX2, FSX3, FSX4 I1IN1, I2IN1, I1IN2, I2IN2, I1IN3, I2IN3, I1IN4, I2IN4 IREF1, IREF2, IREF3 8 Current (I2IN on Am79Q4457 Device Only) Analog Inputs. The analog voice band voltage signal is applied to the IIN input of the QSLAC-NP device through a resistor. The IIN input is a virtual AC ground input (summing node). IIN is biased at the voltage on the VREF1 pin. The audio signal is sampled, digitally processed and encoded, and then made available at the TTL-compatible PCM output (DXA). There are two inputs per channel in the 44-pin QSLAC-NP device. I1IN1 is input 1 of Channel 1 and I2IN1 is input 2 of Channel 1; I1IN2 and I2IN2 are inputs 1 and 2 of Channel 2; I1IN3 and I2IN3 are inputs 1 and 2 of Channel 3; and I1IN4 and I2IN4 are inputs 1 and 2 of Channel 4. See Figure 9 for more details. Output (IREF2 and IREF3 on Am79Q4457 Device Only). Reference Current. The IREF outputs are biased at the internal reference voltage, which is the same as the voltage on the VREF1 pin. A resistor placed from IREFn (n = 1, 2, or 3) to ground sets one of three reference currents used by the Analog-to-Digital (Ato-D) converter to encode the signal current present on IyINn (n = channel number [1 to 4] and y = input number [1 or 2]) into digital form. By setting different levels for I REFx, three different transmit gains can be achieved. The reference current used by a channel A-to-D is determined by the Transmit Gain Select (TGS) bits in the channel control register. The absolute transmit gain is determined by the reference current selected and the input resistance connected to IIN. See Figure 9 and Table 2 for more details. Am79Q4457/5457 Data Sheet Pin Name Type Description Input Master Clock. The Master Clock frequency can be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz for use by the digital signal processor. Using the Transmit Frame Sync (FSX) Inputs, the QSLAC-NP device determines the MCLK frequency and makes the necessary internal adjustments automatically. The master clock frequency must be an exact integer multiple of the frame sync frequency. Input PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 4.096 MHz, and the minimum clock frequency is 256 kHz, due to a single PCM highway. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The digital signal processor clock can be derived from PCLK by connecting MCLK and PCLK together. See frequency restrictions under MCLK. PDN1, PDN2, PDN3, PDN4 Input (Am79Q5457 Device Only) Power Down. The power-down inputs provide direct control over the channel circuitry. A logic High on PDN n (n = 1 to 4) powers Channel n down while a logic Low powers the channel up. PDN1 controls Channel 1, PDN2 controls Channel 2, PDN3 controls Channel 3, and PDN4 controls Channel 4. The PDN pins are used in the initialization of the internal circuitry. Refer to the Power-Up Sequence section on 24 for initialization using the PDN pins. TSCA Output Time Slot Control. The Time Slot Control output is an open drain output (requiring a pull-up resistor to VCCD) and is normally inactive (high impedance). TSCA is active (Low) when PCM data is transmitted on the DXA pin for any of the four channels. Voltage Analog Outputs. The received digital data at DRA is processed and converted to an analog signal at the VOUT pin. VOUT1 is the output from Channel 1; VOUT2 is the output for Channel 2; VOUT3 is the output from Channel 3; and VOUT4 is the output for Channel 4. The VOUT voltages are referenced to V REF1. Output Voltage Reference. The V REF1 output is provided in order for an external 0.1-µF capacitor (or larger) to be connected from VREF1 to ground, filtering noise present on the internal voltage reference. VREF1 is buffered before it is used by internal circuitry. The voltage on V REF1 is nominally 2.1 V, and the output resistance is 115 kW. The leakage current in the capacitor must be less than 20 nA. A larger filter capacitor will provide better filtering, but will increase the settling time. Input (Am79Q4457 Device Only). Voltage Reference. VREF2 and VREF3 are buffered and are available as alternative reference voltages for the channel Digital-to-Analog (D-to-A) converters. The D-to-A converters decode the received PCM data into analog voltage levels. VREF1, VREF2, or VREF3 can be selected by the Receive Gain Select (RGS) bits as the reference for the D-to-A converter in order to select the receive gain of the channel. MCLK PCLK VOUT1, VOUT2, VOUT3, VOUT4 VREF1 VREF2, VREF3 Power Supply for the Am79Q4457/5457 Devices: AGND DGND VCCA VCCD Analog Ground Digital Ground +5.0 V Analog Power Supply +5.0 V Digital Power Supply Two separate power supply inputs are provided to allow for noise isolation and good power supply decoupling techniques; however, the two pins have a low impedance connection inside the part. For best performance, all of the +5.0 power supply pins should be connected together at the connector of the printed circuit board, and all of the grounds should be connected together at the connector of the printed circuit board. SLAC Products 9 FUNCTIONAL DESCRIPTION The QSLAC-NP device performs the Codec/Filter and two-to-four-wire conversion function (requires external balance impedance) required of the subscriber line interface circuitry in telecommunications equipment. These functions involve converting an audio signal into digital PCM samples and converting digital PCM samples back into an audio signal. During conversion, digital filters are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. The transmit and receive gain can be altered on a perchannel basis and the per-channel balance impedance can be selected between two external impedances by the Am79Q4457 QSLAC-NP device. Control of these functions is provided by an integrated serial shift register and latch per channel. These additional functions are available on the Am79Q4457 device only. 10 Data transmitted or received on the PCM highway is an 8-bit, A-law or µ-law companded code. The QSLAC-NP device is compatible with both codes. Code selection is provided via a device pin (A/µ). The 8-bit codes appear 1 byte per time slot. The PCM data is read and written to the PCM highway in time slots determined by the individual Frame Sync signals (FSRN and FSXN) at rates from 256 kHz to 4.096 MHz. Both Long- and ShortFrame Sync modes are available in the QSLAC-NP device. Two configurations of the QSLAC-NP device are offered as pictured previously. The Am79Q4457 dev ic e w i t h s e r i a l c o n t r o l o f g a i n a n d b a la n c e impedance is available in the 44-pin PLCC package and 44-pin TQFP package. The Am79Q5457 device without serial control is available in a 32-pin PLCC package and 44-pin TQFP package. Serial Control Package Yes 44 PLCC Am79Q4457 JC No 32 PLCC Am79Q5457 JC Yes 44 TQFP Am79Q4457 VC No 44 TQFP Am79Q5457 VC Am79Q4457/5457 Data Sheet Part Number ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . –60°C < TA < +125°C VCCA, Analog Supply . . . . . . . . . . . . . . . . VCCD ±10 mV Ambient Operating Temp . . . . . . . –40°C < TA < +85°C VCCA, Analog Supply . . . . . . . . . . . . . +5.0 V ± 0.25 V Ambient Relative Humidity . . . . . . . . . . . . 5% to 95% VCCD, Digital Supply . . . . . . . . . . . . . +5.0 V ± 0.25 V (non condensing) DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V VCCA with respect to VCCD . . . . . . . . . . . . . . . . ±50 mV AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mV VCCA with respect to AGND. . . . . . . . . –0.4 V to +7.0 V Ambient Temperature . . . . . . . . . . . .0°C < TA < +70°C VCCD with respect to DGND . . . . . . . . –0.4 V to +7.0 V Ambient Relative Humidity . . . . . . . . . . . .15% to 95% AGND with respect to DGND . . . . . . . . . . . . . . ±0.4 V IIN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Other pins with respect to DGND . . . . . .–0.4 V to VCCD +0.4 V Latch-up immunity (any pin). . . . . . . . . . . . . . ±30 mA Operating Ranges define those limits between which functionality of the device is guaranteed by 100% production testing. Specifications in this data sheet are guaranteed by testing from 0° C to +70° C. Performance from –40 °C to +85 °C is guaranteed by characterization and periodic sampling of production units. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. SLAC Products 11 ELECTRICAL CHARACTERISTICS over operating ranges (unless otherwise noted) Typical values are for TA = 25°C and nominal supply voltages. Minimum and maximum specifications are over the temperature and supply voltage ranges shown in Operating Ranges. Symbol Parameter Descriptions Min VIL Input Low voltage VIH Input High voltage 2.0 IIL Input leakage current –10 VOL Typ Output High voltage All digital outputs (IOH = 400 µA) 2.4 IOL Output leakage current (H I = Z State) –10 IIR Analog input current range, RREF = 13 kΩ IIOS Offset current allowed on IIN –1.6 –16 Unit 0.8 V V Output Low voltage TSCA (IOL =14 mA) All other digital outputs (IOL = 2 mA) VOH Max 10 µA 0.4 0.4 V V 10 µA V ±40 µA 1.6 µA 16 mV 4 Ω VIOS Offset voltage on IIN relative to VREF1 ZOUT VOUT output impedance ZREF1 VREF1 output impedance (F < 3400 Hz) 80 150 kΩ IOUT VOUT output current (F<3400 Hz) (Note 1) –4 4 mA 40 mV 240 90 6 mW mW mW 1 VOR VOUT voltage range VOOS VOUT offset voltage (Relative to VREF1) PD Power dissipation CI Input capacitance (Digital) CO Output capacitance (Digital) PSRR ±1.584 –40 All channels active 1 channel active All channels inactive (Note 2) 180 60 1 15 15 Power supply rejection ratio (1.02 kHz, 100 mVrms, either path, GX = GR = 0 dB) 40 V pF pF dB Notes: 1. When the QSLAC-NP device is in the Inactive mode, the analog output (VOUT) will present a VREF1 DC output level through a ~400-kΩ resistor. 2. Power dissipation in the Inactive mode is measured with all digital inputs at VIH = VCC and VIL = DGND, and with no load connected to VOUT1, VOUT2, VOUT3, or VOUT4. 12 Am79Q4457/5457 Data Sheet Transmission Characteristics Table 1. 0 dBm0 Voltage Definitions Transmit Receive A-law digital mW or equivalent (0 dBm0) Signal at Digital Interface 0.6776/Gt 0.6776 x Gr Vrms 1 µ-law digital mW or equivalent (0 dBm0) 0.6778/Gt 0.6778 x Gr Vrms 1 Description Test Conditions Gain accuracy, either path Min Unit Max Unit –0.25 +0.25 dB –0.35 +0.35 dB –0.125 +0.125 dB 2 –46 dB 3 –55 –78 12 –68 16 dBm0 dBm0p dBrnc0 dBm0p dBrnc0 4 4 4 4 4 1014 Hz Average –76 –76 dBm0 dBm0 5 1014 Hz Average –78 –78 dBm0 dBm0 5 6, 7 0 dBm0, 1014 Hz 0°C to 85°C Am79Q5457, or Am79Q4457, Gt = Gt1, Gr = Gr1 –40°C (All), or Am79Q4457, Gt = Gt2 or Gt = Gt3, or Gr = Gr2 or Gr = Gr3 Attenuation distortion 300 Hz to 3 kHz Typ Single frequency distortion Idle channel noise Analog out Analog out Analog out Digital out Digital out Crosstalk between channels Note digital input = 0 analog VIN = 0 unweighted A-law µ-law A-law µ-law Note 0 dBm0 TX or RX to TX TX or RX to RX End-to-end group delay PCLK ≥ 1.53 MHz 540 µs Analog-to-analog 3 dBm0, 1004 Hz input, C-weight 0.5 dB overload compression loss 6 dBm0, 1004 Hz input, C-weight 2 dB relative to 0 dBm0 loss 9 dBm0, 1004 Hz input, C-weight 5 dB 500 Notes: 1. Gt and Gr are defined in the Transmit Gain Select and Receive Gain Select tables on 28 and 29. Gr must be in the range: 0.4 ≤ Gr ≤ 1. RREF must be in the range: 13K ≤ R REF ≤ 26K, where R REF is RREF1, R REF2A + RREF2B, or R REF3A + RREF3B. 2. Also see the following Attenuation Distortion figure. 3. Measured with a 0 dBm0 input signal, 300 Hz to 3400 Hz; output measured at any other frequency 300 Hz to 3400 Hz. 4. No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0. 5. The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, fN = 3300 Hz, f1 = 300 Hz, and the frequency points (fj, j = 2..N) are closely spaced: 1----• C (fj ) 20 1----• C ( fj – 1 ) 20 • log ∑ --------------------------------------------------------2 10 Average = 20 • log + 10 fj -------f j–1 j -------------------------------------------------------------------------------------------------f N log ----f 1 6. See following Group Delay Distortion figure also. 7. The End-to-End Group Delay is the sum of the transmit and receive group delays where both are measured using the same time slot. SLAC Products 13 Attenuation Distortion If a capacitive coupling network is used in series with either the transmit input or the receive output of the part, that network must have a corner frequency of less than 20 Hz to meet the template in Figure 1. If the corner frequency is above 20 Hz, the loss in the coupling network must be taken into account. QSLAC-NP Device Specification 2 Transmit curve 1.6 dB Attenuation (dB) Receive curve 1 dB 1 0.75 dB 0.125 0 Transmit only – 0.125 200 300 3000 3400 Frequency (Hz) 20013A-006 Figure 1. Attenuation Distortion 14 Am79Q4457/5457 Data Sheet Group Delay Distortion For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value of the group delay is taken as the reference. The signal level should be 0 dBm0. 420 QSLAC-NP Device Specification (Either Path) Delay (µs) 175 125 90 0 500 600 1000 2600 2800 3000 Frequency (Hz) 20013A-007 Figure 2. Group Delay Distortion SLAC Products 15 Variation of Gain with Input Level The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. QSLAC-NP Device Specification 1.5 0.55 0.25 Gain dB 0 –55 –50 –40 –10 +3 0 Input Level dBm0 –0.25 –0.55 –1.5 19256A-008 Figure 3a. A-law Gain Tracking with Tone Input (Both Paths) QSLAC-NP Device Specification 1.4 0.45 0.25 Gain dB 0 –55 –50 –37 –10 0 +3 Input Level dBm0 –0.25 –0.45 –1.4 19256A-009 Figure 3b. µ-law Gain Tracking with Tone Input (Both Paths) 16 Am79Q4457/5457 Data Sheet Total Distortion, Including Quantizing Distortion The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. QSLAC-NP Device Specification 35.5 35.5 30 Signal-to-Total Distortion (dB) 25 –45 –40 –30 +3 Input Level (dBm0) 20013A-010 Figure 4a. A-law Total Distortion with Tone Input (Both Paths) QSLAC-NP Device Specification 35.5 35.5 31 Signal-to-Total Distortion (dB) 27 –45 –40 –30 +3 Input Level (dBm0) 20013A-011 Figure 4b. µ-law Total Distortion with Tone Input (Both Paths) SLAC Products 17 Discrimination against Out-of-Band Input Signals When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output caused by the out-of-band signal. These components are at least the specified dB level below the level of a signal at the same output originating from a 1014-Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are shown in Figure 5. Frequency of Out-of-Band Signal Amplitude of Out-of-Band Signal Level below A 16.6 Hz < f < 45 Hz –25 dBm0 < A ≤ 0 dBm0 18 dB 45 Hz < f < 65 Hz –25 dBm0 < A ≤ 0 dBm0 25 dB 65 Hz < f < 100 Hz –25 dBm0 < A ≤ 0 dBm0 10 dB 3400 Hz < f < 4600 Hz –25 dBm0 < A ≤ 0 dBm0 see Figure 5 4600 Hz < f < 100 kHz –25 dBm0 < A ≤ 0 dBm0 32 dB 0 QSLAC-NP Device Specification –10 –20 Level (dB) –28 dBm –30 –32 dB, –25 dBm0 < input < 0 dBm0 –40 –50 3.4 4.0 4.6 Frequency (kHz) Note: The attenuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula: π ( 4000 – f ) Attenuation (db) = 14 – 14 sin -------------------------1200 Figure 5. Discrimination against Out-of-Band Signals 18 Am79Q4457/5457 Data Sheet 20013A-012 Discrimination against 12 kHz and 16 kHz Metering Signals out-of-band signals at the analog output is less than the limits shown in the following table. If the QSLAC-NP device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of those tones may also appear at the I IN terminal. These out-of-band signals may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or 16 kHz tone, the frequency components below 4 kHz will be reduced from the input by at least 70 dB. The sum of the peak metering and signal currents must be within the analog input current range. Spurious Out-of-Band Signals at the Analog Output With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the digital input, the level of the spurious Frequency Level 4.6 kHz to 40 kHz –32 dBm0 40 kHz to 240 kHz –46 dBm0 240 kHz to 1 MHz –36 dBm0 With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital input, the level of the signals at the analog output are below the limits in Figure 6. The amplitude of the spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula: π ( f – 4000 ) A = – 14 – 14 sin ---------------------------- dBm0 1200 0 QSLAC-NP Device Specification –10 –20 Level (dBm0) –28 dB –30 –32 dB –40 –50 3.4 4.0 4.6 Frequency (kHz) 19256A-013 Figure 6. Spurious Out-of-Band Signals SLAC Products 19 SWITCHING CHARACTERISTICS over operating ranges (unless otherwise noted) Min and Max values are valid for all digital outputs with a 150 pF load. Control Interface No. Symbol Parameter Min Typ Max Units 1 tCCY Control Clock Period 244 ns 2 tCCH Control Clock High Pulse Width 97 ns 3 tCCL Control Clock Low Pulse Width 97 4 tCCR Rise Time of Clock 5 tCCF Fall Time of Clock 6 tICSS Chip Select Setup Time, Input Mode 70 0 ns 25 ns 25 ns t CCY –10 ns 7 tICSH Chip Select Hold Time, Input Mode 8 tICSL Chip Select Pulse Width, Input Mode t CCH –20 9 tICSO Chip Select Off Time, Input Mode 2 µs 10 tIDS Input Data Setup Time 30 ns 11 tIDH Input Data Hold Time 30 12 tOLH Output Latch Valid (Internal) 13 tOCSS Chip Select Setup Time, Output Mode 70 t CCY –10 ns 14 tOCSH Chip Select Hold Time, Output Mode 0 t CCH –20 ns 15 tOCSL Chip Select Pulse Width, Output Mode 16 tOCSO Chip Select Off Time, Output Mode 17 tODD Output Data Turn On Delay 18 tODH Output Data Hold Time 19 tODOF Output Data Turn Off Delay 20 tODC Output Data Valid 8t CCY ns ns ns 100 8t CCY ns ns µs 1 50 0 ns ns 0 50 ns 50 ns Max Units PCM Interface PCLK not to exceed 4.096 MHz. Pull-up resistor of 360 Ω is attached to TSCA. No. Symbol Parameter Min 21 tPCY PCM Clock Period (Note 1) 244 ns 22 tPCH PCM Clock High Pulse Width 97 ns 23 tPCL PCM Clock Low Pulse Width 97 24 tPCF Fall Time of Clock 25 tPCR Rise Time of Clock 26 tFSS FS Setup Time 27 tFSH FS Hold Time 50 28 tFSJ FS or PCLK Jitter Time –68 29 tTSD Delay to TSCA Valid (Short Frame Sync Mode) 30 tTSO Delay to TSCA Off (Note 2) 31 tDXD PCM Data Output Delay (Short Frame Sync Mode) 5 32 tDXH PCM Data Output Hold Time 33 tDXZ PCM Data Output Delay to High-Z (Note 3) 34 tDRS PCM Data Input Setup Time 25 35 tDRH PCM Data Input Hold Time 5 36 tTSD Delay to TSCA Valid (Long Frame Sync Mode) 5 40 ns 37 tDXD PCM Data Output Delay (Long Frame Sync Mode) 5 40 ns 55 Typ ns 25 ns 25 ns t PCY –50 ns ns +68 ns 5 80 ns 50 220 ns t PCL +70 70 ns 5 70 ns 50 220 ns t PCL +70 20 Am79Q4457/5457 Data Sheet ns ns Master Clock No. Symbol Parameter Min Max Units 38 AMCY Master Clock Accuracy +100 ppM 39 tMCR 40 tMCF Rise Time of Clock 15 ns Fall Time of Clock 15 ns 41 tMCH MCLK High Pulse Width 97 ns 42 tMCL MCLK Low Pulse Width 97 ns –100 Typ Notes: 1. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 4.096 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 256 kHz. 2. tTSO is defined as the time at which the output achieves the open circuit condition. 3. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DX pins of two QSLAC-NP devices are tied together and one QSLAC-NP device starts to transmit before the other has gone into a high-impedance state. SWITCHING WAVEFORMS Input and Output Waveforms for AC Tests 2.4 2.0 Test Points 0.8 0.45 2.0 0.8 19256A-015 Master Clock Timing 38 41 VIH VIL 42 40 39 SLAC Products 20031A-005 21 Control Interface (Input Mode) 1 2 5 VIH VIH CCLK VIL VIL 3 7 9 4 6 CSN 8 10 11 Data Valid Data Valid CI Data Valid 12 Latch Outputs (Internal) Data Valid Data Valid 20013A-017 Control Interface (Output Mode) VIH VIL CCLK 13 14 16 15 CSN 20 17 18 19 CO Three-State VOH VOL Data Valid Data Valid Data Valid Three-State 20013A-018 22 Am79Q4457/5457 Data Sheet PCM Highway Timing (Short Frame Sync Mode) Same point in previous frame Time Slot Zero Clock Slot Zero 28 21 25 24 VIH PCLK VIL 22 23 26 27 FSX/FSR 29 30 TSCA 31 33 VOH DXA 32 First Bit VOL 35 34 VIH DRA First Bit Second Bit VIL 20031A-006 SLAC Products 23 PCM Highway Timing (Long Frame Sync Mode) 21 28 25 PCLK 1 24 2 26 4 3 23 8 5 9 22 27 26 FSX/FSR 30 36 TSCA 37 DXA 33 32 37 First Bit 2 4 3 First Bit 2 3 8 5 8 35 34 DRA 5 4 20031A-007 OPERATING THE QSLAC-NP DEVICES The following describes the operation of the four independent channels of the QSLAC-NP device. The description is valid for Channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example, VOUT refers to either VOUT1, VOUT2, VOUT3, or VOUT4. Also, the additional features provided by the Am79Q4457 device (over the Am79Q5457 device) are described. Power-Up Sequence The signal pins have protection diodes to V CC and ground; consequently, if the signal leads are connected before VCC or ground, the transient signal current must be limited in order to prevent latch-up of the part. Following initial power application, it is necessary to place all channels in an inactive state. This ensures a hardware reset is initiated upon activation of any channel. For these reasons, the following power-up sequence is recommended: Following any subsequent occurrence of all channels inactivated, upon activation of any channel, a hardware reset will be initiated. Master Clock The master clock, MCLK, is used to derive internal clocks and timing signals. The master clock must be essentially jitter free and it must be an integer multiple of the frame sync frequency. The allowed frequencies for MCLK are 1.536 MHz, 1.544 MHz, 2.048 MHz, and 4.096 MHz. Internal circuitry determines the MCLK frequency based on the FSX inputs and adjusts the internal timing circuitry automatically. 1. VCC and ground 2. Signal connections 3. In the case of device Am79Q5457, take pins PDN1, PDN2, PDN3, and PDN4 to a logic high state, (device Am79Q4457 will default to all channels powered down). 24 Am79Q4457/5457 Data Sheet CONTROL OF THE Am79Q4457/5457 QSLAC-NP DEVICES Serial Control Register (Am79Q4457 Device Only) The QSLAC-NP device is controlled either directly via device pins (PDN and A/µ for the Am79Q5457 device) or through the serial control interface (Am79Q4457 device). The Am79Q4457 device provides an A-law/µ-law select pin in the same manner as the Am79Q5457 device. The Am79Q4457 QSLAC-NP device provides several additional features over the Am79Q5457 device. The Am79Q4457 device provides the ability to program three different gain levels on both the transmit and receive side of each channel. One of two balance impedances (connected externally) can be selected on a per-channel basis with the Am79Q4457 device. The individual channels of the Am79Q4457 device can be powered down. Control of the power-down function is through the per-channel serial control register. Parallel Control (Am79Q5457 Device) The Am79Q5457 QSLAC-NP device is controlled directly via device pins. There are two different control input pins on the Am79Q5457 device, an A-law/µ-law select (A/µ) pin and four power-down (PDN) pins, one per channel. Logic levels on these pins determine the operating state of the individual channels, active (powerup) or idle (power-down), and A-law or µ-law operation. Each channel of the QSLAC-NP device can operate in either the Powered-Up (Active) or Powered-Down (Standby) mode. In the Active mode, individual channels of the QSLAC™ device are able to transmit and receive PCM and analog information. The Active mode is required when a telephone call is in progress. The Standby mode requires the least amount of power per channel and should be used whenever the line circuit is on hook and a telephone call is not in progress. Power Down Input (PDN n): 0 — Powers the channel up 1 — Powers the channel down A-Law/µ-Law Select Input (A/µ): 0 — Selects µ-law operation Each channel of the Am79Q4457 QSLAC-NP device contains a serial shift register and latch in order to easily control the additional functionality of the device. The registers are connected as shown in Figure 7. The channel control registers are enabled for reading or writing by their corresponding Chip Select (CSn) signal. Data on the Control Input (CI) is shifted into the enabled register by the Control Clock (CCLK). Each channel register contains a Balance Network Select (BNS1) bit, two Receive Gain Select (RGS1/2) bits, two Transmit Gain Select (TGS1/2) bits and a Power-Down (PDN) bit. As indicated in Figure 7, the PDN bit is the most significant bit in the register and is shifted in first. The balance network select bit is the least significant bit and is shifted in last. The Balance Network is selected with the BNS1 bit, where: 1 — Selects A-law operation 0 —Selects the balance network connected to I1IN of the channel. 1 —Selects the balance network connected to I2IN of the channel. Transmit and Receive gains are selected according to the TGS1/2 and RGS1/2 bits as shown in the gain select tables, Table 2 and Table 3. The register layout for each channel is as follows: PDN RSVD RSVD TGS2 RGS2 TGS1 RGS1 BNS1 Note: PDN is loaded first. SLAC Products 25 CI CO CS1 CCLK CO CS1 CCLK Shift Register and Latch Channel 1 Qh Qg PDN1 RSVD Qf RSVD CO CS2 CCLK CS2 Qh PDN2 Qg RSVD Qh PDN3 Qf PDN4 Qc Qb Qf RSVD RSVD Qe Qd CI Qc Qb Qf Qd TGS23 RGS23 RSVD RSVD Qe Qa RGS22 TGS12 RGS12 BNS12 CI Qc Qb Qd TGS24 RGS24 Qa TGS13 RGS13 BNS13 Shift Register and Latch Channel 4 Qg Qa RGS21 TGS11 RGS11 BNS11 Shift Register and Latch Channel 3 Qg Qh Am79Q4457 Qe RSVD TGS22 CO CS4 CCLK CS4 TGS21 Qd Shift Register and Latch Channel 2 CO CS3 CCLK CS3 Qe CI CI Qc Qb Qa TGS14 RGS14 BNS14 20031A–008 Figure 7. Am79Q4457 QSLAC-NP Device Serial Control Interface I1IN *I2IN BNS1 Decimator ADC LPF & HPF Compressor PCM Interface DXA TGS1* TGS2* REF Select IREF1 *IREF2 *IREF3 A/µ VREF1 *VREF2 *VREF3 REF Select VOUT DAC RGS1* RGS2* Interpolator LPF Expander PCM Interface DRA 20031A-009 *Am79Q4457 device only Figure 8. QSLAC-NP Device Block Diagram 26 Am79Q4457/5457 Data Sheet Power Down (PDNn): Receive Signal Processing 0 — Powers the channel up Digital data received from the PCM highway is expanded from A-law or µ-law, filtered, converted to analog, and passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. 1 — Powers the channel down Reset State All four channel control registers are reset by the application of power. This resets the QSLAC-NP device to the following state: TGS, RGS, BNS = 0 and PDN = 1 for all four channels. The Low-Pass Filter band limits the signal. The interpolator increases the sampling rate prior to D/A conversion. Signal Processing Receive PCM Interface Overview of Digital Filters The receive PCM interface receives 1 byte (8 bits) every 125 µs from the PCM highway. The data is received under control of the receive logic and synchronized by the receive frame synchronization signal (FSR N). The receive frame sync (FSXN) pulse identifies the receive time slot of the PCM frame for Channel N. The QSLAC-NP devices (Am79Q4457/5457) are compatible with both a long- and a short-frame synchroniz a t i o n s i g n a l . S e e t h e P C M i n t e r fa c e t i m in g specifications (20 to 24) for more details. The receive PCM data is expanded by the A-law/µ-law expansion logic, and passed on to the signal processor. Several elements in the signal processing section of the Am79Q4457 device provide user options. These options allow the user to optimize the performance of the QSLAC-NP device for the application. Figure 8 shows the QSLAC-NP device signal processing section and indicates the user-programmable blocks, the reference current selector, the reference voltage selector, the balance network selector, and the A-law/µ-law selector. The High-Pass Filter (HPF) and the LowPass Filter (LPF) sections of the signal processor are implemented in the digital domain. The advantages of digital filters are high reliability, no drift with time or temperature, unit-to-unit repeatability, and superior transmission performance. Transmit Signal Processing In the transmit path, the analog input signal (IIN) is A/D converted, filtered, compressed, and made available to the PCM highway in A-law or µ-law form. The signal processor contains an ALU, RAM, ROM, and control logic to implement the filter sections. The decimator reduces the high input sampling rate to 16 kHz for input to the Low-Pass and High-Pass Filters. The High-Pass Filter rejects low frequencies such as 50 Hz or 60 Hz and the Low-Pass Filter limits the voice band to 3400 Hz. Transmit PCM Interface The transmit PCM interface receives 1 byte (8 bits) every 125 µs from the A-law/µ-law compressor. The data is transmitted onto the PCM highway under control of the transmit logic, synchronized by the Transmit Frame Synchronization signal (FSXN). The frame synchronization signal (FSX N) identifies the transmit time slot of the PCM frame for Channel N. The QSLAC-NP devices (Am79Q4457/5457) are compatible with both a long- and a short-frame synchronization signal. See the PCM interface timing specifications (20 to 24) for more details. While the PCM data is output on the DXA port, the TSCA buffer control signal is Low. Speech Coding The A/D and D/A conversions follow either the A-law or the µ-law standard as defined in ITU-T Recommendation G.711. A-law or µ-law operation is programmed using the A-law/µ-law program (A/µ) pin. Alternate bit inversion is performed as part of the A-law coding. Short-Frame Sync Mode If each of the transmit (FSXN) frame sync pulses overlap either one or two negative-going transitions of PCLK, the part operates in what is called Short-Frame Sync mode. In this mode, the part operates like a DSLAC, ASLAC, or QSLAC device programmed for time slot 0, clock slot 0, and XE=1. If a frame sync overlaps two transitions, the first of these transitions defines the beginning of the time slot. The first positive PCLK transition after the beginning of a transmit time slot enables the DXA output with the sign bit as the first output. It also drives the TSCA output Low. The succeeding seven positive clock transitions shift out the remainder of the data, and the eighth negative transition tri-states DXA and turns off TSCA. During the latter part of each output period, the transmit data is held by a weak driver in order to minimize bus contention if one time slot starts before the preceding one ends. The first negative PCLK transition after the beginning of a receive time slot latches in the first data bit (sign bit) from the DRA input. The succeeding seven negative clock transitions shift in the remainder of the data. SLAC Products 27 Long-Frame Sync Mode If each of the transmit (FSXN) frame sync pulses overlap three or more negative-going transitions of PCLK, the part operates in what is called Long-Frame Sync mode. The time slot begins at the first point where both frame sync and PCLK are High. The beginning of a transmit time slot enables the DXA output with the sign bit as the first output. It also drives the TSCA output Low. The succeeding seven positive clock transitions shift out the remainder of the data. The eighth negative transition of PCLK or the end of FSX, whichever comes later, tri-states DXA and turns off TSCA. If FSX extends beyond the eighth PCLK edge, the eighth bit is held at DXA. During the latter part of each output period, the transmit data is held by a weak driver in order to minimize bus contention if one time slot starts before the preceding one ends. The first negative PCLK transition after the beginning of a receive time slot latches in the first data bit (sign bit) from the DRA input. The succeeding seven negative clock transitions shift in the remainder of the data. APPLICATIONS The QSLAC-NP device family consists of two devices, the Am79Q5457 device and the Am79Q4457 device. The Am79Q5457 device is a four-channel Codec/Filter device with eight frame synchronization inputs, two per channel. Both the Am79Q4457 and Am79Q5457 devices are A-law or µ-law c om patible. The Am79Q4457 device provides all the functions of the Am79Q5457 device and the additional functions of selecting transmit and receive gain levels and balance networks on a per-channel basis. If the application requires a fixed transmit and receive gain level and one balance network, the Am79Q5457 device is ideal. If the application requires more than one gain setting or balance network, the Am79Q4457 device is ideal. If full programmability of gain, frequency response, balance impedance, input impedance, and time slot assignment are required, then the Am79Q02/021/031 Quad SLAC (QSLAC) device is ideal. The QSLAC-NP device performs the Codec/Filter function for four telephone lines. It interfaces to the telephone lines through four Legerity SLIC devices as shown in Figure 10 and Figure 11. The QSLAC-NP device may require an external buffer to drive transformer SLICs. Connection to a PCM back plane is implemented by means of a simple buffer IC. See Figure 10 and Figure 11. Several QSLAC-NP devices can be tied together in one bus interfacing the back plane through a single buffer. An intelligent bus interface chip is not required because each QSLAC-NP device provides its own buffer control (TSCA). 28 SETTING GAIN LEVELS Gain Settings for the Am79Q4457 Device The possible transmit and receive gain levels are set once for the four channels via three reference currents and three reference voltages (see Figure 9a). The three IREF outputs are biased at the internal reference voltage so that a resistor placed from the output to ground sets up a reference current in the device. These reference currents are buffered and provided as inputs to the 3-to-1 analog multiplexers, one per channel. One of three reference currents can be selected for use by the transmit A/D converter. Each reference current set up by the user corresponds to one transmit gain setting. The transmit gain is a function of the input resistor RTX and the reference resistor R REF as shown in Figure 9a and Table 2. In much the same way, three reference voltages are set up, one internally and two externally, as shown in Figure 9a. These voltages are internally buffered and provided to the 3-to-1 analog multiplexers, one per channel. One of three reference voltages can be selected and provided to the receive D/A converter for use in decoding the data. Each reference voltage level corresponds to a receive gain setting. The receive gain is a function of the internally generated reference voltage V REF1 and the scaled version V REF2 or V REF3, as shown in Figure 9a and Table 3. One of two balance networks per channel is selected via the serial control register. As shown in Figure 9a, this is achieved by providing two inputs to the transmit A/D converter and using a 2-to-1 analog multiplexer to select the desired input. Table 2. Transmit Gain Select (Am79Q4457 Device Only) Transmit Gain Select 1 (TGS1) and Transmit Gain Select 2 (TGS2) TGS2 TGS1 A-to-D Gain 0 0 3•R REF1Gt = Gt1 = --------------------------Rb TX 0 1 3 • (R +R ) REF2A REF2B Gt = Gt2 = ------------------------------------------------------------------Rb TX 1 0 3 • ( R REF3A + R REF3B ) Gt = Gt3 = -------------------------------------------------------------------Rb TX 1 1 Do Not Use See Figure 9. “b” represents the value of BNS1. Am79Q4457/5457 Data Sheet Gain Settings for the Am79Q5457 Device Table 3. Receive Gain Select (Am79Q4457 Device Only) The transmit and receive gains for each of the four channels are set for the Am79Q5457 device similarly to those of the Am79Q4457 device. The Am79Q5457 device has only one IREF output and one VREF input as shown in Figure 9b, and only one gain setting is available. The transmit gain is a function of the reference current set up by the R REF1 resistor and by the R TX1 input resistor, and is set by the following equation: Receive Gain Select 1 (RGS1) and Receive Gain Select 2 (RGS2) RGS2 RGS1 0 0 D-to-A Voltage Reference Gr = Gr1 = 1 0 1 1.4 • R REF2A Gr = Gr2 = -----------------------------------------R REF2A + R REF2B 1 0 1.4 • R REF3A Gr = Gr3 = -----------------------------------------R REF3A + R REF3B 1 1 Do Not Use 3 • R REF1 Gt = ---------------------R1 TX1 The receive gain Gr through the QSLAC-NP device is equal to 1 and is not adjustable. However, this gain typically is set by choice of component values in the SLIC portion of the circuit. Note: 0.4 ≤ Gr ≤ 1 Am79Q4457JC to SLIC VTX R1TX1 C1TX1 R2TX1 l1IN1 A/D 1 2 3 4 IREF l2IN1 C2TX1 BNS1 I1 IO 3 to 1 Multiplexer I2 I3 TGS1 TGS2 IREF1 VREF to IREF IREF2 IREF3 Bal Net 1 * to SLIC RSN Bal Net 2 Bal Net 1 VREF1 * Bal Net 2 V1 3 to 1 Multiplexer Vo CRX1 VOUT1 D/A 1 RREF1 IREF2 RREF2A RREF2B IREF3 RREF3A RREF3B VREF1 CFIL VREF2 V2 VREF3 V3 RGS1 RGS2 VREF RRX1 IREF1 2 3 4 20031A–010 *Optional Bal Net Connection Figure 9a. Am79Q4457JC Device (Channel 1 Shown) SLAC Products 29 Am79Q5457 to SLIC VTX R1TX1 C1TX1 A/D 1 I1 IN1 2 3 4 IREF VREF to IREF * Bal Net to SLIC RSN Bal Net VREF1 RREF1 CFIL VREF RRX1 CRX1 VOUT1 D/A *Optional Bal Net Connection Figure 9b. Am79Q5457 Device (Channel 1 Shown) 30 IREF1 Am79Q4457/5457 Data Sheet 20031A–012 R1TX1 C1TX1 VTX I1IN1 C2TX1 RREF1 IREF1 I2IN1 R2TX1 SLIC1 ZT1 Bal Net 1 Bal Net 2 Bal Net 1 * Bal Net 2 * IREF2 RRX1 VOUT1 RSN VREF1 A/µ I2IN2 ZT2 * Bal Net 1 Bal Net 2 Bal Net 1 * M B A PCLK C1TX3 I1IN3 Bal Net 2 Bal Net 1 * Bal Net 2 K P FSRn L A FSXn I2IN3 Bal Net 1 C C C2TX3 ZT3 P DRA CRX2 SLIC3 VCCD TSCA VOUT2 R2TX3 VCCD DXA RSN VTX CFIL RPULL Bal Net 2 RRX2 R1TX3 RREF3B VREF3 I1IN2 C2TX2 R2TX2 RREF3A VREF2 C1TX2 VTX SLIC2 RREF2B IREF3 Am79Q4457JC QSLAC-NP C RX1 R1TX2 RREF2A N E * MCLK RRX3 CCLK VOUT3 RSN CI C RX3 R1TX4 C2TX4 R2TX4 SLIC4 ZT4 Bal Net 1 O CO C1TX4 VTX C Bal Net 2 Bal Net 1 * Bal Net 2 * I1IN4 CS1 I2IN4 CS2 CS3 N T R O L CS4 RRX4 RSN VOUT4 To SLICs Analog GND Analog VCC CRX4 AGND VCCA 13 kΩ ≤ R REF1 ≤ 26 kΩ 13 kΩ ≤ R REF2A + RREF2B ≤ 26 kΩ 13 kΩ ≤ R REF3A + RREF3B ≤ 26 kΩ RPULL = 360 Ω ± 5% R1TX1, R1TX2, R1TX3, R1TX4 - See Transmit Gain Select 1, Table 2 R2TX1, R2TX2, R2TX3, R2TX4 - See Transmit Gain Select 2, Table 2 ZT1–4 = SLIC Programming Impedance - See SLIC Data Sheet DGND VCCD Digital Digital GND VCC To other QSLAC-NP Devices 20031A–011 RRX1, RRX2, R RX3, RRX4 - See SLIC Data Sheet CFIL = 0.1 µF ± 20%, X7R C1TX1, C1TX2, C1TX3, C1TX4 = 0.1 µF ± 20%, X7R, typ. C2TX1, C2TX2, C2TX3, C2TX4 = 0.1 µF ± 20%, X7R, typ. CRX1, CRX2, C RX3, CRX4 = 0.1 µF ± 20%, X7R, typ. *Optional Balance Network connection. Figure 10. Am79Q4457JC Device SLAC Products 31 R1TX1 C1TX1 I1IN1 VTX RREF1 IREF1 * SLIC1 Bal Net ZT1 Bal Net VOUT1 RSN R RX1 R1TX2 Am79Q5457 QSLAC-NP VREF1 CFIL C RX1 C1TX2 VTX VCCD I1IN2 A/µ VCCD * SLIC2 Bal Net ZT2 RPULL Bal Net P DXA C M TSCA VOUT2 RSN RRX2 R1TX3 B DRA CRX2 PCLK C1TX3 VTX Bal Net ZT3 P L A FSXn N E MCLK Bal Net CCLK VOUT3 RSN RRX3 K FSRn I1IN3 * SLIC3 A C C RX3 C O R1TX4 C1TX4 N VTX PDN1 I1IN4 PDN2 PDN3 * SLIC4 Bal Net ZT4 To SLICs CRX4 AGND VCCA DGND VCCD Digital Digital GND VCC 13 kΩ ≤ R REF1 ≤ 26 kΩ RPULL = 360 Ω ± 5% R1TX1, R1TX2, R1TX3, R1TX4 - See Transmit Gain Select 1, Table 2 RRX1, RRX2, RRX3, RRX4 - See SLIC Data Sheet ZT1–4 = SLIC Programming Impedance - See SLIC Data Sheet To other QSLAC-NP Devices 20031A–011 CFIL = 0.1 µF ± 20%, X7R, typ. C1TX1, C1TX2, C1TX3, C1TX4 = 0.1 µF ± 20%, X7R, typ. CRX1, CRX2, C RX3, CRX4 = 0.1 µF ± 20%, X7R, typ. *Optional Balance Network connection. Figure 11. Am79Q5457JC Device 32 L VOUT4 RRX4 Analog GND Analog VCC O PDN4 Bal Net RSN T R Am79Q4457/5457 Data Sheet Calculation of Balance Network Th e balan ce fu nctio n is implemen ted with the QSLAC-NP device by connecting an external balance network (ZBAL) between the VOUT and IIN terminals. Assuming the uncancelled receive path signal, which appears in the SLIC’s transmit path, is out of phase with the originating receive path (the QSLAC-NP device’s VOUT) signal, this external network will provide a path for the needed cancellation. The IIN terminal is a current summing node and is a virtual ac ground, simplifying the implementation of this balance function. In many cases, this balance network can be a single resistor, and in other cases, depending on the balance impedance and the transfer characteristics of the SLIC, it may be necessary to add a capacitor. Complete definition of the balance network is dependent on the SLIC and the balance impedance and, as such, cannot be completely defined within this document. However, a general method of calculation can be described as follows: Figure 12 shows a simplified equivalent circuit of a SLIC, along with the balance impedance and interconnecting networks to the QSLAC device. A SLIC circuit can be represented by four gain parameters (G-parameters), where each of these blocks represents a complex transfer function: G24 is the gain from the tip/ring two-wire port toward the four-wire port; G42 is the unterminated gain from the four-wire port toward the two- wire port; ZSL is the two-wire SLIC impedance; and G44 is the gain that appears from the four-wire input toward the four-wire output with the two-wire por t shorted. Considering only the SLIC, plus the externally connected balance impedance, ZTERM, any signal that is presented to the SLIC’s four-wire input will have a representation at the V TX four-wire output defined by the SLIC’s G-parameters and the ZBAL termination. G44L (G44 loaded) can then be defined as the four-wire to four-wire gain through the SLIC when loaded by Z TERM. The RTX resistor establishes the transmit path gain by translating the SLIC’s VTX output voltage so that it appears as a current into the QSLAC-NP device’s IIN current input and, as such, provides the scaling necessary to define the transmit gain. If the G44L gain is then known, the balance network can be calculated as follows: R TX 1 Z BAL = ------------G44L G44L is a complex value, which implies that ZBAL must also be complex. However, in many cases, satisfactory balance over the voice band can be achieved by using only one resistor. This configuration assumes that R TX • C TX and R RX • C RX have time constants greater than 10 ms. If that is not true, the balance network should be moved to the QSLAC-NP device side of the coupling capacitors and should also have a capacitor placed in series with the network. QSLAC-NP device SLIC VTX ε G24 CTX RTX IIN Optional ZBAL Placement ZBAL G44 RRX * TIP/RING ZSL VOUT G42 CRX ZTERM Note: *G-parameter model includes the R RX resistor inside SLIC. Figure 12. Balance Network SLAC Products 33 CONSIDERATIONS FOR CONNECTION TO SLICS There are several factors to consider with the connection method used between the QSLAC-NP device and the SLIC. The RTX resistor controls the transmit path gain by establishing the current into the QSLAC-NP device’s IIN pin. The RRX resistor controls the receive path gain in conjunction with the other SLIC circuit elements, by establishing the current into the SLIC’s RSN pin. The balance network provides a path for passing a representative portion of the receive path signal back into the transmit path for setting the transhybrid balance. Additionally, the capacitors used to provide DC isolation between the SLIC and the QSLAC device also have an effect on system performance. Figure 13 shows the connection scheme as described earlier in this document. An alternative connection scheme is shown in Figure 14. The only difference in these connection methods is the placement of the balance network, but in each case, there are specific factors to be considered. Effects of CRX and CTX Capacitors While the purpose of the CRX and CTX capacitors is to provide DC isolation, they have a finite impedance that is a function of frequency. Nominal values of the RRX and RTX resistors typically are large compared to the capacitors’ impedances at most voice band frequencies; but at lower frequencies, the capacitor impedances may have an effect. For example, a 0.1 uF capacitor at 1000 Hz has an impedance of 1592 Ω, but at 300 Hz, that impedance increases to 5305 Ω. While this is still a small change compared to the resistor values, it is not this change alone that may need to be considered. For example, in Figure 14, the I IN input pin of the QSLAC-NP device has two sources feeding it: One is the ZBAL balance network, and the other is the series path of RTX and CTX that are fed from the SLIC’s VTX output. The IIN pin is a virtual ground, so currents from the two source paths do not effect one another. However, in Figure 13, the ZBAL network is connected between the C TX and R TX components. So long as the capacitor’s impedance is low, it has little effect on signals from either ZBAL or from RTX, and both of those signal’s currents continue to flow into the IIN virtual ground. As the capacitor’s impedance begins to become significant with lower frequencies, a portion of the transmit path current from RTX will begin to flow into ZBAL toward the low impedance output of the QSLAC-NP device’s VOUT pin. The net effect is a low frequency attenuation to the transmit path signal. A similar situation also exists in the receive path. 34 Placement of the Balance Network The only difference in the two circuit connection methods shown in Figure 13 and Figure 14 is the placement of the ZBAL network. Both methods have benefits and both have different issues to consider for the overall design performance. Depending on the SLIC and the termination impedance for which balance is specified, the circuit of Figure 13 may reduce the complexity needed of the ZBAL network so that only a single resistor is required. This would be especially true of short loop applications where the actual termination in service is a relatively constant resistance. Since in this configuration the CTX and C RX capacitors are both external to the echo loop being canceled by ZBAL, the frequency dependent echo responses due to their effects need not be considered. In Figure 14, however, the capacitors are in series with the receive and transmit paths. Since the resistor values are unequal, the frequency rolloff characteristics will likely be unequal without corresponding changes of the C RX and CTX values. This frequency dependent characteristic now implies that the ZBAL network also contains the necessary complex components to maintain proper phase response. SLIC Connection Consideration Summary Two different interconnection schemes are described in Figure 13 and Figure 14. The configuration shown in Figure 13 may simplify the ZBAL network, or possibly even remove the need for it to contain capacitive elements, provided that the balance termination impedance and SLIC characteristics are compatible. It may be necessary in this configuration to use larger C RX or CTX capacitor values if frequency response at very low frequencies becomes a concern. The configuration shown in Figure 14 may allow smaller transmit and receive path coupling capacitors, but may require a slightly more complex ZBAL network. Variations of the configurations from either of these figures are also possible. In any case, the designer must consider all of the effects of SLIC characteristics, balance termination impedance values, coupling capacitor values, and balance network values. Am79Q4457/5457 Data Sheet SLIC QSLAC-NP device RTX VTX CTX IIN ZBAL ZT RSN VOUT RRX CRX Figure 13. Balance Network Connection SLIC QSLAC-NP device RTX VTX CTX IIN ZBAL ZT RSN VOUT RRX CRX Figure 14. Alternate Balance Network Connection SLAC Products 35 PHYSICAL DIMENSIONS PL032 Dwg rev AH; 10/99 36 Am79Q4457/5457 Data Sheet PL044 Dwg rev. AN; 8/99 SLAC Products 37 PQT044 Dwg rev AS; 08/99 38 Am79Q4457/5457 Data Sheet REVISION SUMMARY Revision B to Revision C • The physical dimensions (PL032, PL044 and PQT044) were added to the Physical Dimension section. • Updated the Pin Description table to correct inconsistencies. Revision C to Revision D • All the physical dimensions were updated. SLAC Products 39 Notes: www.legerity.com Notes: www.legerity.com Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers’ products. By combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide field applications support, Legerity ensures its customers enjoy a smoother design experience. It is this commitment to our customers that places Legerity in a class by itself. The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity’s Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. 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