Preliminary Information Integrated Circuit Systems, Inc. M1010-01 VCSO BASED CLOCK JITTER ATTENUATOR GENERAL DESCRIPTION PIN ASSIGNMENT (9 x 9 mm SMT) 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC The M1010-01 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for OC-12 and OC-48 optical network systems supporting 622 2,488 MHz rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M1010-01 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. FIN_SEL0 SEL0 SEL1 SEL2 NC VCC DNC DNC DNC VCC NC nFOUT FOUT GND NC NC VCC GND 18 17 16 15 14 13 12 11 10 M1010 (Top View) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 1 2 3 4 5 6 7 8 9 28 29 30 31 32 33 34 35 36 FEATURES ◆ Ideal for OC-12/48 data clock Figure 1: Pin Assignment ◆ Integrated SAW delay line Example I/O Clock Frequency Combinations Using M1010-01-155.5200 ◆ Output frequencies from 150 to 175 MHz (Specify VCSO output frequency at time of order) Input Reference Clock (MHz) Frequency Input (Mfin) Ratio ◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz) ◆ LVPECL clock output 8 2 1 ◆ Pin-selectable feedback and reference divider ratios, no programming required ◆ Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance 19.44 77.76 155.52 Output Clock MHz 155.52 Table 1: Example I/O Clock Frequency Combinations ◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package SIMPLIFIED BLOCK DIAGRAM Loop Filter M1010 DIF_REF0 0 nDIF_REF0 R Div DIF_REF1 nDIF_REF1 M Div REF_SEL SEL2:0 FIN_SEL1:0 VCSO 1 3 Mfin Div FOUT Divider LUT 2 nFOUT Mfin Divider LUT Figure 2: Simplified Block Diagram M1010-01 Datasheet Rev 0.4 Revised 29Sep2003 M1010-01 VCSO Based Clock Jitter Attenuator Integrated Circuit Systems, Inc. ● Communications Modules ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information DETAILED BLOCK DIAGRAM RLOOP CLOOP RPOST External Loop Filter Components CPOST CPOST RPOST RLOOP CLOOP M1010 OP_IN MUX DIF_REF0 nDIF_REF0 0 DIF_REF1 nDIF_REF1 1 Phase Detector nOP_IN OP_OUT nOP_OUT RIN Phase Locked Loop (PLL) R Div RIN nVC Loop Filter Amplifier VC SAW Delay Line Phase Shifter VCSO M Div REF_SEL SEL2:0 FIN_SEL1:0 3 Mfin Divider Divider LUT FOUT nFOUT Mfin Divider LUT 2 Figure 3: Detailed Block Diagram PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC 11, 18, 19, 33 VCC 12, 13, 17, 25, 32 15 16 NC FOUT nFOUT 20 nDIF_REF1 21 DIF_REF1 22 REF_SEL 23 nDIF_REF0 24 DIF_REF0 27 28 FIN_SEL1 FIN_SEL0 29 30 31 34, 35, 36 SEL0 SEL1 SEL2 DNC I/O Configuration Description Ground Power supply ground connections. Input External loop filter connections. See Figure 4, External Loop Filter, on pg. 4. Output Input Power Power supply connection, connect to +3.3V. No internal connection. Output No internal terminator Clock output pairs. Differential LVPECL. Internal pull-UP resistor1 Input 1 Internal pull-down resistor Internal pull-down resistor1 Input Internal pull-UP resistor1 Input 1 Internal pull-down resistor Reference clock input pair. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair. Differential LVPECL or LVDS. Input Input clock frequency selection. LVCMOS/LVTTL. Internal pull-down resistor1 See Table 3, Mfin (Frequency Input) Divider Look-Up Table (LUT) on pg. 3. Input Internal pull-UP resistor1 M and R divider value selection. LVCMOS/ LVTTL. See Table 4, SEL2:0 Look-up Table (LUT) on pg. 3. Do Not Connect. Table 2: Pin Descriptions Note 1: For typical values of internal pull-down and pull-up resistors, see “Inputs with Pull-down” and “Inputs with Pull-up” in Table 8, DC Characteristics, on pg. 6. M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 2 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information PLL DIVIDER LOOK-UP TABLES SEL2:0 Look-up Table (LUT) Mfin (Frequency Input) Divider Look-Up Table (LUT) The SEL2:0 pins select the feedback and reference divider values M and R to enable adjustment of loop bandwidth and jitter tolerance. The FIN_SEL1:0 pins select the feedback divider value (“Mfin”). FIN_SEL1:0 0 0 1 1 0 1 0 1 Mfin Value 8 2 1 x SEL2:0 M1010-01-155.5200 0 0 0 0 Sample Ref. Freq. (MHz) 1 19.44 77.76 155.52 Test mode. Do not use. Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT) Note 1: Example with M1010-01-155.5200. 0 0 1 1 0 1 0 1 M R 236 79 14 239 Description 236 79 14 239 Various divider values to adjust bandwidth 1 and jitter tolerance 1 0 0 1 1 0 1 2 2 1 1 0 4 4 1 1 1 8 8 Table 4: SEL2:0 Look-up Table (LUT) FUNCTIONAL DESCRIPTION The M1010-01 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). A configurable frequency divider (labeled “Mfin Divider”) provides the division options to accomodate various reference clock frequencies. In addition, configurable feedback and reference dividers (the “M Divider” and “R Divider”) provide divider value options to enable adjustment of loop bandwidth and jitter tolerance. For example, the M1010-01-155.5200 (see “Ordering Information” on pg. 8) has a 155.52MHz VCSO The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output’s frequency and phase to those of the input reference clock. Due to the narrow tuning range of the VCSO (+200ppm), appropriate selection of all of the following are required for the PLL be able to lock: VCSO center frequency, input frequency, and divider selections. Relationship Among Frequencies and Dividers The VCSO center frequency must be specified at time of order. The relationship between the VCSO (Fvcso) frequency, the Mfin divider, the M divider, the R divider, and the input reference frequency (Fin) is: M frequency: The Mfin feedback divider allows an input frequency to be the VCSO output frequency divided by 1, 2, or 8. Therefore, for the base input frequency of 155.52MHz, the actual input reference clock frequencies can be: 155.52, 77.76, and 19.44MHz. (See Table 3 on pg. 3.) The PLL Fvcso = Fin × Mfin × ---R Clock Output The M1010-01 provides one differential LVPECL output pair FOUT. PECL and LVDS product options are available; consult factory. The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The “Mfin Divider” and “M Divider” divide the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the “R Divider”. The result is fed into the other input of the phase detector. M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 3 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information External Loop Filter To provide stable PLL operation, the M1010-01 requires the use of an external loop filter. This is implemented by connecting passive external components to the device as shown in Figure 4 below. The M1010-01 utilizes a differential analog signal path to minimize noise coupling from the system. Because of this, the loop filter implementation requires two identical complementary RC filters as shown here. RLOOP CLOOP CPOST OP_IN nOP_IN 4 RPOST CLOOP OP_OUT 9 nOP_OUT 8 nVC 5 The various SEL1:0 settings can be used to actively change PLL loop bandwidth in a given application. See “SEL2:0 Look-up Table (LUT)” on pg. 3. See Table 5, Example Loop Filter Component Values for M1010-01-155.5200, on pg. 4. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. RPOST CPOST RLOOP PLL bandwidth is affected by the “M” value and the “Mfin” value, as well as the VCSO frequency. VC 6 7 Figure 4: External Loop Filter Example Loop Filter Component Values for M1010-01-155.52001 VCSO Parameters: KVCO = 200kHz/V, RIN = 2050kΩ, VCSO Bandwidth = 700kHz. Device Configuration FRef FVCSO Mfin 19.44 155.52 8 (MHz) 77.76 155.52 (MHz) 155.52 155.52 2 1 Example External Loop Filter Component Value M, R R loop Value2 C loop R post C post Nominal Performance Using These Values PLL Loop Damping Passband Peak Bandwidth Factor Amplitude @ Center (dB) Freq. 6.5 0.05 10Hz 270Hz 1 118.0kΩ 1.0µF 100kΩ 1000pF 2 118.0kΩ 22.0µF 200kΩ 1000pF 134Hz 6.8 0.04 4Hz 1 59.0kΩ 1.0µF 100kΩ 1000pF 610Hz 6.5 0.05 20Hz 2 59.0kΩ 2.2µF 100kΩ 1000pF 267Hz 6.8 0.04 10Hz 8 118.0kΩ 2.2µF 200kΩ 1000pF 134Hz 6.8 0.04 10Hz 1 40.2kΩ 1.0µF 40.2kΩ 1000pF 740Hz 6.3 0.05 20Hz 4 59.0kΩ 1.0µF 100kΩ 1000pF 267Hz 6.8 0.04 10Hz 76.8kΩ 2.0µF 180Hz 6.3 0.05 8Hz 8 200kΩ 1000pF Table 5: Example Loop Filter Component Values for M1010-01-155.5200 Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. Note 2: For loop timing applications, the recommended value for the product of “Mfin” x “M” is 8 or higher. M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 4 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Rating Unit VI Inputs -0.5 to VCC +0.5 V VO Outputs -0.5 to VCC +0.5 V VCC Power Supply Voltage 4.6 V TS Storage Temperature -45 to +100 oC Table 6: Absolute Maximum Ratings Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. RECOMMENDED CONDITIONS OF OPERATION Symbol Parameter VCC Positive Supply Voltage TA Ambient Operating Temperature Commercial Industrial Min Typ Max Unit 3.135 3.3 3.465 V 0 -40 oC +70 +85 oC Table 7: Recommended Conditions of Operation M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 5 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information ELECTRICAL SPECIFICATIONS DC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter Power Supply VCC Differential Inputs Positive Supply Voltage ICC Power Supply Current IIH Input High Current Min Typ Max Unit Conditions 3.135 3.3 3.465 V DIF_REF0, DIF_REF1 150 µA 5 µA nDIF_REF0, nDIF_REF1 IIL Input Low Current -5 µA nDIF_REF0, nDIF_REF1 -150 µA DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 0.15 DIF_REF0, DIF_REF1 VP-P Peak to Peak Input VCMR Common Mode Input LVCMOS / LVTTL Inputs VIH Input High Voltage VIL Input Low Voltage CIN Input Capacitance Inputs with Pull-down IIH Input High Current IIL Input Low Current -0.3 All Inputs except nDIF_REF1:0, SEL2:0 Input High Current IIL Input Low Current Rpullup Internal Pull-up Resistor All Inputs CIN Input Capacitance Differential Outputs VOH Output High Voltage VOL VP-P 0.8 V 4 pF 150 µA µA -5 µA 5 µA -150 All Inputs Peak to Peak Output Voltage Vcc - 1.4 Vcc - 1.0 V Vcc - 2.0 Vcc - 1.7 V 0.4 0.85 6 of 8 ● Communications Modules V Table 8: DC Characteristics Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time on pg. 7. M1010-01 Datasheet Rev 0.4 pF 4 1 VCC = 3.456V VIN = 0 V kΩ 51 FOUT, nFOUT VCC = VIN = 3.456V kΩ 51 nDIF_REF1, nDIF_REF0, SEL2, SEL1, SEL0 Output Low Voltage Integrated Circuit Systems, Inc. V Vcc + 0.3 V 2 REF_SEL, FIN_SEL1, FIN_SEL0, SEL2, SEL1, SEL0 IIH V Vcc - 0.5 Rpulldown Internal Pull-down Resistor Inputs with Pull-up mA 162 Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M1010-01 Integrated Circuit Systems, Inc. VCSO BASED CLOCK JITTER ATTENUATOR Preliminary Information ELECTRICAL SPECIFICATIONS (CONTINUED) AC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter FIN PLL Loop Constants 1 Min Input Frequency Typ 18.75 DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 Max Unit Conditions 175 MHz MHz MHz 50 FOUT Output Frequency APR VCSO Pull-Range KVCO VCO Gain 200 ppm ppm kHz/V RIN Internal Loop Resistor 2050 kΩ 700 kHz -72 -94 -123 FOUT, nFOUT 150 175 ±120 ±50 Commercial Industrial BWVCSO VCSO Bandwidth Φn Phase Noise and Jitter Single Side Band Phase Noise @155.52MHz 1kHz Offset 45 50 55 dBc/Hz Fin=19.44_MHz dBc/Hz Mfin=8, M=x, R=x dBc/Hz ps ps % 325 450 500 ps 20% to 80% 325 450 500 ps 20% to 80% 10kHz Offset 100kHz Offset J(t) Jitter (rms) @155.52MHz odc Output Duty Cycle 2 ±200 ±150 0.5 12kHz to 20MHz 50kHz to 80MHz 0.5 2 tR Output Rise Time for FOUT, nFOUT tF Output Fall Time 2 for FOUT, nFOUT Table 9: AC Characteristics Note 1: Parameters needed for PLL Simulator software; see Table 5, Example Loop Filter Component Values for M1010-01-155.5200 on pg. 4. Note 2: See Parameter Measurement Information on pg. 7. PARAMETER MEASUREMENT INFORMATION Output Rise and Fall Time Output Duty Cycle nFOUT 80% FOUT 80% VP-P Clock Output tPW (Output Pulse Width) 20% tF 20% tR tPERIOD odc = tPW tPERIOD Figure 6: Output Duty Cycle Figure 5: Output Rise and Fall Time M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 7 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 Integrated Circuit Systems, Inc. M1010-01 Preliminary Information VCSO BASED CLOCK JITTER ATTENUATOR DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER Mechanical Dimensions: Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier ORDERING INFORMATION VCSO Freq (MHz) Temperature commercial industrial commercial industrial 155.52 156.25 Order Part Number M1010-01 - 155.5200 M1010-01I 155.5200 M1010-01 - 156.2500 M1010-01I 156.2500 Table 10: Ordering Information Consult ICS for the availability of other VCSO frequencies. Part Number: M1010- 01 - xxx.xxxx Device Number Temperature “ - ” = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) VCSO Frequency (MHz) Consult ICS for available VCSO frequencies Figure 8: Part Numbering Scheme While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M1010-01 Datasheet Rev 0.4 Integrated Circuit Systems, Inc. 8 of 8 ● Communications Modules Revised 29Sep2003 ● w w w. i c s t . c o m ● tel (508) 852-5400