NJU26040-09D SRS TruSurround HD/HD4 Decoder General Description The NJU26040-09D is a digital audio signal processor that provides the function of TruSurround HD/HD4 + FOCUS and WOW HD. The NJU26040-09D processes all sound sources, such as DVD multi channel signals, CD, AM/FM radio, and TV sound into spacious sound of natural virtual surround by TruSurround HD/HD4 + FOCUS and WOW HD. The applications of NJU26040-09D are suitable for front multi-channel and stereo outputs products such as DVD Receivers, AV Amplifiers, TV, radio-cassettes player, Car Audio or ordinary audio products such as small speakers system. Package NJU26040V-09D FEATURES - Software Front Multi channel outputs by SRS TruSurround HD/HD4 technology WOW HD technology is offered to the stereo I/O product. LFE by SRS TruBass-II technology SRS FOCUS technology (FOCUS is possible to use with TruSurround HD/HD4.) SRS Definition technology improves the perception of clarity and acoustic space Dialog Clarity technology Support mono ~ 5.1ch input, 2.0 ~ 5.1ch output. - Hardware 24bit Fixed-point Digital Signal Processing Maximum System Clock Frequency : 38MHz Max. Digital Audio Interface : 3 Input ports / 3 Output ports Power Supply : 3.3V (Input : 5V tolerant) Package : SSOP32 (Pb-Free) Micro computer interface : I2C bus (standard-mode/100kbps, fast-mode/400kbps), 4-Wire Serial Bus (4-Wire: clock, enable, input data, output data) The detail hardware specification is described in the “NJU26040 Series Hardware Data Sheet”. Ver.2009-02-10 -1- NJU26040-09D DSP Block Diagram AD1/SDIN NJU26040-09D AD2/SSX DSP ARITHMETIC UNIT SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE SERIAL AUDIO INTERFACE BCKO PROGRAM CONTROL LRO 24-BIT x 24-BIT MULTIPLIER SDO0 L/R SDI0 ALU SDI1 RESETb SDI2 XI SDO1 C/SW MCK TIMING GENERATOR ADDRESS GENERATION UNIT BCKI SDO2 Ls/Rs XO LRI WDC DATA RAM FIRMWARE RAM MUTEb GPIO PROC. SEL Fig.1-1 NJU26040-09D Block Diagram TruSurround HD/HD4 Decoder SDI0 SDI2 mute SET TASK mode select Input Select SDI1 C/SW input SDI2 Input Select Input Trimmer SDI0 mute Through mode L/R input TruSurround Bypass mode TruSurround mode SDI0 SDI1 SDI2 mute Ls/Rs input Input Select Advanced Bypass mode Master / Channel Trimmer SDI1 L/R C/SW Ls/Rs Fig.1-2 NJU26040-09D Top Level Function Diagram -2- Ver.2009-02-10 NJU26040-09D NJU3555 Ls/Rs Input Trimmer C/SW L out Master / Channel Trimmer L/R R out C out SW out Ls out Rs out Through mode Block Diagram Fig.1-3a NJU26040-09D Function Diagram Ls -3dB L C -3dB R Rs SW -3dB + + + + + + + + + + + + + Lt/Rt input. + Master / Channel Trimmer Ls/Rs Input Trimmer C/SW TruSurround Bypass Trimmer L/R L out R out -3dB Not Lt/Rt input. TruSurround Bypass mode Block Diagram Fig.1-3b NJU26040-09D Function Diagram Ver.2009-02-10 -3- NJU26040-09D C TruSurround Input Trimmer C/SW Input Trimmer Mono to Stereo L/R Ls/Rs Dialog Clarity Ls Surround Level Rs TruSurround C pre Ls pre Rs pre L L pre R R pre SW SW pre TruSurround mode Block Diagram (TruSurround mode) C-ch out disable SW out disable Definition C pre HPF C-ch out enable -3dB + Ls pre HPF Rear out enable Rs pre + R pre + + + + + Focus + Bass Management with TruBass-II(L/R) + + Ls out Definition HPF SW out enable + + Focus Rear out disable Rear out disable L pre C out + SW out enable -6dB + Focus Bass Management with TruBass-II (SW) Master / Channel Trimmer + Rear out enable + Focus Definition SW pre Rs out L out R out SW out SW out disable TruSurround mode Block Diagram (TruSurround mode) Definition SRS + + + + FOCUS + Master / Channel Trimmer + FOCUS Limiter R + Limiter Headroom Gain SW Input Trimmer R TruSurround Input Trimmer L Bass Management with TruBass-II(L/R) TruBass II (for WOW HD Front) L L out R out SW out -6dB Definition Bass Management with TruBass-II (SW) TruSurround mode Block Diagram (WOW HD mode) WOW HD mode TruBass disable input(L/R) SW out disable TSHD mode TBII select LFE TruBass enable TBII select L/R SW out enable HPF output(L/R) TruBass II Front(L/R) Bass Management LPF SW out disable TruBass disable input(SW) output(SW) TBII select L/R TruBass enable TBII select LFE SW out enable TruBass II LFE(SW) Bass Management Fig.1-3c NJU26040-09D Function Diagram -4- Ver.2009-02-10 NJU26040-09D NJU3555 Dialog Clarity Ls/Rs TruSurround Input Trimmer C/SW Input Trimmer Mono to Stereo L/R Reffer to TS input mode If C-ch input not exist then C-ch = (L+R)/2. C C output disable C pre + C input enable L R If Ls/Rs input not exist Ls = (L-R)/2, Rs=(R-L)/2 SW If mono Surround input then Rs = Ls Rs Ls L pre R pre SW pre Rear input enable Ls pre Surround Level Rs pre Rear output disable C-ch out disable SW out disable Definition C pre -3dB FOCUS + Rear out enable Rs pre + + Ls pre + -3dB R pre + Rear out enable SW out enable + + + FOCUS HPF Definition FOCUS -3dB L pre HPF Rear out disable Rear out disable SW pre + C-ch out enable + + Bass Management with TruBass-II(L/R) + SW out enable Bass Management with TruBass-II (SW) -6dB -3dB + + FOCUS Definition + C out Master / Channel Trimmer C HPF Ls out Rs out L out R out SW out SW out disable Advanced Bypass mode Block Diagram Fig.1-3d NJU26040-09D Function Diagram Ver.2009-02-10 -5- NJU26040-09D Pin Configuration VDD 1 32 VSS SDA/SDOUT 2 31 TEST SCL/SCK 3 30 TEST AD1/SDIN 4 29 SEL AD2/SSb 5 28 PROC RESETb 6 27 MUTEb VDD 7 NJU26040-09D 26 WDC VDD 8 SSOP32 25 VDD VSS 9 24 VSS 23 TEST CLKOUT 10 CLK 11 22 MCK SDI2 12 21 SDO2 SDI1 13 20 SDO1 SDI0 14 19 SDO0 LRI 15 18 LRO BCKI 16 17 BCKO Fig.1-4 NJU26040-09D Pin Configuration -6- Ver.2009-02-10 NJU26040-09D NJU3555 Pin Description Table 1. Pin Description Pin No. Symbol I/O 1, 7, 8, 25 VDD - 2 SDA/SDOUT OD 3 SCL/SCK I Power Supply +3.3V I2C I/O / 4-Wire Serial Output This pin requires a pull-up resistance in both I2C bus and 4-Wire serial mode. 2 I C clock / Serial clock 4 AD1/SDIN I I2C Address / Serial In 5 AD2/SSb I I2C Address / Serial Enable 6 RESETb I Reset (RESETb=’Low’ : DSP Reset) 9, 24, 32 VSS - GND 10 CLKOUT O OSC Output 11 CLK I OSC Clock Input 12 SDI2 I Audio Data Input 2 13 SDI1 I Audio Data Input 1 14 SDI0 I Audio Data Input 0 15 LRI I LR Clock Input 16 BCKI I Bit Clock Input 17 BCKO O Bit clock Output 18 LRO O LR clock Output 19 SDO0 O Audio Data Output 0 (L/R) 20 SDO1 O Audio Data Output 1 (C/SW) 21 SDO2 O Audio Data Output 2 (Ls/Rs) 22 MCK O Master Clock Output for A/D, D/A 23, 30, 31 TEST I- for Test 26 WDC OD 27 MUTEb I Master Volume level, After Reset DSP (“1” : 0dB “0” : Mute) 28 PROC I After Reset DSP. ( “1” : Normal “0” : Wait from Command ) 29 SEL I Select I2C or Serial bus ( ‘1’ : Serial / ‘0’ : I2C-Bus) Note : I IO OD I/O+ I/O - Ver.2009-02-10 Description (connected to VSS) Watchdog clock output (open drain output) : Input : Input (Pull-down) : Output : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional (with Pull-up resistance) : Bi-directional (with Pull-down resistance) -7- NJU26040-09D Digital Audio Interface The NJU26040-09D audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified. The NJU26040-09D audio interface provides three data input, SDI0, SDI1, SDI2 and three data outputs, SDO0, SDO1, SDO2 as shown in table 2, table 3 and Fig.2. An audio interface input and output data format become the same data format. Table 2. Pin No. 14 13 12 Table 3. Pin No. 19 20 21 Serial Audio Input Pin Symbol Description Audio Data Input 0 SDI0 (L/R, C/SW, Ls/Rs are selected by the command.) Audio Data Input 1 SDI1 (L/R, C/SW, Ls/Rs are selected by the command.) Audio Data Input 2 SDI2 (L/R, C/SW, Ls/Rs are selected by the command.) Serial Audio Output Pin Symbol Description SDO0 SDO1 SDO2 Audio Data Output 0 L / R Audio Data Output 1 C / SW Audio Data Output 2 Ls / Rs Host Interface The NJU26040-09D can be controlled via Serial Host Interface (SHI) using either of two serial bus formats: I2C bus or 4-Wire serial bus.(Table 4) Data transfers are in 8 bit packets (1 byte) when using either format. Serial Host Interface Pin Description.(Table 5) Table 4. Pin No. 29 Table 5. Pin No. 2 3 4 5 Serial Host Interface Pin Description Symbol Setting Host Interface 2 “Low” I C bus SEL “High” 4-Wire serial bus Serial Host Interface Pin Description Symbol I2C bus Format (I2C bus / Serial) Serial Data Input/Output SDA / SDOUT * (Open Drain Input/Output) SCL / SCK * Serial Clock AD1 / SDIN * I2C bus address Bit1 AD2 / SSb * I2C bus address Bit2 4-Wire Serial bus Format Serial Data Output (Open-Drain Output) Serial Clock Serial Data Input Serial enable Note : SDA /SDOUT pin is a bi-directional open drain. 2 This pin requires a pull-up resistance in both I C bus and 4-Wire serial mode. * When the power supply (VDD= +3.3V) is supplied to NJU26040, these pins become +5.0V Input tolerant. -8- Ver.2009-02-10 NJU26040-09D NJU3555 I2C bus When the NJU26040-09D is configured for I2C bus communication during the Reset initialization sequence. I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26040-09A. The AD1 and AD2 pins can arbitrarily set up an address. The I2C address of AD1/AD2 is decided by connection of AD1/AD2 pins. I2C bus SLAVE Address Table 6. bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 AD2 bit2 0 0 1 1 Slave Address ( 7bit ) Start bit AD1 bit1 0 1 0 1 R/W bit R/W bit0 R/W ACK * SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”. Note : In case of the NJU26040-09D only single-byte transmission is available. The serial host interface 2 supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I C bus data transfer. 4-Wire Serial Interface SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = “High”. SDOUT is Open-drain output in case of SSb = “Low”. SDOUT needs a pull-up resistor when SDOUT is Hi-Z. SSb SCK SDIN bit7 bit6 bit5 bit1 MSB SDOUT Hi-Z bit7 bit0 LSB bit6 bit5 bit1 bit0 Fig. 4 4-Wire Serial Interface Timing unstabl e Hi-Z Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb=”High”. When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”. Ver.2009-02-10 -9- NJU26040-09D Pin setting The NJU26040-09D operates default command setting after resetting the NJU26040-09D. In addition, the NJU26040-09D restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDD or VSS through 3.3kΩ resistance. Table 7. Pin No. Pin setting Symbol 28 PROC 27 MUTEb Setting “High” “Low” “High” “Low” Function The NJU26040-09D operates default setting after reset. The NJU26040-09D does not operate after reset. Sending start command is required for starting operation. Master volume is set 0dB after reset. Master volume is set mute after reset. WatchDog Clock The NJU26040-09D outputs clock pulse through WDC (No.26) pin during normal operation. (Table 8) Table 8. WatchDog Clock Output Cycle WDC Output Cycle (Low/High) Time 85ms The NJU26040-09D generates a clock pulse through the WDC terminal after resetting the NJU26040-09D. The WDC clock is useful to check the status of the NJU26040-09D operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26040-09D. When the WDC clock pulse is lost or not normal clock cycle, the NJU26040-09D does not operate correctly. Then reset the NJU26040-09D and set up the NJU26040-09D again. Note : If input and output of an audio signal stop and an audio interface stops, WDC can’t output. That is because it has controlled based on the signal of an audio interface. - 10 - Ver.2009-02-10 NJU26040-09D NJU3555 NJU26040-09D Command Table Table 9. No. NJU26040-09D Command Command No. Command 1 SET_TASK_CMD 19 RIGHT_SRND_TRIM_CMD 2 AUDIO_FORMAT_CMD 20 TSHD_INPUT_TRIM_CMD 3 SYSTEM_STATE_CMD 21 TSHD_BYPASS_TRIM_CMD 4 SAMPRATE_CMD 22 TSHD_SRND_LEVEL_CMD 5 INPUT_SELECT_CMD 23 DC_CNTRL_CMD 6 TSHD_INPUT_MODE_CMD 24 FC_FRONT_CNTRL_CMD 7 TSHD_OUTPUT_MODE_CMD 25 FC_REAR_CNTRL_CMD 8 DF_SELECT_CMD 26 TB2_FRONT_CNTRL_CMD 9 TB2_SETUP_CMD 27 TB2_LFE_CNTRL_CMD 10 SW_CROSSOVER_FREQ_CMD 28 DF_FRONT_CNTRL_CMD 11 SRS3D_SETUP_CMD 29 DF_CENTER_CNTRL_CMD 12 INPUT_TRIM_CMD 30 SRS3D_SPACE_CNTRL_CMD 13 MASTER_TRIM_CMD 31 SRS3D_CENTER_CNTRL_CMD 14 LEFT_TRIM_CMD 32 LIMITER_CMD 15 RIGHT_TRIM_CMD 33 SOFT_RESET_CMD 16 CENTER_TRIM_CMD 34 WDC_TEST_CMD 17 SUBWOOFER_TRIM_CMD 35 START_CMD 18 LEFT_SRND_TRIM_CMD Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (SRS Labs. Inc.) is required. Ver.2009-02-10 - 11 - NJU26040-09D NJU26040-09D Package Dimensions ( SSOP32, Pb-Free ) 11.0 +0.3 -0.1 0 ~ 10° 32 0.1 - 12 - 0.1 0.15 +0.10 -0.05 +0.10 -0.05 1.15 ± 0.1 0.75 MAX. 0.22 ± 0.1 0.5 ± 0.2 16 0.65 M 0.1 1 7.6 ± 0.3 5.6 ± 0.2 17 Unit : mm Ver.2009-02-10 NJU26040-09D NJU3555 License Information The "TruSurround HD", "TruSurround HD4", “WOW HD”, "Dialog Clarity", "FOCUS" and "TruBass" technology rights incorporated in the NJU26040-09D are owned by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd.. Purchaser of NJU26040-09D must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the NJU26040-09D must be sent to SRS Labs for review. "TruSurround HD", "TruSurround HD4", “WOW HD”, "Dialog Clarity", "FOCUS" and "TruBass" is protected under US and foreign patents issued and/or pending. "TruSurround HD", "TruSurround HD4", “WOW HD”, "Dialog Clarity", "FOCUS", "TruBass", SRS and symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the NJU26040-09D, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. For further information, please contact:: SRS Labs, Inc. 2909 Daimler Street. Santa Ana, CA 92705 USA Tel: 949-442-1070 Fax: 949-852-1099 http://www.srslabs.com [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2009-02-10 - 13 -