TI 8413601RA

SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
•
•
•
•
•
SN54ALS273 . . . J PACKAGE
SN74ALS273 . . . DW OR N PACKAGE
(TOP VIEW)
Contain Eight Flip-Flops With Single-Rail
Outputs
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
description
1D
1Q
CLR
VCC
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
CLK is at either the high or low level, the D input
signal has no effect at the output.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
2D
2Q
3Q
3D
4D
8Q
SN54ALS273 . . . FK PACKAGE
(TOP VIEW)
These octal positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with a direct-clear (CLR) input.
The SN54ALS273 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The SN74ALS273 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
H or L
X
Q0
Copyright  1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
logic symbol†
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
R
11
C1
3
2
1D
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
2D
1D
CLK
11
3
3D
4
1D
1D
C1
5D
8
1D
C1
R
CLR
4D
7
1D
C1
R
6D
13
1D
C1
R
7D
14
1D
C1
R
8D
17
1D
C1
R
18
1D
C1
R
C1
R
R
1
2
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN54ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
recommended operating conditions
SN54ALS273
SN74ALS273
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
High-level output current
–1
– 2.6
mA
IOL
fclock
Low-level output current
12
24
mA
35
MHz
High-level input voltage
2
Clock frequency
0
CLR low
tw
2
Pulse duration
tsu
Set p time before CLK↑
Setup
th
TA
Hold time, data after CLK↑
30
10
CLK high
16.5
14
CLK low
16.5
14
Data
10
10
CLR inactive state
15
15
0
Operating free-air temperature
V
0
10
125
V
ns
ns
0
– 55
V
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
VCC = 4
4.5
5V
IOH = – 1 mA
IOH = – 2.6 mA
VOL
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
ICCH
ICCL
VCC = 5.5 V
VCC = 5.5 V
VOH
SN54ALS273
MIN TYP†
MAX
SN74ALS273
MIN TYP†
MAX
– 1.5
VCC – 2
2.4
– 1.5
UNIT
V
VCC – 2
V
3.3
2.4
0.25
0.4
3.2
0.25
0.4
0.35
0.5
0.1
– 20
0.1
V
mA
20
20
µA
– 0.2
– 0.2
mA
– 112
mA
mA
– 112
– 30
11
20
11
20
19
29
19
29
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
SN54ALS273 SN74ALS273
MIN
fmax
tPHL
tPLH
tPHL
MAX
30
CLR
Any Q
Any Q
CLK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
35
MHz
4
24
4
18
2
20
2
12
3
17
3
15
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
MIN
UNIT
ns
ns
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
Data
Input
tw
th
tsu
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
1.3 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
[0 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
84136012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84136012A
SNJ54ALS
273FK
8413601RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8413601RA
SNJ54ALS273J
8413601SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8413601SA
SNJ54ALS273W
SN54ALS273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54ALS273J
SN74ALS273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS273N
SN74ALS273N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
0 to 70
SN74ALS273NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74ALS273N
SN74ALS273NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273NSRE4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SN74ALS273NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
ALS273
SNJ54ALS273FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
Addendum-Page 1
84136012A
SNJ54ALS
273FK
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
25-Sep-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
SNJ54ALS273J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8413601RA
SNJ54ALS273J
SNJ54ALS273W
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
8413601SA
SNJ54ALS273W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS273, SN74ALS273 :
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
• Catalog: SN74ALS273
• Military: SN54ALS273
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ALS273DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
SN74ALS273NSR
SO
NS
20
2000
330.0
24.4
8.2
13.0
2.5
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALS273DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74ALS273NSR
SO
NS
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
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