PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES Generates 24 output buffer from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps. 2.5V Supply range. Enhanced DDR Output Drive selected by I2C. Available in 48 pin SSOP. BLOCK DIAGRAM DDR0T SDATA SCLK I2C Control DDR0C DDR1T FBOUT VDD2.5 1 2 48 47 N/C VDD2.5 GND DDR0T 3 4 46 45 GND DDR11T DDR0C DDR1T 5 6 44 43 DDR11C DDR10T DDR1C VDD2.5 7 8 42 41 DDR10C VDD2.5 GND DDR2T 9 10 40 39 GND DDR9T DDR2C VDD2.5 11 12 38 37 DDR9C VDD2.5 BUF_IN GND DDR3T 13 14 36 35 PD# GND 34 33 DDR8T DDR8C PLL103-02 • • • • • • • • • PIN CONFIGURATION DDR3C 15 16 VDD2.5 GND 17 18 32 31 VDD2.5 GND DDR4T DDR4C 19 20 30 29 DDR7T DDR7C DDR5T DDR5C 21 22 28 27 DDR6T DDR6C VDD2.5 SDATA 23 24 26 25 GND SCLK DDR1C DDR2T Note: #: Active Low DDR2C DDR3T DDR3C DDR4T BUF_IN DDR4C DDR5T DDR5C DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 Rev.D also has an I2C interface, which can enable or disable each output clock. When power up, all output clocks are enabled (has internal pull up). DDR9C DDR10T DDR10C DDR11T DDR11C PD# 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 1 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS PIN DESCRIPTIONS Name Number Type Description FBOUT 1 O Feedback clock for chipset. BUF_IN 13 I Reference input from chipset. PD 36 I Power Down Control input. When low, it will tri-state all outputs. N/C 48 DDR[0:11]T 4,6,10,15,19, 21,28,30,34, 39,43,45 O These outputs provide True copies of BUF_IN. DDR[0:11]C 5,7,11,16,20, 22,27,29,33, 38,42,44 O These outputs provide complementary copies of BUF_IN. VDD2.5 2,8,12,17,23, 32,37,41,47 P 2.5V power supply. GND 3,9,14,18,26, 31,35,40,46 P Ground. Not connected. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 2 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS I2C BUS CONFIGURATION SETTING Address Assignment Slave Receiver/Transmitter Data Transfer Rate Data Protocol A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 48 1 Reserved Bit 6 - 0 Reserved Bit 5 - 0 Enhanced DDR Drive. 1 = Enhanced 25% Bit 4 - 0 Reserved Bit 3 45, 44 1 DDR11T, DDR11C Bit 2 43, 42 1 DDR10T, DDR10C Bit 1 39, 38 1 DDR9T, DDR9C Bit 0 34, 33 1 DDR8T, DDR8C 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 3 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 2. BYTE 7: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 30, 29 1 DDR7T, DDR7C Bit 6 28, 27 1 DDR6T, DDR6C Bit 5 21, 22 1 DDR5T, DDR5C Bit 4 19, 20 1 DDR4T, DDR4C Bit 3 15, 16 1 DDR3T, DDR3C Bit 2 10, 11 1 DDR2T, DDR2C Bit 1 6, 7 1 DDR1T, DDR1C Bit 0 4, 5 1 DDR0T, DDR0C 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 4 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V DD V SS - 0.5 7.0 V Input Voltage, dc VI V SS - 0.5 V DD + 0.5 V Output Voltage, dc VO V SS - 0.5 V DD + 0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA 0 70 °C 2 KV Supply Voltage ESD Voltage Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Operating Conditions PARAMETERS SYMBOL MIN. MAX. UNITS V DD2.5 2.375 2.625 V C IN 5 pF C OUT 6 pF Supply Voltage Input Capacitance Output Capacitance 3. Electrical Specifications PARAMETERS SYMBOL CONDITIONS Input High Voltage V IH All Inputs except I2C Input Low Voltage V IL All inputs except I2C Input High Current I IH Input Low Current I IL MIN. TYP. MAX. UNITS 2.0 V DD +0.3 V V SS -0.3 0.8 V V IN = V DD TBM uA V IN = 0 TBM uA 1.7 Output High Voltage V OH IOL = -12mA, Output Low Voltage V OL IOL = 12mA, Output High Current I OH VDD = 2.375V, VOUT=1V -18 -32 mA Output Low Current I OL VDD = 2.375V, VOUT=1.2V 26 35 mA VDD = 2.375V V VDD = 2.375V 0.6 V Note: TBM: To be measured 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 5 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 3. Electrical Specifications (Continued) PARAMETERS SYMBOL CONDITIONS MIN. Supply Current I DDS Output Crossing Voltage V OC (VDD/2) -0.1 Output Voltage Swing V OUT 1.1 Duty Cycle DT TYP. PD = 0 Measured @ 1.5V 45 Max. Operating Frequency VDD/2 50 66 MAX. UNITS TBM mA (VDD/2)+ 0.1 V VDD-0.4 V 55 % 170 MHz Rising Edge Rate T OR Measured @ 0.4V ~ 2.4V 1.0 1.5 2.0 V/ns Falling Edge Rate T OF Measured @ 2.4V ~ 0.4V 1.0 1.5 2.0 V/ns Clock Skew ( pin to pin ) T SKEW 100 ps Stabilization Time T ST 0.1 ms All outputs equally loaded Note: TBM: To be measured 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 6 PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS PACKAGE INFORMATION 0.400 - 0.410 0.292 - 0.299 10.160 - 10.414 7.417 - 7.959 0.008 - 0.0135 0.025 0.203 - 0.343 0.835 0.015 (0.381) 0.010 - 0.016 (0.25 - 0.41) 0.620 - 0.630 (15.75 - 16.00) 0.088 - 0.096 (2.250 - 2.450) 45 0 0.097 - 0.104 (2.467 - 2.642) 30-6 0 0.050 MIN (1.346) 0.008 - 0.016 (0.20 - 0.41) 48PIN SSOP ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL103-02 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/11/01 Page 7