PCS3P622S04J May 2007 rev 0.3 Low Frequency Timing-Safe™ Peak EMI reduction IC General Features • with Peak EMI Reduction. PCS3P622S04J accepts one reference input and drives out four low-skew clocks. • Low Frequency Clock Distribution with TimingSafe™ and Peak EMI Reduction Input frequency range: 4MHz - 20MHz • Zero input - output propagation delay and is obtained from the CLKOUT pad, internal to the • Low-skew outputs device. PCS3P622S04J has a crystal oscillator interface. • Output-output skew less than 250pS An inexpensive crystal will provide the clock source for • Device-device skew less than 700pS distribution. It is available in 8 pin TSSOP. PCS3P622S04J has an on-chip PLL that locks to an input clock on the XIN/CLKIN pin. The PLL feedback is on-chip • Less than 200pS Cycle-to-cycle jitter • 3.3V Operation All outputs have less than 200pS of Cycle-to-cycle jitter. • Commercial temperature range The input and output propagation delay is guaranteed to be • Available in 8pin TSSOP(4.4MM-Body) less than 350pS, and the output-to-output skew is • First True Drop-in solution guaranteed to be less than 250pS. Refer “Spread Spectrum Control and Input-Output Skew Product Description Table” for values of deviation and Input-Output Skew PCS3P622S04J is a versatile, 3.3V Zero-delay buffer designed to distribute low frequency Timing-Safe™ clocks Block Diagram VDD CLK1 CLKIN / XIN XOUT Crystal Oscillator PLL CLK2 CLK3 CLKOUT GND PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS3P622S04J May 2007 rev 0.3 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves PCBs etc. These methods are expensive. Spread with a 50% duty cycle and as frequencies increase the spectrum clocking reduces the peak energy by reducing edge rates also get faster. Analysis shows that a square the Q factor of the clock. This is done by slowly wave is composed of fundamental frequency and modulating the clock frequency. PCS3P622S04J uses harmonics. The fundamental frequency and harmonics the center modulation spread spectrum technique in generate the energy peaks that become the source of which the modulated output frequency varies above and EMI. Regulatory agencies test electronic equipment by below measuring the amount of peak energy radiated from the modulation rate. With center modulation, the average equipment. In fact, the peak level allowed decreases as frequency is the same as the unmodulated frequency the frequency increases. The standard methods of and there is no performance degradation the reference frequency with a specified reducing EMI are to use shielding, filtering, multi-layer Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Pin Configuration CLKIN / XIN 1 XOUT 2 8 CLKOUT 7 VDD CLK1 3 6 CLK3 GND 4 5 CLK2 PCS3P622S04J Low Frequency Timing-Sage™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 2 of 10 PCS3P622S04J May 2007 rev 0.3 Pin Description Pin # Pin Name Description 1 XIN/CLKIN 2 XOUT can be connected either to an external crystal or an external reference clock. Crystal connection. If using an external reference, this pin must be left unconnected. 3 CLK1 Buffered clock output 4 GND Ground 5 CLK2 Buffered clock output 6 CLK3 Buffered clock output 7 VDD 8 CLKOUT Crystal connection or external reference frequency input. This pin has dual functions. It 3.3V supply Buffered clock output, internal feedback on this pin Notes: 1. Weak pull-down on all outputs 2. Weak pull-up on the Inputs 3. Buffered clock outputs are Timing-Safe™ Spread Spectrum Control and Input-Output Skew Table Device Input Frequency Deviation Input-Output Skew(±TSKEW) PCS3P622S04J 16MHz ±0.35% 0.375 Note: TSKEW is measured in units of the Clock Period Absolute Maximum Ratings Symbol VDD, VIN TSTG Rating Unit Voltage on any pin with respect to Ground Parameter -0.5 to +4.6 V Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions for PCS3P622S04J Parameter VDD Description Supply Voltage Min Max Unit 3.0 3.6 V 0 +70 °C TA Operating Temperature (Ambient Temperature) CL Load Capacitance 30 pF CIN Input Capacitance 7 pF Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 10 PCS3P622S04J May 2007 rev 0.3 Electrical Characteristics Parameter VIL Description Min Typ Input LOW Voltage 1 VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VOL Test Conditions 1 Max Unit 0.8 V 2.0 2 Output LOW Voltage 2 V VIN = 0V 50 µA VIN = VDD 100 µA IOL = 8mA 0.4 V VOH Output HIGH Voltage IOH = -8mA 2.4 IDD Supply Current Unloaded outputs Zo Output Impedance V 14 mA 23 Ω Note: 1. REF input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics Parameter 1/t1 Description Test Conditions Output Frequency 2 Duty Cycle = (t2 / t1) * 100 t3 t4 t5 t6 Output Rise Time Output Fall Time 1,2 1,2 Output-to-output skew 2 Delay, REF Rising Edge to CLKOUT Rising Edge 2 t7 Device-to-Device Skew 2 tJ Cycle-to-cycle jitter tLOCK PLL Lock Time 2 2 Min Max Unit 20 MHz 60 % Measured between 0.8V and 2.0V 2.5 nS Measured between 2.0V and 0.8V 2.5 nS All outputs equally loaded 250 pS Measured at VDD /2 ±350 pS 700 pS 200 pS 1.0 mS 30pF load 4 Measured at VDD/2 40 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on REF pin Typ 50 Note: 1. All parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 10 PCS3P622S04J May 2007 rev 0.3 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V 2.0 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V OUTPUT1 1.4 V OUTPUT2 t 5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew VDD /2 CLKOUT, Device 1 VDD /2 CLKOUT, Device 2 t 7 Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 10 PCS3P622S04J May 2007 rev 0.3 Input-Output Skew Test Circuit Input Timing-Safe™ Output +3.3V CLKOUT OUTPUT TSKEW - TSKEW+ VDD CLOAD 0.1uF GND One clock cycle N=1 TSKEW represents input-output skew when spread spectrum is ON For example, TSKEW = ± 0.375 for an Input clock16MHz, translates in to (1/16MHz) * 0.375=23.43nS A Typical example of Timing-Safe™ waveform Input Input CLKOUT with SSOFF Timing-Safe™ CLKOUT Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 10 PCS3P622S04J May 2007 rev 0.3 Typical Crystal Oscillator Circuit R1 = 510Ω Crystal C1 = 27 pF C2 = 27 pF Typical Crystal Specifications Fundamental AT cut parallel resonant crystal Nominal frequency 16 MHz Frequency tolerance ± 50 ppm or better at 25°C Operating temperature range -25°C to +85°C Storage temperature -40°C to +85°C Load capacitance 18pF Shunt capacitance 7pF maximum ESR 25 Ω Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 10 PCS3P622S04J May 2007 rev 0.3 Package Information 8-lead Thin Shrunk Small Outline Package (4.40-MM Body) H E D A2 A C θ e A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 0.50 0.70 θ 0° 8° 0° 8° Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 10 PCS3P622S04J May 2007 rev 0.3 Ordering Codes Ordering Code Marking Package Type Temperature PCS3P622S04JG-08-TT 3P622S04JG 8-pin 4.4-mm TSSOP - TUBE, Green Commercial PCS3P622S04JG-08-TR 3P622S04JG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial Device Ordering Information P C S 3 P 6 2 2 S 0 4 J G - 0 8 - T R R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 10 PCS3P622S04J May 2007 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS3P622S04J Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Timing-Safe™ US patent pending © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Frequency Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 10