P1P40167 1.8V, 4-PLL Low Power Clock Generator with Spread Spectrum Functional Description The P1P40167 is a high precision frequency synthesizer designed to operate with a 27 MHz fundamental mode crystal. Device has 4 PLL’s with four LVCMOS outputs and a reference clock. The frequencies generated are 22.5792 MHz, 24.576 MHz, 48 MHz and 37 MHz as well as a 27 MHz copy of the reference clock. Device offers flexible spread spectrum options configurable through I2C bus. All output clocks are generated with high precision, zero PPM frequency conversion, thus making it suitable for high−end multimedia and consumer applications. I2C is included to support various system configuration options. Features • • • • • • • • • Low Power Architecture to Support Portable Applications Integrated Loop Filter Input: 27 MHz Crystal or External Input Outputs: ♦ 27 MHz Reference Output ♦ Fixed Output Frequencies of 48 MHz and 22.5792 MHz ♦ Configurable Spread Spectrum for 37 MHz Output ♦ Selectable Audio Clock Frequency of Either 22.5792 MHz or 24.576 MHz LVCMOS Input and Outputs Supply Voltage: 1.8 V 16−pin QFN Package Operating Temperature Range: −10°C to +80°C These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com MARKING DIAGRAM QFN16 CASE 485G P1P 40167 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (*Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Applications • Portable Gaming • Audio/Video Multimedia VDD 27 MHz clock or Crystal Input VDDO 2 3 Crystal Oscillator 27M PLL1 (SSC) SCLK SDATA I2C Control Logic 37M PLL2 48M PLL3 22/24M PLL4 22M 2 VSS Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2012 August, 2012 − Rev. 1 1 Publication Order Number: P1P40167/D VDD 1 VDD 2 XIN XOUT 27M VSS P1P40167 16 15 14 13 Exposed Pad (EP) 12 VDDO 11 37M P1P40167 4 9 5 6 7 8 22/24M VDD SDATA 10 VDDO SCLK 3 22M 48M VSS Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 VDD Power 1.8 V power supply for Core 2 VDD Power 1.8 V power supply for Core 3 48M Output 48 MHz clock output. Has internal pull down resistor. 4 VDD Power 1.8 V power supply for Core 5 22M Output 22.5792 MHz clock output. Has internal pull down resistor. 6 SCLK Input 7 SDATA Input / Output I2C bus Data pin, Internal pull−up resistor 8 22/24M Output 24.576 MHz or 22.5792 MHz clock output. Has internal pull down resistor. 9 VSS Power 0 V device ground 10 VDDO Power 1.8 V power supply for Output Clocks 11 37M Output 37 MHz clock output. Has internal pull down resistor. 12 VDDO Power 1.8 V power supply for Output Clocks 13 VSS Power 0 V device ground 14 27M Output Buffered 27 MHz reference clock output. Has internal pull down resistor. 15 XOUT Output Crystal connection. If using an external reference, this pin must be left unconnected. 16 XIN Input − EP − I2C bus Clock input, internal pull−up resistor Crystal connection. Connect to 27 MHz crystal or External clock input The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is electrically connected to the die, and can be electrically and thermally connected to device ground on the PC board. http://onsemi.com 2 P1P40167 EXTERNAL COMPONENTS Decoupling Capacitor Crystal Load Capacitors As with any high−performance mixed−signal IC, the P1P40167 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.1 mF must be connected between each VDD and the PCB ground plane. No external crystal load capacitors are required. To save discrete component cost, the P1P40167 integrates on−chip capacitance to support a crystal with CL = 10.5 pF. It is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. I2C External Resistor Connection The SCLK and SDATA pins can be connected to any voltage between 1.8 V and 2.0 V. Table 2. ABSOLUTE MAXIMUM RATING Symbol VDD / VDDO VIN VOUT Parameter Supply Voltage All Inputs All Outputs Rating Unit −0.5 to 3.6 V −0.5 to (VDD + 0.5) V −0.5 to (VDDO + 0.5) V TA Storage Temperature −65 to +150 °C TJ Junction Temperature 125 °C TS Soldering Temperature 260 °C TDV Static Discharge Voltage (As per JEDEC STD22−A114−B) Human Body Model 2000 V Machine Model 200 qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 42 500 lpfm 35 qJC Thermal Resistance (Junction−to−Case) (Note 1) MSL Moisture Sensitivity Level °C/W 4.0 °C/W 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. Table 3. RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Operating Supply Voltage (Output Clocks) 1.7 1.8 2.0 V VDD Operating Supply Voltage (Core) 1.7 1.8 2.0 V TA Ambient Operating Temperature −10 +80 °C VDDO Description http://onsemi.com 3 P1P40167 Table 4. DC ELECTRICAL CHARACTERISTICS Unless stated otherwise, VDD/VDDO = 1.8 V − 0.1 V/+0.2 V, TA = −10°C to +80°C Symbol VDD / VDDO Parameter Conditions Supply Voltage IDD Power Supply Current VIH Input High Voltage Typ 1.7 No Load, VDD, VDDO = 1.8 V, All output clocks running and spread ON 10 Max Unit 2.0 V 12 mA 0.7 x VDD VIL Input Low Voltage VOH Output High Voltage IOH = −2 mA VOL Output Low Voltage IOL = 2 mA CIN Input Capacitance Except XIN, XOUT pins Xtal Load Capacitance XIN, XOUT RPU Internal Pull−up Resistor SCLK, SDATA Pins RPD Internal Pull−down Resistor 22M, 22/24M, 27M, 37M, 48M CLOAD Min V 0.3 x VDD 0.8 x VDDO V V 0.2 x VDDO V 5 pF 10.5 pF 100 500 kW 75 250 kW Table 5. AC ELECTRICAL CHARACTERISTICS (Note 2) (Unless stated otherwise, VDD/VDDO = 1.8 V −0.1 V/+0.2 V, CL = 5 pF, TA = −10°C to +80°C) Symbol Fin TF / TR RO TDC27 Parameter Min Input Frequency Measured between 20% and 80% Output Impedance VO = VDDO /2 Output Clock Duty Cycle 27 MHz output @VDDO/2 45 37 MHz, 48 MHz, 22/24 MHz and 22.5792 MHz clocks @ VDDO/2 45 Freq Synthesis Error Typ Max 27 Output Rise / Fall Time TDC TPJ Conditions 1.1 1.8 MHz 3.3 ns 50 55 % 50 55 % 104 All Outputs Unit W 0 ppm Absolute Clock Period Jitter ±225 ±400 ps TCCJ Cycle to Cycle Jitter 225 375 ps TLTJ1 Long Term Jitter 27 MHz, n = 1000 750 ps TLTJ2 48 MHz, n = 1000 750 ps TLTJ3 22 MHz and 22/24MHz, n=1000 1500 ps 750 ps 15 ms 4.0 ms TLTJ4 TWAIT TPU tOEEN tOEZ 37 MHz with SSOFF n = 20, sample count = 3k 22/24M Clock Switching Time Finish from prior cycle to start of new cycle Power−up Time From minimum VDD to outputs stable Output Enable Time Output Disable Time Measured from rising edge of last I2C 550 1.5 20 ms 22/24M, Measured from rising edge of last I2C clock 150 ms 37M, Measured from rising edge of last I2C clock 1.5 ms 20 ms Measured from rising edge of last I2C Crystal Power clock clock 200 2. Guaranteed by design, not tested in production. http://onsemi.com 4 mW P1P40167 SERIAL DATA INTERFACE Data Protocol complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code as described in the following table. The Clock Driver serial protocol accepts byte write, byte read, block write, and block read operations from the Controller. For Block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any Bit Description 7 0= Block read or Block write operation, 1= Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For Block read or Block write operations, these bits should be ‘0000000’. The Block write and Block read protocol is outlined in the table below, followed by the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Block Write Protocol Bit 1 2:8 Block Read Protocol Description Bit Start 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 46 Command code – 8 bit ‘00000000’ stands for block operation 11:18 Command code – 8 bit ‘00000000’ stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte count – 8 bits 20 Repeat start Acknowledge from slave 21:27 Slave address – 7 bits Data byte 0 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 1 – 8 bits 30:37 Acknowledge from slave 38 39:46 Byte count from slave – 8 bits Acknowledge from master Data byte from slave – 8 bits …... ……………… …... Data byte (N−1) – 8 bits 47 …... Acknowledge from slave 48:55 …... Data byte N – 8 bits 56 Acknowledge from master …... Acknowledge from slave ….. Data byte N from slave – 8 bits …... Stop ….. Not Acknowledge from master …. Stop http://onsemi.com 5 Acknowledge from master Data byte from slave – 8 bits P1P40167 Byte Read Protocol Byte Write Protocol Bit Description 1 Bit Start 2:8 1 Slave addresses – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 2:8 Command code – 8 bit ‘10000000’ stands for byte operation, bits[1:0] command code represents the offset of the byte to be accessed 19 20:27 Description Start Slave addresses – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 Command code – 8 bit ‘10000000’ stands for byte operation bits[1:0] command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte from master − 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 38 39 Data byte from slave – 8 bits Not Acknowledge from master stop Byte 0: Vendor ID, Revision Code Bit @Pup Name Description 7 0 Revision Code (MSB) Revision Code 6 0 Revision Code Revision Code 5 0 Revision Code Revision Code 4 1 Revision Code (LSB) Revision Code 3 1 Vendor ID (MSB) Vendor ID 2 1 Vendor ID Vendor ID 1 0 Vendor ID Vendor ID 0 0 Vendor ID (LSB) Vendor ID Description Byte 1 Controller Register Bit @Pup Name 7 1 27M 27M Output Enable 0 = Disable (Output pulled LOW), 1= Enable 6 1 37M 37M Output Enable 0 = Disable (Output pulled LOW), corresponding PLL shut off. 1= Enable 5 1 48M 48M Output Enable 0 = Disable (Output pulled LOW), 1= Enable 4 1 22/24M 22/24M Clock Output Enable 0 = Disable (Output pulled LOW), 1= Enable 3 0 22M 22M Output Enable 0 = Disable (Output pulled LOW), 1= Enable 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 22/24M SEL 22/24M Clock Select 1= 24.576 MHz, 0= 22.5792MHz http://onsemi.com 6 P1P40167 Byte 2 Controller Register Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 SS Table 1 1 SS Table 0 0 SS Table Bit 2:0 = 000: No Spread Bit 2:0 = 001: − 0.5% Spread Bit 2:0 = 010: − 1.0% Spread Bit 2:0 = 011: No Spread Bit 2:0 = 100: −2.0%Spread Bit 2:0 = 101: No Spread Bit 2:0 = 110: −3.0%Spread Bit 2:0 = 111: No Spread ORDERING INFORMATION Part Number P1P40167MNTWG Package Type Shipping† QFN16 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 P1P40167 PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D PIN 1 LOCATION 2X A B ÇÇÇ ÇÇÇ ÇÇÇ L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉÉ ÉÉÉ EXPOSED Cu 0.10 C TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 0.10 C 2X L (A3) ÉÉ ÉÉ ÇÇ A3 A1 DETAIL B A 0.05 C MOLD CMPD ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 16X L DETAIL A PACKAGE OUTLINE D2 8 4 16X 16X 0.58 0.10 C A B 1 9 2X K 2X 1.84 3.30 E2 1 16X 16 e e/2 BOTTOM VIEW 0.30 16X b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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