SS8061G 1A Low Dropout Regulator with Enable FEATURES DESCRIPTION Adjustable output from 1.2V to 4.8V Output voltage options 1.5V, 1.8V and 2.5V (externally adjustable using resistors) Over-current and over-temperature protection Dropout voltage of 400mV at 1A load Enable pin Quiescent current of 10µA in shutdown SOT-89-5 Package APPLICATIONS Battery-powered systems Motherboards Peripheral cards Network cards Set Top Boxes Medical Equipment Notebook Computers The SS8061 is a high performance positive voltage regulator designed for use in applications requiring very low dropout voltage at up to 1 Amps. Since it has superior dropout characteristics compared to regular LDOs, it can be used to supply 2.5V on motherboards or 1.5V, 1.8V on peripheral cards from the 3.3V supply thus allowing the elimination of costly heatsinks. An enable-pin further reduces power dissipation while in shut-down. The SS8061 provides excellent regulation over variations in line, load and temperature. The SS8061 is available with 1.5V, 1.8V and 2.5V internally preset outputs that are also adjustable using external resistors. ORDERING INFORMATION SS8061-15GTETR SS8061-18GTETR SS8061-25GTETR 1.5V output, in SOT89-5 with Pb-free lead finish, shipped on tape and reel. 1.8V output, in SOT89-5 with Pb-free lead finish, shipped on tape and reel. 2.5V output, in SOT89-5 with Pb-free lead finish, shipped on tape and reel. This device is only available with Pb-free lead finish (second-level interconnect). PIN CONFIGURATION TYPICAL APPLICATION CIRCUIT IENH R3 SS8061G VIN 5 SS8061G VEN VEN VEN VIN VIN 4 VO VO R1 C1 22µF GND ADJ C2 47µF R2 1 2 3 ADJ GND VO SOT-89-5 1.2 (R1+R2) Volts R2 R2=12kΩ is recommended VO = R3 should be connected for current IENH restriction as VEN > VIN+0.3V 1/21/2005 Rev.2.01 www.SiliconStandard.com 1 of 6 SS8061G ABSOLUTE MAXIMUM RATINGS Input Voltage……………………………………………..7V VEN Voltage…………..…………………………..VIN+0.3V Power Dissipation Internally Limited (Note 2) Maximum Junction Temperature…………………150°C Storage Temperature Range……..-65°C ≤TJ ≤ +150°C Reflow Temperature (soldering, 10sec)……..….260°C Thermal Resistance Junction to Ambient…..…177°C/W Thermal Resistance Junction to Case………..…52°C/W ESD Rating (Human Body Model)…………..………2kV OPERATING CONDITIONS (note 1) Input Voltage………………………………….2.2V ~5.5V Temperature Range………….………-40°C ≤TA ≤ +85°C ELECTRICAL CHARACTERISTICS VEN=VIN, VIN =5V, IO = 0.5A, CIN = 4.7µF, COUT =10µF, TA = TJ = 25°C unless otherwise specified (Note 3) PARAMETER SYMBOL Supply Voltage VIN Output Voltage VO CONDITION VIN=VO +0.7V, IO=10mA MIN TYP MAX UNIT 2.2 -2 --VO 5.5 2 V % Line Regulation VO+0.7V < VIN < 5.5V, IO=10mA --- 0.2 2 % Load Regulation 10mA < IO < 1A VIN=3.3V,VEN=VIN ----- 0.8 1.7 2 2.5 % mA VIN=3.3V,VEN=0V fi=120Hz, 1VP-P, IO=100mA ----- 16 55 35 --- µA dB IO=1A ------- 0.4 0.8 150 0.6 ----- V A °C Quiescent Current IQ Ripple Rejection Dropout Voltage Short Circuit Current Over Temperature VD VEN Voltage High VENH Output Active 1.6 --- --- V VEN Voltage Low VEN Bias Current Low VENL IENL Output Disabled VEN=0.4V ----- ----- 0.4 20 V µA ADJ Reference Voltage ADJ Pin Threshold VREF VIN=2.2V, VADJ=VOUT, IO=10mA 1.188 --- 1.2 0.2 1.212 --- V V Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Conditions are conditions under which the device functions but the specifications might not be guaranteed. For guaranteed specifications and test conditions see the Electrical Characteristics. Note2: The maximum power dissipation is a function of the maximum junction temperature, TJmax; total thermal resistance, θJA, and ambient temperature TA. The maximum allowable power dissipation at any ambient temperature is (Tjmax-TA) / θJA. If this dissipation is exceeded, the die temperature will rise above 150°C and IC will go into thermal shutdown. Note3: Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Note4: The type of output capacitor should be tantalum or aluminum. Definitions Dropout Voltage The input/output Voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 2% below its nominal value, dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Line Regulation The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. 1/21/2005 Rev.2.01 Load Regulation The change in output voltage for a change in load current at constant chip temperature. The measurement is made under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. Maximum Power Dissipation The maximum total device dissipation for which the regulator will operate within specifications. Quiescent Bias Current Current which is used to operate the regulator chip and is not delivered to the load. www.SiliconStandard.com 2 of 6 SS8061G TYPICAL PERFORMANCE CHARACTERISTICS VEN=VIN, VIN =5V, IO = 0.5A, CIN = 4.7µF, COUT =10µF, TA = TJ = 25°C (VOUT=1.8V) Line Transient Response Load Transient Response Short Circuit Current Ripple Rejection 60 IL=10mA Ripple Rejection (dB) 50 IL=1A 40 IL=500mA 30 20 VIN=4V COUT=10µF Vripple=224mV 10 0 10 100 1000 10000 100000 1000000 Frequency (Hz) Overcurrent Protection Characteristics 1/21/2005 Rev.2.01 www.SiliconStandard.com Start-up 3 of 6 SS8061G TYPICAL PERFORMANCE CHARACTERISTICS (continued) Max. Power Dissipation vs. PCB Top Copper Area 1.8 Max. Power Dissipation vs. TAMB 1.8 Max. Dissipation Power (W) Max. Dissipation Power (W) Unit:in 1.6 1.6 1.4 1.2 1 0.8 0.6 0.4 A=0.2 1.4 A=0.5 A=1.0 A=1.5 0.8 A=2.0 0.6 A=2.5 0.4 A=3.5 0 0 2 3 4 PCB Top Copper Area (in2) A=0.4 1 0.2 1 A=0.3 1.2 0.2 0 A=3.0 A=4.0 A=4.5 A=5.0 25 5 Quiescent Current vs. Temperature 45 65 (°C) 75 85 Dropout Voltage vs. IL 600 1.85 Dropout Voltage (mV) 1.90 VIN=5.0V 1.80 1.75 VIN=3.0V 1.70 1.65 1.60 500 400 T=85°C T=25°C 300 200 T=-25°C 100 1.55 0 1.50 -25 -15 -5 5 0 15 25 35 45 55 65 75 85 200 Temperature (°C) 400 600 IL (mA) 800 1000 Output Voltage vs. VIN Output Voltage vs. Temperature 1.824 1.825 1.819 IL=10mA 1.82 1.814 Output Voltage (V) Output Voltage (V) 55 700 1.95 Quiescent Current (mA) 35 TAMB 2.00 VIN=5.0V 1.809 1.804 VIN=3.0V 1.799 1.794 T=85°C 1.815 T=25°C 1.81 1.805 1.789 T=-25°C 1.8 1.784 -25 -15 -5 1/21/2005 Rev.2.01 2 A=0.1 5 15 25 35 45 55 65 75 85 Temperature (°C) 2.5 3.5 www.SiliconStandard.com 4.5 5.5 VIN (V) 6.5 4 of 6 SS8061G RECOMMENDED MINIMUM FOOTPRINT SOT-89-5 1/21/2005 Rev.2.01 www.SiliconStandard.com 5 of 6 SS8061G PHYSICAL DIMENSIONS SOT-89-5 A C D F L E B I K H J G DIMENSION IN MM MIN MAX DIMENSION IN INCH MIN MAX A 4.40 4.60 0.173 0.181 B C 4.05 1.50 4.25 1.70 0.159 0.059 0.167 0.067 D E 1.30 2.40 1.50 2.60 0.051 0.094 0.059 0.102 F 0.80 ----- 0.031 SYMBOL G H I J K L 3.00 REF 1.50 REF 0.40 1.40 0.35 ----0.118 REF 0.059 REF 0.52 1.60 0.41 0.016 0.055 0.014 5º TYP 0.020 0.063 0.016 5º TYP Taping Specification PACKAGE Q’TY/REEL SOT-89-5 1,000 ea Feed Direction SOT-89-5 Package Orientation Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 1/21/2005 Rev.2.01 www.SiliconStandard.com 6 of 6